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Varun Wadekar0f3baa02015-07-16 11:36:33 +05301/*
Varun Wadekar84a775e2019-01-03 10:12:55 -08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekar7cf57d72018-05-17 09:36:38 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar0f3baa02015-07-16 11:36:33 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar0f3baa02015-07-16 11:36:33 +05306 */
7
Varun Wadekarb7b45752015-12-28 14:55:41 -08008#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <common/bl_common.h>
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070010#include <drivers/console.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/xlat_tables/xlat_tables_v2.h>
Ambroise Vincentffbf32a2019-03-28 09:01:18 +000012#include <plat/common/platform.h>
Varun Wadekar0f3baa02015-07-16 11:36:33 +053013#include <tegra_def.h>
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070014#include <tegra_platform.h>
Varun Wadekarb7b45752015-12-28 14:55:41 -080015#include <tegra_private.h>
Varun Wadekar0f3baa02015-07-16 11:36:33 +053016
Varun Wadekar0f3baa02015-07-16 11:36:33 +053017/* sets of MMIO ranges setup */
18#define MMIO_RANGE_0_ADDR 0x50000000
19#define MMIO_RANGE_1_ADDR 0x60000000
20#define MMIO_RANGE_2_ADDR 0x70000000
21#define MMIO_RANGE_SIZE 0x200000
22
23/*
24 * Table of regions to map using the MMU.
25 */
26static const mmap_region_t tegra_mmap[] = {
27 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
28 MT_DEVICE | MT_RW | MT_SECURE),
29 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
30 MT_DEVICE | MT_RW | MT_SECURE),
31 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
32 MT_DEVICE | MT_RW | MT_SECURE),
33 {0}
34};
35
36/*******************************************************************************
37 * Set up the pagetables as per the platform memory map & initialize the MMU
38 ******************************************************************************/
39const mmap_region_t *plat_get_mmio_map(void)
40{
41 /* MMIO space */
42 return tegra_mmap;
43}
44
Varun Wadekare34bc3d2017-04-28 08:43:33 -070045/*******************************************************************************
46 * The Tegra power domain tree has a single system level power domain i.e. a
47 * single root node. The first entry in the power domain descriptor specifies
48 * the number of power domains at the highest power level.
49 *******************************************************************************
50 */
51const unsigned char tegra_power_domain_tree_desc[] = {
52 /* No of root nodes */
53 1,
54 /* No of clusters */
55 PLATFORM_CLUSTER_COUNT,
56 /* No of CPU cores */
57 PLATFORM_CORE_COUNT,
58};
59
60/*******************************************************************************
61 * This function returns the Tegra default topology tree information.
62 ******************************************************************************/
63const unsigned char *plat_get_power_domain_tree_desc(void)
64{
65 return tegra_power_domain_tree_desc;
66}
67
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010068unsigned int plat_get_syscnt_freq2(void)
Varun Wadekar0f3baa02015-07-16 11:36:33 +053069{
70 return 12000000;
71}
Varun Wadekard2014c62015-10-29 10:37:28 +053072
73/*******************************************************************************
74 * Maximum supported UART controllers
75 ******************************************************************************/
76#define TEGRA132_MAX_UART_PORTS 5
77
78/*******************************************************************************
79 * This variable holds the UART port base addresses
80 ******************************************************************************/
81static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
82 0, /* undefined - treated as an error case */
83 TEGRA_UARTA_BASE,
84 TEGRA_UARTB_BASE,
85 TEGRA_UARTC_BASE,
86 TEGRA_UARTD_BASE,
87 TEGRA_UARTE_BASE,
88};
89
90/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070091 * Enable console corresponding to the console ID
Varun Wadekard2014c62015-10-29 10:37:28 +053092 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070093void plat_enable_console(int32_t id)
Varun Wadekard2014c62015-10-29 10:37:28 +053094{
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070095 static console_16550_t uart_console;
96 uint32_t console_clock;
97
98 if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) {
99 /*
100 * Reference clock used by the FPGAs is a lot slower.
101 */
102 if (tegra_platform_is_fpga()) {
103 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
104 } else {
105 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
106 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530107
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700108 (void)console_16550_register(tegra132_uart_addresses[id],
109 console_clock,
110 TEGRA_CONSOLE_BAUDRATE,
111 &uart_console);
112 console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
113 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
114 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530115}
Varun Wadekarb7b45752015-12-28 14:55:41 -0800116
117/*******************************************************************************
118 * Initialize the GIC and SGIs
119 ******************************************************************************/
120void plat_gic_setup(void)
121{
122 tegra_gic_setup(NULL, 0);
Varun Wadekar84a775e2019-01-03 10:12:55 -0800123 tegra_gic_init();
Varun Wadekarb7b45752015-12-28 14:55:41 -0800124}
Varun Wadekar7cf57d72018-05-17 09:36:38 -0700125
126/*******************************************************************************
127 * Return pointer to the BL31 params from previous bootloader
128 ******************************************************************************/
129struct tegra_bl31_params *plat_get_bl31_params(void)
130{
131 return NULL;
132}
133
134/*******************************************************************************
135 * Return pointer to the BL31 platform params from previous bootloader
136 ******************************************************************************/
137plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
138{
139 return NULL;
140}
141
142/*******************************************************************************
143 * Handler for early platform setup
144 ******************************************************************************/
145void plat_early_platform_setup(void)
146{
147 ; /* do nothing */
148}
149
150/*******************************************************************************
151 * Handler for late platform setup
152 ******************************************************************************/
153void plat_late_platform_setup(void)
154{
155 ; /* do nothing */
156}