blob: cd439ad6fd05b98eb260244cf3223ffa2f978724 [file] [log] [blame]
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001Secure Partition Manager
2************************
3
4.. contents::
5
Olivier Deprez3de57e32022-04-28 18:18:36 +02006.. toctree::
7 ffa-manifest-binding
8
Olivier Deprezecb2fe52020-04-02 15:38:02 +02009Acronyms
10========
11
Olivier Deprez2b0be752021-09-01 10:25:21 +020012+--------+--------------------------------------+
13| CoT | Chain of Trust |
14+--------+--------------------------------------+
15| DMA | Direct Memory Access |
16+--------+--------------------------------------+
17| DTB | Device Tree Blob |
18+--------+--------------------------------------+
19| DTS | Device Tree Source |
20+--------+--------------------------------------+
21| EC | Execution Context |
22+--------+--------------------------------------+
23| FIP | Firmware Image Package |
24+--------+--------------------------------------+
25| FF-A | Firmware Framework for Arm A-profile |
26+--------+--------------------------------------+
27| IPA | Intermediate Physical Address |
28+--------+--------------------------------------+
Olivier Deprez3de57e32022-04-28 18:18:36 +020029| JOP | Jump-Oriented Programming |
30+--------+--------------------------------------+
Olivier Deprez2b0be752021-09-01 10:25:21 +020031| NWd | Normal World |
32+--------+--------------------------------------+
33| ODM | Original Design Manufacturer |
34+--------+--------------------------------------+
35| OEM | Original Equipment Manufacturer |
36+--------+--------------------------------------+
37| PA | Physical Address |
38+--------+--------------------------------------+
39| PE | Processing Element |
40+--------+--------------------------------------+
41| PM | Power Management |
42+--------+--------------------------------------+
43| PVM | Primary VM |
44+--------+--------------------------------------+
Olivier Deprez3de57e32022-04-28 18:18:36 +020045| ROP | Return-Oriented Programming |
46+--------+--------------------------------------+
Olivier Deprez2b0be752021-09-01 10:25:21 +020047| SMMU | System Memory Management Unit |
48+--------+--------------------------------------+
49| SP | Secure Partition |
50+--------+--------------------------------------+
51| SPD | Secure Payload Dispatcher |
52+--------+--------------------------------------+
53| SPM | Secure Partition Manager |
54+--------+--------------------------------------+
55| SPMC | SPM Core |
56+--------+--------------------------------------+
57| SPMD | SPM Dispatcher |
58+--------+--------------------------------------+
59| SiP | Silicon Provider |
60+--------+--------------------------------------+
61| SWd | Secure World |
62+--------+--------------------------------------+
63| TLV | Tag-Length-Value |
64+--------+--------------------------------------+
65| TOS | Trusted Operating System |
66+--------+--------------------------------------+
67| VM | Virtual Machine |
68+--------+--------------------------------------+
Olivier Deprezecb2fe52020-04-02 15:38:02 +020069
70Foreword
71========
72
Olivier Deprez3de57e32022-04-28 18:18:36 +020073Three implementations of a Secure Partition Manager co-exist in the TF-A
74codebase:
Olivier Deprezecb2fe52020-04-02 15:38:02 +020075
Olivier Deprez3de57e32022-04-28 18:18:36 +020076#. S-EL2 SPMC based on the FF-A specification `[1]`_, enabling virtualization in
77 the secure world, managing multiple S-EL1 or S-EL0 partitions.
78#. EL3 SPMC based on the FF-A specification, managing a single S-EL1 partition
79 without virtualization in the secure world.
80#. EL3 SPM based on the MM specification, legacy implementation managing a
81 single S-EL0 partition `[2]`_.
Olivier Deprezecb2fe52020-04-02 15:38:02 +020082
Olivier Deprez3de57e32022-04-28 18:18:36 +020083These implementations differ in their respective SW architecture and only one
84can be selected at build time. This document:
Olivier Deprezecb2fe52020-04-02 15:38:02 +020085
Olivier Deprez3de57e32022-04-28 18:18:36 +020086- describes the implementation from bullet 1. when the SPMC resides at S-EL2.
Olivier Deprez5e0a73f2021-04-30 14:42:24 +020087- is not an architecture specification and it might provide assumptions
88 on sections mandated as implementation-defined in the specification.
Olivier Deprez3de57e32022-04-28 18:18:36 +020089- covers the implications to TF-A used as a bootloader, and Hafnium used as a
90 reference code base for an S-EL2/SPMC secure firmware on platforms
91 implementing the FEAT_SEL2 architecture extension.
Olivier Deprezecb2fe52020-04-02 15:38:02 +020092
93Terminology
94-----------
95
Olivier Deprez5e0a73f2021-04-30 14:42:24 +020096- The term Hypervisor refers to the NS-EL2 component managing Virtual Machines
97 (or partitions) in the normal world.
98- The term SPMC refers to the S-EL2 component managing secure partitions in
99 the secure world when the FEAT_SEL2 architecture extension is implemented.
100- Alternatively, SPMC can refer to an S-EL1 component, itself being a secure
101 partition and implementing the FF-A ABI on platforms not implementing the
102 FEAT_SEL2 architecture extension.
103- The term VM refers to a normal world Virtual Machine managed by an Hypervisor.
104- The term SP refers to a secure world "Virtual Machine" managed by an SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200105
106Support for legacy platforms
107----------------------------
108
Olivier Deprez3de57e32022-04-28 18:18:36 +0200109The SPM is split into a dispatcher and a core component (respectively SPMD and
110SPMC) residing at different exception levels. To permit the FF-A specification
111adoption and a smooth migration, the SPMD supports an SPMC residing either at
112S-EL1 or S-EL2:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200113
Olivier Deprez3de57e32022-04-28 18:18:36 +0200114- The SPMD is located at EL3 and mainly relays the FF-A protocol from NWd
115 (Hypervisor or OS kernel) to the SPMC.
116- The same SPMD component is used for both S-EL1 and S-EL2 SPMC configurations.
117- The SPMC exception level is a build time choice.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200118
Olivier Deprez3de57e32022-04-28 18:18:36 +0200119TF-A supports both cases:
120
121- S-EL1 SPMC for platforms not supporting the FEAT_SEL2 architecture
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200122 extension. The SPMD relays the FF-A protocol from EL3 to S-EL1.
Olivier Deprez3de57e32022-04-28 18:18:36 +0200123- S-EL2 SPMC for platforms implementing the FEAT_SEL2 architecture
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200124 extension. The SPMD relays the FF-A protocol from EL3 to S-EL2.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200125
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200126Sample reference stack
127======================
128
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200129The following diagram illustrates a possible configuration when the
130FEAT_SEL2 architecture extension is implemented, showing the SPMD
131and SPMC, one or multiple secure partitions, with an optional
132Hypervisor:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200133
134.. image:: ../resources/diagrams/ff-a-spm-sel2.png
135
136TF-A build options
137==================
138
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200139This section explains the TF-A build options involved in building with
140support for an FF-A based SPM where the SPMD is located at EL3 and the
Marc Bonniciabaac162021-12-01 18:00:40 +0000141SPMC located at S-EL1, S-EL2 or EL3:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200142
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200143- **SPD=spmd**: this option selects the SPMD component to relay the FF-A
144 protocol from NWd to SWd back and forth. It is not possible to
145 enable another Secure Payload Dispatcher when this option is chosen.
146- **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC exception
Marc Bonniciabaac162021-12-01 18:00:40 +0000147 level to being at S-EL2. It defaults to enabled (value 1) when
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200148 SPD=spmd is chosen.
Marc Bonniciabaac162021-12-01 18:00:40 +0000149- **SPMC_AT_EL3**: this option adjusts the SPMC exception level to being
150 at EL3.
Olivier Deprez3de57e32022-04-28 18:18:36 +0200151- If neither ``SPMD_SPM_AT_SEL2`` or ``SPMC_AT_EL3`` are enabled the SPMC
Marc Bonniciabaac162021-12-01 18:00:40 +0000152 exception level is set to S-EL1.
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200153- **CTX_INCLUDE_EL2_REGS**: this option permits saving (resp.
154 restoring) the EL2 system register context before entering (resp.
155 after leaving) the SPMC. It is mandatorily enabled when
156 ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine
157 and exhaustive list of registers is visible at `[4]`_.
158- **SP_LAYOUT_FILE**: this option specifies a text description file
159 providing paths to SP binary images and manifests in DTS format
160 (see `Describing secure partitions`_). It
161 is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple
Olivier Deprez3de57e32022-04-28 18:18:36 +0200162 secure partitions are to be loaded by BL2 on behalf of the SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200163
Marc Bonniciabaac162021-12-01 18:00:40 +0000164+---------------+----------------------+------------------+-------------+
165| | CTX_INCLUDE_EL2_REGS | SPMD_SPM_AT_SEL2 | SPMC_AT_EL3 |
166+---------------+----------------------+------------------+-------------+
167| SPMC at S-EL1 | 0 | 0 | 0 |
168+---------------+----------------------+------------------+-------------+
169| SPMC at S-EL2 | 1 | 1 (default when | 0 |
170| | | SPD=spmd) | |
171+---------------+----------------------+------------------+-------------+
172| SPMC at EL3 | 0 | 0 | 1 |
173+---------------+----------------------+------------------+-------------+
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200174
175Other combinations of such build options either break the build or are not
176supported.
177
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200178Notes:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200179
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200180- Only Arm's FVP platform is supported to use with the TF-A reference software
181 stack.
Olivier Deprez3de57e32022-04-28 18:18:36 +0200182- When ``SPMD_SPM_AT_SEL2=1``, the reference software stack assumes enablement
183 of FEAT_PAuth, FEAT_BTI and FEAT_MTE architecture extensions.
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200184- The ``CTX_INCLUDE_EL2_REGS`` option provides the generic support for
185 barely saving/restoring EL2 registers from an Arm arch perspective. As such
186 it is decoupled from the ``SPD=spmd`` option.
187- BL32 option is re-purposed to specify the SPMC image. It can specify either
188 the Hafnium binary path (built for the secure world) or the path to a TEE
189 binary implementing FF-A interfaces.
190- BL33 option can specify the TFTF binary or a normal world loader
Olivier Deprez3de57e32022-04-28 18:18:36 +0200191 such as U-Boot or the UEFI framework payload.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200192
Olivier Deprez3de57e32022-04-28 18:18:36 +0200193Sample TF-A build command line when the SPMC is located at S-EL1
194(e.g. when the FEAT_SEL2 architecture extension is not implemented):
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200195
196.. code:: shell
197
198 make \
199 CROSS_COMPILE=aarch64-none-elf- \
200 SPD=spmd \
201 SPMD_SPM_AT_SEL2=0 \
202 BL32=<path-to-tee-binary> \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200203 BL33=<path-to-bl33-binary> \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200204 PLAT=fvp \
205 all fip
206
Olivier Deprez3de57e32022-04-28 18:18:36 +0200207Sample TF-A build command line when FEAT_SEL2 architecture extension is
208implemented and the SPMC is located at S-EL2:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200209.. code:: shell
210
211 make \
212 CROSS_COMPILE=aarch64-none-elf- \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200213 PLAT=fvp \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200214 SPD=spmd \
215 CTX_INCLUDE_EL2_REGS=1 \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200216 ARM_ARCH_MINOR=5 \
217 BRANCH_PROTECTION=1 \
218 CTX_INCLUDE_PAUTH_REGS=1 \
Olivier Deprez3de57e32022-04-28 18:18:36 +0200219 CTX_INCLUDE_MTE_REGS=1 \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200220 BL32=<path-to-hafnium-binary> \
221 BL33=<path-to-bl33-binary> \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200222 SP_LAYOUT_FILE=sp_layout.json \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200223 all fip
224
Olivier Deprez3de57e32022-04-28 18:18:36 +0200225Sample TF-A build command line when FEAT_SEL2 architecture extension is
226implemented, the SPMC is located at S-EL2, and enabling secure boot:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200227.. code:: shell
228
229 make \
230 CROSS_COMPILE=aarch64-none-elf- \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200231 PLAT=fvp \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200232 SPD=spmd \
233 CTX_INCLUDE_EL2_REGS=1 \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200234 ARM_ARCH_MINOR=5 \
235 BRANCH_PROTECTION=1 \
236 CTX_INCLUDE_PAUTH_REGS=1 \
Olivier Deprez3de57e32022-04-28 18:18:36 +0200237 CTX_INCLUDE_MTE_REGS=1 \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200238 BL32=<path-to-hafnium-binary> \
239 BL33=<path-to-bl33-binary> \
240 SP_LAYOUT_FILE=sp_layout.json \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200241 MBEDTLS_DIR=<path-to-mbedtls-lib> \
242 TRUSTED_BOARD_BOOT=1 \
243 COT=dualroot \
244 ARM_ROTPK_LOCATION=devel_rsa \
245 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
246 GENERATE_COT=1 \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200247 all fip
248
Olivier Deprez3de57e32022-04-28 18:18:36 +0200249Sample TF-A build command line when the SPMC is located at EL3:
Marc Bonniciabaac162021-12-01 18:00:40 +0000250
251.. code:: shell
252
253 make \
254 CROSS_COMPILE=aarch64-none-elf- \
255 SPD=spmd \
256 SPMD_SPM_AT_SEL2=0 \
257 SPMC_AT_EL3=1 \
258 BL32=<path-to-tee-binary> \
259 BL33=<path-to-bl33-binary> \
260 PLAT=fvp \
261 all fip
262
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200263FVP model invocation
264====================
265
266The FVP command line needs the following options to exercise the S-EL2 SPMC:
267
268+---------------------------------------------------+------------------------------------+
269| - cluster0.has_arm_v8-5=1 | Implements FEAT_SEL2, FEAT_PAuth, |
270| - cluster1.has_arm_v8-5=1 | and FEAT_BTI. |
271+---------------------------------------------------+------------------------------------+
272| - pci.pci_smmuv3.mmu.SMMU_AIDR=2 | Parameters required for the |
273| - pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B | SMMUv3.2 modeling. |
274| - pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 | |
275| - pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 | |
276| - pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 | |
277| - pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 | |
278| - pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 | |
279| - pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 | |
280+---------------------------------------------------+------------------------------------+
281| - cluster0.has_branch_target_exception=1 | Implements FEAT_BTI. |
282| - cluster1.has_branch_target_exception=1 | |
283+---------------------------------------------------+------------------------------------+
Olivier Deprez3de57e32022-04-28 18:18:36 +0200284| - cluster0.has_pointer_authentication=2 | Implements FEAT_PAuth |
285| - cluster1.has_pointer_authentication=2 | |
286+---------------------------------------------------+------------------------------------+
287| - cluster0.memory_tagging_support_level=2 | Implements FEAT_MTE2 |
288| - cluster1.memory_tagging_support_level=2 | |
289| - bp.dram_metadata.is_enabled=1 | |
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200290+---------------------------------------------------+------------------------------------+
291
292Sample FVP command line invocation:
293
294.. code:: shell
295
Olivier Deprez3de57e32022-04-28 18:18:36 +0200296 <path-to-fvp-model>/FVP_Base_RevC-2xAEMvA -C pctl.startup=0.0.0.0 \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200297 -C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \
298 -C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \
299 -C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \
300 -C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \
301 -C bp.pl011_uart2.out_file=fvp-uart2.log \
Olivier Deprez3de57e32022-04-28 18:18:36 +0200302 -C cluster0.has_arm_v8-5=1 -C cluster1.has_arm_v8-5=1 \
303 -C cluster0.has_pointer_authentication=2 -C cluster1.has_pointer_authentication=2 \
304 -C cluster0.has_branch_target_exception=1 -C cluster1.has_branch_target_exception=1 \
305 -C cluster0.memory_tagging_support_level=2 -C cluster1.memory_tagging_support_level=2 \
306 -C bp.dram_metadata.is_enabled=1 \
307 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B \
308 -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 \
309 -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 \
310 -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200311
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200312Boot process
313============
314
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200315Loading Hafnium and secure partitions in the secure world
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200316---------------------------------------------------------
317
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200318TF-A BL2 is the bootlader for the SPMC and SPs in the secure world.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200319
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200320SPs may be signed by different parties (SiP, OEM/ODM, TOS vendor, etc.).
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200321Thus they are supplied as distinct signed entities within the FIP flash
322image. The FIP image itself is not signed hence this provides the ability
323to upgrade SPs in the field.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200324
325Booting through TF-A
326--------------------
327
328SP manifests
329~~~~~~~~~~~~
330
331An SP manifest describes SP attributes as defined in `[1]`_
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200332(partition manifest at virtual FF-A instance) in DTS format. It is
333represented as a single file associated with the SP. A sample is
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200334provided by `[5]`_. A binding document is provided by `[6]`_.
335
336Secure Partition packages
337~~~~~~~~~~~~~~~~~~~~~~~~~
338
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200339Secure partitions are bundled as independent package files consisting
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200340of:
341
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200342- a header
343- a DTB
344- an image payload
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200345
346The header starts with a magic value and offset values to SP DTB and
347image payload. Each SP package is loaded independently by BL2 loader
348and verified for authenticity and integrity.
349
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200350The SP package identified by its UUID (matching FF-A uuid property) is
351inserted as a single entry into the FIP at end of the TF-A build flow
352as shown:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200353
354.. code:: shell
355
356 Trusted Boot Firmware BL2: offset=0x1F0, size=0x8AE1, cmdline="--tb-fw"
357 EL3 Runtime Firmware BL31: offset=0x8CD1, size=0x13000, cmdline="--soc-fw"
358 Secure Payload BL32 (Trusted OS): offset=0x1BCD1, size=0x15270, cmdline="--tos-fw"
359 Non-Trusted Firmware BL33: offset=0x30F41, size=0x92E0, cmdline="--nt-fw"
360 HW_CONFIG: offset=0x3A221, size=0x2348, cmdline="--hw-config"
361 TB_FW_CONFIG: offset=0x3C569, size=0x37A, cmdline="--tb-fw-config"
362 SOC_FW_CONFIG: offset=0x3C8E3, size=0x48, cmdline="--soc-fw-config"
363 TOS_FW_CONFIG: offset=0x3C92B, size=0x427, cmdline="--tos-fw-config"
364 NT_FW_CONFIG: offset=0x3CD52, size=0x48, cmdline="--nt-fw-config"
365 B4B5671E-4A90-4FE1-B81F-FB13DAE1DACB: offset=0x3CD9A, size=0xC168, cmdline="--blob"
366 D1582309-F023-47B9-827C-4464F5578FC8: offset=0x48F02, size=0xC168, cmdline="--blob"
367
368.. uml:: ../resources/diagrams/plantuml/fip-secure-partitions.puml
369
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200370Describing secure partitions
371~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200372
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200373A json-formatted description file is passed to the build flow specifying paths
374to the SP binary image and associated DTS partition manifest file. The latter
375is processed by the dtc compiler to generate a DTB fed into the SP package.
J-Alvescfc6e232022-05-24 12:13:08 +0100376Optionally, the partition's json description can contain offsets for both
377the image and partition manifest within the SP package. Both offsets need to be
3784KB aligned, because it is the translation granule supported by Hafnium SPMC.
379These fields can be leveraged to support SPs with S1 translation granules that
380differ from 4KB, and to configure the regions allocated within the SP package,
381as well as to comply with the requirements for the implementation of the boot
382information protocol (see `Passing boot data to the SP`_ for more details). In
383case the offsets are absent in their json node, they default to 0x1000 and
3840x4000 for the manifest offset and image offset respectively.
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200385This file also specifies the SP owner (as an optional field) identifying the
386signing domain in case of dual root CoT.
387The SP owner can either be the silicon or the platform provider. The
388corresponding "owner" field value can either take the value of "SiP" or "Plat".
389In absence of "owner" field, it defaults to "SiP" owner.
Imre Kis3f370fd2022-02-08 18:06:18 +0100390The UUID of the partition can be specified as a field in the description file or
391if it does not exist there the UUID is extracted from the DTS partition
392manifest.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200393
394.. code:: shell
395
396 {
397 "tee1" : {
398 "image": "tee1.bin",
Manish Pandey77870962020-08-12 17:06:25 +0100399 "pm": "tee1.dts",
Imre Kis3f370fd2022-02-08 18:06:18 +0100400 "owner": "SiP",
401 "uuid": "1b1820fe-48f7-4175-8999-d51da00b7c9f"
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200402 },
403
404 "tee2" : {
405 "image": "tee2.bin",
Manish Pandey77870962020-08-12 17:06:25 +0100406 "pm": "tee2.dts",
407 "owner": "Plat"
J-Alvescfc6e232022-05-24 12:13:08 +0100408 },
409
410 "tee3" : {
411 "image": {
412 "file": "tee3.bin",
413 "offset":"0x2000"
414 },
415 "pm": {
416 "file": "tee3.dts",
417 "offset":"0x6000"
418 },
419 "owner": "Plat"
420 },
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200421 }
422
423SPMC manifest
424~~~~~~~~~~~~~
425
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200426This manifest contains the SPMC *attribute* node consumed by the SPMD at boot
427time. It implements `[1]`_ (SP manifest at physical FF-A instance) and serves
428two different cases:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200429
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200430- The SPMC resides at S-EL1: the SPMC manifest is used by the SPMD to setup a
431 SP that co-resides with the SPMC and executes at S-EL1 or Secure Supervisor
432 mode.
433- The SPMC resides at S-EL2: the SPMC manifest is used by the SPMD to setup
434 the environment required by the SPMC to run at S-EL2. SPs run at S-EL1 or
435 S-EL0.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200436
437.. code:: shell
438
439 attribute {
440 spmc_id = <0x8000>;
441 maj_ver = <0x1>;
Olivier Deprez3de57e32022-04-28 18:18:36 +0200442 min_ver = <0x1>;
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200443 exec_state = <0x0>;
444 load_address = <0x0 0x6000000>;
445 entrypoint = <0x0 0x6000000>;
446 binary_size = <0x60000>;
447 };
448
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200449- *spmc_id* defines the endpoint ID value that SPMC can query through
450 ``FFA_ID_GET``.
451- *maj_ver/min_ver*. SPMD checks provided version versus its internal
452 version and aborts if not matching.
453- *exec_state* defines the SPMC execution state (AArch64 or AArch32).
454 Notice Hafnium used as a SPMC only supports AArch64.
455- *load_address* and *binary_size* are mostly used to verify secondary
456 entry points fit into the loaded binary image.
457- *entrypoint* defines the cold boot primary core entry point used by
458 SPMD (currently matches ``BL32_BASE``) to enter the SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200459
460Other nodes in the manifest are consumed by Hafnium in the secure world.
Olivier Deprez3de57e32022-04-28 18:18:36 +0200461A sample can be found at `[7]`_:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200462
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200463- The *hypervisor* node describes SPs. *is_ffa_partition* boolean attribute
464 indicates a FF-A compliant SP. The *load_address* field specifies the load
Olivier Deprez3de57e32022-04-28 18:18:36 +0200465 address at which BL2 loaded the SP package.
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200466- *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping.
Olivier Deprez3de57e32022-04-28 18:18:36 +0200467 Note the primary core is declared first, then secondary cores are declared
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200468 in reverse order.
469- The *memory* node provides platform information on the ranges of memory
470 available to the SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200471
472SPMC boot
473~~~~~~~~~
474
475The SPMC is loaded by BL2 as the BL32 image.
476
Olivier Deprez4ab7a4a2021-06-21 09:47:13 +0200477The SPMC manifest is loaded by BL2 as the ``TOS_FW_CONFIG`` image `[9]`_.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200478
479BL2 passes the SPMC manifest address to BL31 through a register.
480
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200481At boot time, the SPMD in BL31 runs from the primary core, initializes the core
Olivier Deprez4ab7a4a2021-06-21 09:47:13 +0200482contexts and launches the SPMC (BL32) passing the following information through
483registers:
484
485- X0 holds the ``TOS_FW_CONFIG`` physical address (or SPMC manifest blob).
486- X1 holds the ``HW_CONFIG`` physical address.
487- X4 holds the currently running core linear id.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200488
489Loading of SPs
490~~~~~~~~~~~~~~
491
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200492At boot time, BL2 loads SPs sequentially in addition to the SPMC as depicted
493below:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200494
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200495.. uml:: ../resources/diagrams/plantuml/bl2-loading-sp.puml
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200496
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200497Note this boot flow is an implementation sample on Arm's FVP platform.
498Platforms not using TF-A's *Firmware CONFiguration* framework would adjust to a
Olivier Deprez3de57e32022-04-28 18:18:36 +0200499different boot flow. The flow restricts to a maximum of 8 secure partitions.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200500
501Secure boot
502~~~~~~~~~~~
503
504The SP content certificate is inserted as a separate FIP item so that BL2 loads SPMC,
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200505SPMC manifest, secure partitions and verifies them for authenticity and integrity.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200506Refer to TBBR specification `[3]`_.
507
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200508The multiple-signing domain feature (in current state dual signing domain `[8]`_) allows
509the use of two root keys namely S-ROTPK and NS-ROTPK:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200510
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200511- SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK.
512- BL33 may be signed by the OEM using NS-ROTPK.
513- An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK).
Olivier Deprez3de57e32022-04-28 18:18:36 +0200514- A maximum of 4 partitions can be signed with the S-ROTPK key and 4 partitions
515 signed with the NS-ROTPK key.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200516
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200517Also refer to `Describing secure partitions`_ and `TF-A build options`_ sections.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200518
519Hafnium in the secure world
520===========================
521
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200522General considerations
523----------------------
524
525Build platform for the secure world
526~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
527
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200528In the Hafnium reference implementation specific code parts are only relevant to
529the secure world. Such portions are isolated in architecture specific files
530and/or enclosed by a ``SECURE_WORLD`` macro.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200531
Olivier Deprez3de57e32022-04-28 18:18:36 +0200532Secure partitions scheduling
533~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200534
Olivier Deprez3de57e32022-04-28 18:18:36 +0200535The FF-A specification `[1]`_ provides two ways to relinquinsh CPU time to
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200536secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200537
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200538- the FFA_MSG_SEND_DIRECT_REQ interface.
539- the FFA_RUN interface.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200540
Olivier Deprez3de57e32022-04-28 18:18:36 +0200541Additionally a secure interrupt can pre-empt the normal world execution and give
542CPU cycles by transitioning to EL3 and S-EL2.
543
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200544Platform topology
545~~~~~~~~~~~~~~~~~
546
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200547The *execution-ctx-count* SP manifest field can take the value of one or the
Olivier Deprez3de57e32022-04-28 18:18:36 +0200548total number of PEs. The FF-A specification `[1]`_ recommends the
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200549following SP types:
550
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200551- Pinned MP SPs: an execution context matches a physical PE. MP SPs must
552 implement the same number of ECs as the number of PEs in the platform.
553- Migratable UP SPs: a single execution context can run and be migrated on any
554 physical PE. Such SP declares a single EC in its SP manifest. An UP SP can
555 receive a direct message request originating from any physical core targeting
556 the single execution context.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200557
558Parsing SP partition manifests
559------------------------------
560
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200561Hafnium consumes SP manifests as defined in `[1]`_ and `SP manifests`_.
562Note the current implementation may not implement all optional fields.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200563
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200564The SP manifest may contain memory and device regions nodes. In case of
565an S-EL2 SPMC:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200566
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200567- Memory regions are mapped in the SP EL1&0 Stage-2 translation regime at
568 load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can
569 specify RX/TX buffer regions in which case it is not necessary for an SP
570 to explicitly invoke the ``FFA_RXTX_MAP`` interface.
571- Device regions are mapped in the SP EL1&0 Stage-2 translation regime (or
572 EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate
573 additional resources (e.g. interrupts).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200574
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200575For the S-EL2 SPMC, base addresses for memory and device region nodes are IPAs
576provided the SPMC identity maps IPAs to PAs within SP EL1&0 Stage-2 translation
577regime.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200578
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200579Note: in the current implementation both VTTBR_EL2 and VSTTBR_EL2 point to the
580same set of page tables. It is still open whether two sets of page tables shall
581be provided per SP. The memory region node as defined in the specification
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200582provides a memory security attribute hinting to map either to the secure or
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200583non-secure EL1&0 Stage-2 table if it exists.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200584
585Passing boot data to the SP
586---------------------------
587
J-Alvescfc6e232022-05-24 12:13:08 +0100588In `[1]`_ , the section "Boot information protocol" defines a method for passing
589data to the SPs at boot time. It specifies the format for the boot information
590descriptor and boot information header structures, which describe the data to be
591exchanged between SPMC and SP.
592The specification also defines the types of data that can be passed.
593The aggregate of both the boot info structures and the data itself is designated
594the boot information blob, and is passed to a Partition as a contiguous memory
595region.
596
597Currently, the SPM implementation supports the FDT type which is used to pass the
598partition's DTB manifest.
599
600The region for the boot information blob is allocated through the SP package.
601
602.. image:: ../resources/diagrams/partition-package.png
603
604To adjust the space allocated for the boot information blob, the json description
605of the SP (see section `Describing secure partitions`_) shall be updated to contain
606the manifest offset. If no offset is provided the manifest offset defaults to 0x1000,
607which is the page size in the Hafnium SPMC.
608
609The configuration of the boot protocol is done in the SPs manifest. As defined by
610the specification, the manifest field 'gp-register-num' configures the GP register
611which shall be used to pass the address to the partitions boot information blob when
612booting the partition.
613In addition, the Hafnium SPMC implementation requires the boot information arguments
614to be listed in a designated DT node:
615
616.. code:: shell
617
618 boot-info {
619 compatible = "arm,ffa-manifest-boot-info";
620 ffa_manifest;
621 };
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200622
J-Alvescfc6e232022-05-24 12:13:08 +0100623The whole secure partition package image (see `Secure Partition packages`_) is
624mapped to the SP secure EL1&0 Stage-2 translation regime. As such, the SP can
625retrieve the address for the boot information blob in the designated GP register,
626process the boot information header and descriptors, access its own manifest
627DTB blob and extract its partition manifest properties.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200628
629SP Boot order
630-------------
631
632SP manifests provide an optional boot order attribute meant to resolve
633dependencies such as an SP providing a service required to properly boot
J-Alves855fc882021-12-14 16:02:27 +0000634another SP. SPMC boots the SPs in accordance to the boot order attribute,
635lowest to the highest value. If the boot order attribute is absent from the FF-A
636manifest, the SP is treated as if it had the highest boot order value
637(i.e. lowest booting priority).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200638
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200639It is possible for an SP to call into another SP through a direct request
640provided the latter SP has already been booted.
641
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200642Boot phases
643-----------
644
645Primary core boot-up
646~~~~~~~~~~~~~~~~~~~~
647
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200648Upon boot-up, BL31 hands over to the SPMC (BL32) on the primary boot physical
649core. The SPMC performs its platform initializations and registers the SPMC
650secondary physical core entry point physical address by the use of the
J-Alvesc9ca31c2021-10-04 14:33:51 +0100651`FFA_SECONDARY_EP_REGISTER`_ interface (SMC invocation from the SPMC to the SPMD
652at secure physical FF-A instance).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200653
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200654The SPMC then creates secure partitions based on SP packages and manifests. Each
655secure partition is launched in sequence (`SP Boot order`_) on their "primary"
656execution context. If the primary boot physical core linear id is N, an MP SP is
657started using EC[N] on PE[N] (see `Platform topology`_). If the partition is a
658UP SP, it is started using its unique EC0 on PE[N].
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200659
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200660The SP primary EC (or the EC used when the partition is booted as described
661above):
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200662
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200663- Performs the overall SP boot time initialization, and in case of a MP SP,
664 prepares the SP environment for other execution contexts.
665- In the case of a MP SP, it invokes the FFA_SECONDARY_EP_REGISTER at secure
666 virtual FF-A instance (SMC invocation from SP to SPMC) to provide the IPA
667 entry point for other execution contexts.
668- Exits through ``FFA_MSG_WAIT`` to indicate successful initialization or
669 ``FFA_ERROR`` in case of failure.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200670
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200671Secondary cores boot-up
672~~~~~~~~~~~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200673
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200674Once the system is started and NWd brought up, a secondary physical core is
675woken up by the ``PSCI_CPU_ON`` service invocation. The TF-A SPD hook mechanism
676calls into the SPMD on the newly woken up physical core. Then the SPMC is
677entered at the secondary physical core entry point.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200678
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200679In the current implementation, the first SP is resumed on the coresponding EC
680(the virtual CPU which matches the physical core). The implication is that the
681first SP must be a MP SP.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200682
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200683In a linux based system, once secure and normal worlds are booted but prior to
684a NWd FF-A driver has been loaded:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200685
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200686- The first SP has initialized all its ECs in response to primary core boot up
687 (at system initialization) and secondary core boot up (as a result of linux
688 invoking PSCI_CPU_ON for all secondary cores).
689- Other SPs have their first execution context initialized as a result of secure
690 world initialization on the primary boot core. Other ECs for those SPs have to
691 be run first through ffa_run to complete their initialization (which results
692 in the EC completing with FFA_MSG_WAIT).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200693
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200694Refer to `Power management`_ for further details.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200695
J-Alvesc9ca31c2021-10-04 14:33:51 +0100696Notifications
697-------------
698
699The FF-A v1.1 specification `[1]`_ defines notifications as an asynchronous
700communication mechanism with non-blocking semantics. It allows for one FF-A
701endpoint to signal another for service provision, without hindering its current
702progress.
703
704Hafnium currently supports 64 notifications. The IDs of each notification define
705a position in a 64-bit bitmap.
706
707The signaling of notifications can interchangeably happen between NWd and SWd
708FF-A endpoints.
709
710The SPMC is in charge of managing notifications from SPs to SPs, from SPs to
711VMs, and from VMs to SPs. An hypervisor component would only manage
712notifications from VMs to VMs. Given the SPMC has no visibility of the endpoints
713deployed in NWd, the Hypervisor or OS kernel must invoke the interface
714FFA_NOTIFICATION_BITMAP_CREATE to allocate the notifications bitmap per FF-A
715endpoint in the NWd that supports it.
716
717A sender can signal notifications once the receiver has provided it with
718permissions. Permissions are provided by invoking the interface
719FFA_NOTIFICATION_BIND.
720
721Notifications are signaled by invoking FFA_NOTIFICATION_SET. Henceforth
722they are considered to be in a pending sate. The receiver can retrieve its
723pending notifications invoking FFA_NOTIFICATION_GET, which, from that moment,
724are considered to be handled.
725
726Per the FF-A v1.1 spec, each FF-A endpoint must be associated with a scheduler
727that is in charge of donating CPU cycles for notifications handling. The
728FF-A driver calls FFA_NOTIFICATION_INFO_GET to retrieve the information about
729which FF-A endpoints have pending notifications. The receiver scheduler is
730called and informed by the FF-A driver, and it should allocate CPU cycles to the
731receiver.
732
733There are two types of notifications supported:
Olivier Deprez3de57e32022-04-28 18:18:36 +0200734
J-Alvesc9ca31c2021-10-04 14:33:51 +0100735- Global, which are targeted to a FF-A endpoint and can be handled within any of
Olivier Deprez3de57e32022-04-28 18:18:36 +0200736 its execution contexts, as determined by the scheduler of the system.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100737- Per-vCPU, which are targeted to a FF-A endpoint and to be handled within a
Olivier Deprez3de57e32022-04-28 18:18:36 +0200738 a specific execution context, as determined by the sender.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100739
740The type of a notification is set when invoking FFA_NOTIFICATION_BIND to give
741permissions to the sender.
742
743Notification signaling resorts to two interrupts:
J-Alvesc9ca31c2021-10-04 14:33:51 +0100744
Olivier Deprez3de57e32022-04-28 18:18:36 +0200745- Schedule Receiver Interrupt: non-secure physical interrupt to be handled by
746 the FF-A driver within the receiver scheduler. At initialization the SPMC
747 donates a SGI ID chosen from the secure SGI IDs range and configures it as
748 non-secure. The SPMC triggers this SGI on the currently running core when
749 there are pending notifications, and the respective receivers need CPU cycles
750 to handle them.
751- Notifications Pending Interrupt: virtual interrupt to be handled by the
752 receiver of the notification. Set when there are pending notifications for the
753 given secure partition. The NPI is pended when the NWd relinquishes CPU cycles
754 to an SP.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100755
Olivier Deprez3de57e32022-04-28 18:18:36 +0200756The notifications receipt support is enabled in the partition FF-A manifest.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100757
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200758Mandatory interfaces
759--------------------
760
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200761The following interfaces are exposed to SPs:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200762
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200763- ``FFA_VERSION``
764- ``FFA_FEATURES``
765- ``FFA_RX_RELEASE``
766- ``FFA_RXTX_MAP``
J-Alvesc9ca31c2021-10-04 14:33:51 +0100767- ``FFA_RXTX_UNMAP``
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200768- ``FFA_PARTITION_INFO_GET``
769- ``FFA_ID_GET``
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200770- ``FFA_MSG_WAIT``
771- ``FFA_MSG_SEND_DIRECT_REQ``
772- ``FFA_MSG_SEND_DIRECT_RESP``
773- ``FFA_MEM_DONATE``
774- ``FFA_MEM_LEND``
775- ``FFA_MEM_SHARE``
776- ``FFA_MEM_RETRIEVE_REQ``
777- ``FFA_MEM_RETRIEVE_RESP``
778- ``FFA_MEM_RELINQUISH``
Olivier Deprez3de57e32022-04-28 18:18:36 +0200779- ``FFA_MEM_FRAG_RX``
780- ``FFA_MEM_FRAG_TX``
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200781- ``FFA_MEM_RECLAIM``
Olivier Deprez3de57e32022-04-28 18:18:36 +0200782- ``FFA_RUN``
J-Alvesc9ca31c2021-10-04 14:33:51 +0100783
Olivier Deprez3de57e32022-04-28 18:18:36 +0200784As part of the FF-A v1.1 support, the following interfaces were added:
J-Alvesc9ca31c2021-10-04 14:33:51 +0100785
786 - ``FFA_NOTIFICATION_BITMAP_CREATE``
787 - ``FFA_NOTIFICATION_BITMAP_DESTROY``
788 - ``FFA_NOTIFICATION_BIND``
789 - ``FFA_NOTIFICATION_UNBIND``
790 - ``FFA_NOTIFICATION_SET``
791 - ``FFA_NOTIFICATION_GET``
792 - ``FFA_NOTIFICATION_INFO_GET``
793 - ``FFA_SPM_ID_GET``
794 - ``FFA_SECONDARY_EP_REGISTER``
Olivier Deprez3de57e32022-04-28 18:18:36 +0200795 - ``FFA_MEM_PERM_GET``
796 - ``FFA_MEM_PERM_SET``
J-Alves4256a272022-10-26 13:46:37 +0100797 - ``FFA_MSG_SEND2``
798 - ``FFA_RX_ACQUIRE``
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200799
800FFA_VERSION
801~~~~~~~~~~~
802
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200803``FFA_VERSION`` requires a *requested_version* parameter from the caller.
804The returned value depends on the caller:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200805
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200806- Hypervisor or OS kernel in NS-EL1/EL2: the SPMD returns the SPMC version
807 specified in the SPMC manifest.
808- SP: the SPMC returns its own implemented version.
809- SPMC at S-EL1/S-EL2: the SPMD returns its own implemented version.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200810
811FFA_FEATURES
812~~~~~~~~~~~~
813
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200814FF-A features supported by the SPMC may be discovered by secure partitions at
815boot (that is prior to NWd is booted) or run-time.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200816
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200817The SPMC calling FFA_FEATURES at secure physical FF-A instance always get
818FFA_SUCCESS from the SPMD.
819
820The request made by an Hypervisor or OS kernel is forwarded to the SPMC and
821the response relayed back to the NWd.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200822
823FFA_RXTX_MAP/FFA_RXTX_UNMAP
824~~~~~~~~~~~~~~~~~~~~~~~~~~~
825
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200826When invoked from a secure partition FFA_RXTX_MAP maps the provided send and
827receive buffers described by their IPAs to the SP EL1&0 Stage-2 translation
828regime as secure buffers in the MMU descriptors.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200829
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200830When invoked from the Hypervisor or OS kernel, the buffers are mapped into the
831SPMC EL2 Stage-1 translation regime and marked as NS buffers in the MMU
J-Alves4256a272022-10-26 13:46:37 +0100832descriptors. The provided addresses may be owned by a VM in the normal world,
833which is expected to receive messages from the secure world. The SPMC will in
834this case allocate internal state structures to facilitate RX buffer access
835synchronization (through FFA_RX_ACQUIRE interface), and to permit SPs to send
836messages.
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200837
J-Alvesc9ca31c2021-10-04 14:33:51 +0100838The FFA_RXTX_UNMAP unmaps the RX/TX pair from the translation regime of the
839caller, either it being the Hypervisor or OS kernel, as well as a secure
840partition.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200841
842FFA_PARTITION_INFO_GET
843~~~~~~~~~~~~~~~~~~~~~~
844
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200845Partition info get call can originate:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200846
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200847- from SP to SPMC
848- from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200849
850FFA_ID_GET
851~~~~~~~~~~
852
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200853The FF-A id space is split into a non-secure space and secure space:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200854
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200855- FF-A ID with bit 15 clear relates to VMs.
856- FF-A ID with bit 15 set related to SPs.
857- FF-A IDs 0, 0xffff, 0x8000 are assigned respectively to the Hypervisor, SPMD
858 and SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200859
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200860The SPMD returns:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200861
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200862- The default zero value on invocation from the Hypervisor.
863- The ``spmc_id`` value specified in the SPMC manifest on invocation from
864 the SPMC (see `SPMC manifest`_)
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200865
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200866This convention helps the SPMC to determine the origin and destination worlds in
867an FF-A ABI invocation. In particular the SPMC shall filter unauthorized
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200868transactions in its world switch routine. It must not be permitted for a VM to
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200869use a secure FF-A ID as origin world by spoofing:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200870
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200871- A VM-to-SP direct request/response shall set the origin world to be non-secure
872 (FF-A ID bit 15 clear) and destination world to be secure (FF-A ID bit 15
873 set).
874- Similarly, an SP-to-SP direct request/response shall set the FF-A ID bit 15
875 for both origin and destination IDs.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200876
877An incoming direct message request arriving at SPMD from NWd is forwarded to
878SPMC without a specific check. The SPMC is resumed through eret and "knows" the
879message is coming from normal world in this specific code path. Thus the origin
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200880endpoint ID must be checked by SPMC for being a normal world ID.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200881
882An SP sending a direct message request must have bit 15 set in its origin
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200883endpoint ID and this can be checked by the SPMC when the SP invokes the ABI.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200884
885The SPMC shall reject the direct message if the claimed world in origin endpoint
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200886ID is not consistent:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200887
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200888- It is either forwarded by SPMD and thus origin endpoint ID must be a "normal
889 world ID",
890- or initiated by an SP and thus origin endpoint ID must be a "secure world ID".
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200891
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200892
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200893FFA_MSG_SEND_DIRECT_REQ/FFA_MSG_SEND_DIRECT_RESP
894~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200895
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200896This is a mandatory interface for secure partitions consisting in direct request
897and responses with the following rules:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200898
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200899- An SP can send a direct request to another SP.
900- An SP can receive a direct request from another SP.
901- An SP can send a direct response to another SP.
902- An SP cannot send a direct request to an Hypervisor or OS kernel.
903- An Hypervisor or OS kernel can send a direct request to an SP.
904- An SP can send a direct response to an Hypervisor or OS kernel.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200905
J-Alvesc9ca31c2021-10-04 14:33:51 +0100906FFA_NOTIFICATION_BITMAP_CREATE/FFA_NOTIFICATION_BITMAP_DESTROY
907~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
908
909The secure partitions notifications bitmap are statically allocated by the SPMC.
910Hence, this interface is not to be issued by secure partitions.
911
912At initialization, the SPMC is not aware of VMs/partitions deployed in the
913normal world. Hence, the Hypervisor or OS kernel must use both ABIs for SPMC
914to be prepared to handle notifications for the provided VM ID.
915
916FFA_NOTIFICATION_BIND/FFA_NOTIFICATION_UNBIND
917~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
918
919Pair of interfaces to manage permissions to signal notifications. Prior to
920handling notifications, an FF-A endpoint must allow a given sender to signal a
921bitmap of notifications.
922
923If the receiver doesn't have notification support enabled in its FF-A manifest,
924it won't be able to bind notifications, hence forbidding it to receive any
925notifications.
926
927FFA_NOTIFICATION_SET/FFA_NOTIFICATION_GET
928~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
929
Olivier Deprez3de57e32022-04-28 18:18:36 +0200930FFA_NOTIFICATION_GET retrieves all pending global notifications and
931per-vCPU notifications targeted to the current vCPU.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100932
Olivier Deprez3de57e32022-04-28 18:18:36 +0200933Hafnium maintains a global count of pending notifications which gets incremented
934and decremented when handling FFA_NOTIFICATION_SET and FFA_NOTIFICATION_GET
935respectively. A delayed SRI is triggered if the counter is non-zero when the
936SPMC returns to normal world.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100937
938FFA_NOTIFICATION_INFO_GET
939~~~~~~~~~~~~~~~~~~~~~~~~~
940
Olivier Deprez3de57e32022-04-28 18:18:36 +0200941Hafnium maintains a global count of pending notifications whose information
942has been retrieved by this interface. The count is incremented and decremented
943when handling FFA_NOTIFICATION_INFO_GET and FFA_NOTIFICATION_GET respectively.
944It also tracks notifications whose information has been retrieved individually,
J-Alvesc9ca31c2021-10-04 14:33:51 +0100945such that it avoids duplicating returned information for subsequent calls to
946FFA_NOTIFICATION_INFO_GET. For each notification, this state information is
947reset when receiver called FFA_NOTIFICATION_GET to retrieve them.
948
949FFA_SPM_ID_GET
950~~~~~~~~~~~~~~
951
Olivier Deprez3de57e32022-04-28 18:18:36 +0200952Returns the FF-A ID allocated to an SPM component which can be one of SPMD
953or SPMC.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100954
Olivier Deprez3de57e32022-04-28 18:18:36 +0200955At initialization, the SPMC queries the SPMD for the SPMC ID, using the
956FFA_ID_GET interface, and records it. The SPMC can also query the SPMD ID using
957the FFA_SPM_ID_GET interface at the secure physical FF-A instance.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100958
Olivier Deprez3de57e32022-04-28 18:18:36 +0200959Secure partitions call this interface at the virtual FF-A instance, to which
960the SPMC returns the priorly retrieved SPMC ID.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100961
Olivier Deprez3de57e32022-04-28 18:18:36 +0200962The Hypervisor or OS kernel can issue the FFA_SPM_ID_GET call handled by the
963SPMD, which returns the SPMC ID.
J-Alvesc9ca31c2021-10-04 14:33:51 +0100964
965FFA_SECONDARY_EP_REGISTER
966~~~~~~~~~~~~~~~~~~~~~~~~~
967
968When the SPMC boots, all secure partitions are initialized on their primary
969Execution Context.
970
Olivier Deprez3de57e32022-04-28 18:18:36 +0200971The FFA_SECONDARY_EP_REGISTER interface is to be used by a secure partition
J-Alvesc9ca31c2021-10-04 14:33:51 +0100972from its first execution context, to provide the entry point address for
973secondary execution contexts.
974
975A secondary EC is first resumed either upon invocation of PSCI_CPU_ON from
976the NWd or by invocation of FFA_RUN.
977
J-Alves4256a272022-10-26 13:46:37 +0100978FFA_RX_ACQUIRE/FFA_RX_RELEASE
979~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
980
981The RX buffers can be used to pass information to an FF-A endpoint in the
982following scenarios:
983
984 - When it was targetted by a FFA_MSG_SEND2 invokation from another endpoint.
985 - Return the result of calling ``FFA_PARTITION_INFO_GET``.
986 - In a memory share operation, as part of the ``FFA_MEM_RETRIEVE_RESP``,
987 with the memory descriptor of the shared memory.
988
989If a normal world VM is expected to exchange messages with secure world,
990its RX/TX buffer addresses are forwarded to the SPMC via FFA_RXTX_MAP ABI,
991and are from this moment owned by the SPMC.
992The hypervisor must call the FFA_RX_ACQUIRE interface before attempting
993to use the RX buffer, in any of the aforementioned scenarios. A successful
994call to FFA_RX_ACQUIRE transfers ownership of RX buffer to hypervisor, such
995that it can be safely used.
996
997The FFA_RX_RELEASE interface is used after the FF-A endpoint is done with
998processing the data received in its RX buffer. If the RX buffer has been
999acquired by the hypervisor, the FFA_RX_RELEASE call must be forwarded to
1000the SPMC to reestablish SPMC's RX ownership.
1001
1002An attempt from an SP to send a message to a normal world VM whose RX buffer
1003was acquired by the hypervisor fails with error code FFA_BUSY, to preserve
1004the RX buffer integrity.
1005The operation could then be conducted after FFA_RX_RELEASE.
1006
1007FFA_MSG_SEND2
1008~~~~~~~~~~~~~
1009
1010Hafnium copies a message from the sender TX buffer into receiver's RX buffer.
1011For messages from SPs to VMs, operation is only possible if the SPMC owns
1012the receiver's RX buffer.
1013
1014Both receiver and sender need to enable support for indirect messaging,
1015in their respective partition manifest. The discovery of support
1016of such feature can be done via FFA_PARTITION_INFO_GET.
1017
1018On a successful message send, Hafnium pends an RX buffer full framework
1019notification for the receiver, to inform it about a message in the RX buffer.
1020
1021The handling of framework notifications is similar to that of
1022global notifications. Binding of these is not necessary, as these are
1023reserved to be used by the hypervisor or SPMC.
1024
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001025SPMC-SPMD direct requests/responses
1026-----------------------------------
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001027
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001028Implementation-defined FF-A IDs are allocated to the SPMC and SPMD.
1029Using those IDs in source/destination fields of a direct request/response
1030permits SPMD to SPMC communication and either way.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001031
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001032- SPMC to SPMD direct request/response uses SMC conduit.
1033- SPMD to SPMC direct request/response uses ERET conduit.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001034
Olivier Deprez3de57e32022-04-28 18:18:36 +02001035This is used in particular to convey power management messages.
1036
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001037PE MMU configuration
1038--------------------
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001039
Olivier Deprez3de57e32022-04-28 18:18:36 +02001040With secure virtualization enabled (``HCR_EL2.VM = 1``) and for S-EL1
1041partitions, two IPA spaces (secure and non-secure) are output from the
1042secure EL1&0 Stage-1 translation.
1043The EL1&0 Stage-2 translation hardware is fed by:
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001044
Olivier Deprez3de57e32022-04-28 18:18:36 +02001045- A secure IPA when the SP EL1&0 Stage-1 MMU is disabled.
1046- One of secure or non-secure IPA when the secure EL1&0 Stage-1 MMU is enabled.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001047
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001048``VTCR_EL2`` and ``VSTCR_EL2`` provide configuration bits for controlling the
Olivier Deprez3de57e32022-04-28 18:18:36 +02001049NS/S IPA translations. The following controls are set up:
1050``VSTCR_EL2.SW = 0`` , ``VSTCR_EL2.SA = 0``, ``VTCR_EL2.NSW = 0``,
1051``VTCR_EL2.NSA = 1``:
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001052
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001053- Stage-2 translations for the NS IPA space access the NS PA space.
1054- Stage-2 translation table walks for the NS IPA space are to the secure PA space.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001055
Olivier Deprez3de57e32022-04-28 18:18:36 +02001056Secure and non-secure IPA regions (rooted to by ``VTTBR_EL2`` and ``VSTTBR_EL2``)
1057use the same set of Stage-2 page tables within a SP.
1058
1059The ``VTCR_EL2/VSTCR_EL2/VTTBR_EL2/VSTTBR_EL2`` virtual address space
1060configuration is made part of a vCPU context.
1061
1062For S-EL0 partitions with VHE enabled, a single secure EL2&0 Stage-1 translation
1063regime is used for both Hafnium and the partition.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001064
Madhukar Pappireddyd0889a32022-10-03 14:26:48 -05001065Schedule modes and SP Call chains
1066---------------------------------
1067
1068An SP execution context is said to be in SPMC scheduled mode if CPU cycles are
1069allocated to it by SPMC. Correspondingly, an SP execution context is said to be
1070in Normal world scheduled mode if CPU cycles are allocated by the normal world.
1071
1072A call chain represents all SPs in a sequence of invocations of a direct message
1073request. When execution on a PE is in the secure state, only a single call chain
1074that runs in the Normal World scheduled mode can exist. FF-A v1.1 spec allows
1075any number of call chains to run in the SPMC scheduled mode but the Hafnium
1076SPMC restricts the number of call chains in SPMC scheduled mode to only one for
1077keeping the implementation simple.
1078
1079Partition runtime models
1080------------------------
1081
1082The runtime model of an endpoint describes the transitions permitted for an
1083execution context between various states. These are the four partition runtime
1084models supported (refer to `[1]`_ section 7):
1085
1086 - RTM_FFA_RUN: runtime model presented to an execution context that is
1087 allocated CPU cycles through FFA_RUN interface.
1088 - RTM_FFA_DIR_REQ: runtime model presented to an execution context that is
1089 allocated CPU cycles through FFA_MSG_SEND_DIRECT_REQ interface.
1090 - RTM_SEC_INTERRUPT: runtime model presented to an execution context that is
1091 allocated CPU cycles by SPMC to handle a secure interrupt.
1092 - RTM_SP_INIT: runtime model presented to an execution context that is
1093 allocated CPU cycles by SPMC to initialize its state.
1094
1095If an endpoint execution context attempts to make an invalid transition or a
1096valid transition that could lead to a loop in the call chain, SPMC denies the
1097transition with the help of above runtime models.
1098
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001099Interrupt management
1100--------------------
1101
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001102GIC ownership
1103~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001104
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001105The SPMC owns the GIC configuration. Secure and non-secure interrupts are
1106trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt
1107IDs based on SP manifests. The SPMC acknowledges physical interrupts and injects
1108virtual interrupts by setting the use of vIRQ/vFIQ bits before resuming a SP.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001109
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001110Abbreviations:
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001111
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001112 - NS-Int: A non-secure physical interrupt. It requires a switch to the normal
1113 world to be handled if it triggers while execution is in secure world.
1114 - Other S-Int: A secure physical interrupt targeted to an SP different from
1115 the one that is currently running.
1116 - Self S-Int: A secure physical interrupt targeted to the SP that is currently
1117 running.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001118
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001119Non-secure interrupt handling
1120~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001121
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001122This section documents the actions supported in SPMC in response to a non-secure
1123interrupt as per the guidance provided by FF-A v1.1 EAC0 specification.
1124An SP specifies one of the following actions in its partition manifest:
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001125
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001126 - Non-secure interrupt is signaled.
1127 - Non-secure interrupt is signaled after a managed exit.
1128 - Non-secure interrupt is queued.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001129
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001130An SP execution context in a call chain could specify a less permissive action
1131than subsequent SP execution contexts in the same call chain. The less
1132permissive action takes precedence over the more permissive actions specified
1133by the subsequent execution contexts. Please refer to FF-A v1.1 EAC0 section
11348.3.1 for further explanation.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001135
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001136Secure interrupt handling
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001137~~~~~~~~~~~~~~~~~~~~~~~~~
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001138
1139This section documents the support implemented for secure interrupt handling in
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001140SPMC as per the guidance provided by FF-A v1.1 EAC0 specification.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001141The following assumptions are made about the system configuration:
1142
1143 - In the current implementation, S-EL1 SPs are expected to use the para
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001144 virtualized ABIs for interrupt management rather than accessing the virtual
1145 GIC interface.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001146 - Unless explicitly stated otherwise, this support is applicable only for
1147 S-EL1 SPs managed by SPMC.
1148 - Secure interrupts are configured as G1S or G0 interrupts.
1149 - All physical interrupts are routed to SPMC when running a secure partition
1150 execution context.
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001151 - All endpoints with multiple execution contexts have their contexts pinned
1152 to corresponding CPUs. Hence, a secure virtual interrupt cannot be signaled
1153 to a target vCPU that is currently running or blocked on a different
1154 physical CPU.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001155
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001156A physical secure interrupt could trigger while CPU is executing in normal world
1157or secure world.
1158The action of SPMC for a secure interrupt depends on: the state of the target
1159execution context of the SP that is responsible for handling the interrupt;
1160whether the interrupt triggered while execution was in normal world or secure
1161world.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001162
1163Secure interrupt signaling mechanisms
1164~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1165
1166Signaling refers to the mechanisms used by SPMC to indicate to the SP execution
1167context that it has a pending virtual interrupt and to further run the SP
1168execution context, such that it can handle the virtual interrupt. SPMC uses
1169either the FFA_INTERRUPT interface with ERET conduit or vIRQ signal for signaling
1170to S-EL1 SPs. When normal world execution is preempted by a secure interrupt,
1171the SPMD uses the FFA_INTERRUPT ABI with ERET conduit to signal interrupt to SPMC
1172running in S-EL2.
1173
1174+-----------+---------+---------------+---------------------------------------+
1175| SP State | Conduit | Interface and | Description |
1176| | | parameters | |
1177+-----------+---------+---------------+---------------------------------------+
1178| WAITING | ERET, | FFA_INTERRUPT,| SPMC signals to SP the ID of pending |
1179| | vIRQ | Interrupt ID | interrupt. It pends vIRQ signal and |
1180| | | | resumes execution context of SP |
1181| | | | through ERET. |
1182+-----------+---------+---------------+---------------------------------------+
1183| BLOCKED | ERET, | FFA_INTERRUPT | SPMC signals to SP that an interrupt |
1184| | vIRQ | | is pending. It pends vIRQ signal and |
1185| | | | resumes execution context of SP |
1186| | | | through ERET. |
1187+-----------+---------+---------------+---------------------------------------+
1188| PREEMPTED | vIRQ | NA | SPMC pends the vIRQ signal but does |
1189| | | | not resume execution context of SP. |
1190+-----------+---------+---------------+---------------------------------------+
1191| RUNNING | ERET, | NA | SPMC pends the vIRQ signal and resumes|
1192| | vIRQ | | execution context of SP through ERET. |
1193+-----------+---------+---------------+---------------------------------------+
1194
1195Secure interrupt completion mechanisms
1196~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1197
1198A SP signals secure interrupt handling completion to the SPMC through the
1199following mechanisms:
1200
1201 - ``FFA_MSG_WAIT`` ABI if it was in WAITING state.
1202 - ``FFA_RUN`` ABI if its was in BLOCKED state.
1203
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001204This is a remnant of SPMC implementation based on the FF-A v1.0 specification.
1205In the current implementation, S-EL1 SPs use the para-virtualized HVC interface
1206implemented by SPMC to perform priority drop and interrupt deactivation (SPMC
1207configures EOImode = 0, i.e. priority drop and deactivation are done together).
1208The SPMC performs checks to deny the state transition upon invocation of
1209either FFA_MSG_WAIT or FFA_RUN interface if the SP didn't perform the
1210deactivation of the secure virtual interrupt.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001211
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001212If the current SP execution context was preempted by a secure interrupt to be
1213handled by execution context of target SP, SPMC resumes current SP after signal
1214completion by target SP execution context.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001215
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001216Actions for a secure interrupt triggered while execution is in normal world
1217~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001218
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001219+-------------------+----------+-----------------------------------------------+
1220| State of target | Action | Description |
1221| execution context | | |
1222+-------------------+----------+-----------------------------------------------+
1223| WAITING | Signaled | This starts a new call chain in SPMC scheduled|
1224| | | mode. |
1225+-------------------+----------+-----------------------------------------------+
1226| PREEMPTED | Queued | The target execution must have been preempted |
1227| | | by a non-secure interrupt. SPMC queues the |
1228| | | secure virtual interrupt now. It is signaled |
1229| | | when the target execution context next enters |
1230| | | the RUNNING state. |
1231+-------------------+----------+-----------------------------------------------+
1232| BLOCKED, RUNNING | NA | The target execution context is blocked or |
1233| | | running on a different CPU. This is not |
1234| | | supported by current SPMC implementation and |
1235| | | execution hits panic. |
1236+-------------------+----------+-----------------------------------------------+
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001237
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001238If normal world execution was preempted by a secure interrupt, SPMC uses
1239FFA_NORMAL_WORLD_RESUME ABI to indicate completion of secure interrupt handling
1240and further returns execution to normal world.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001241
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001242The following figure describes interrupt handling flow when a secure interrupt
1243triggers while execution is in normal world:
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001244
1245.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-nwd.png
1246
1247A brief description of the events:
1248
1249 - 1) Secure interrupt triggers while normal world is running.
1250 - 2) FIQ gets trapped to EL3.
1251 - 3) SPMD signals secure interrupt to SPMC at S-EL2 using FFA_INTERRUPT ABI.
1252 - 4) SPMC identifies target vCPU of SP and injects virtual interrupt (pends
1253 vIRQ).
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001254 - 5) Assuming SP1 vCPU is in WAITING state, SPMC signals virtual interrupt
1255 using FFA_INTERRUPT with interrupt id as an argument and resumes the SP1
1256 vCPU using ERET in SPMC scheduled mode.
1257 - 6) Execution traps to vIRQ handler in SP1 provided that the virtual
1258 interrupt is not masked i.e., PSTATE.I = 0
1259 - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized
1260 HVC call. SPMC clears the pending virtual interrupt state management
1261 and returns the pending virtual interrupt id.
1262 - 8) SP1 services the virtual interrupt and invokes the paravirtualized
1263 de-activation HVC call. SPMC de-activates the physical interrupt,
1264 clears the fields tracking the secure interrupt and resumes SP1 vCPU.
1265 - 9) SP1 performs secure interrupt completion through FFA_MSG_WAIT ABI.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001266 - 10) SPMC returns control to EL3 using FFA_NORMAL_WORLD_RESUME.
1267 - 11) EL3 resumes normal world execution.
1268
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001269Actions for a secure interrupt triggered while execution is in secure world
1270~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1271
1272+-------------------+----------+------------------------------------------------+
1273| State of target | Action | Description |
1274| execution context | | |
1275+-------------------+----------+------------------------------------------------+
1276| WAITING | Signaled | This starts a new call chain in SPMC scheduled |
1277| | | mode. |
1278+-------------------+----------+------------------------------------------------+
1279| PREEMPTED by Self | Signaled | The target execution context reenters the |
1280| S-Int | | RUNNING state to handle the secure virtual |
1281| | | interrupt. |
1282+-------------------+----------+------------------------------------------------+
1283| PREEMPTED by | Queued | SPMC queues the secure virtual interrupt now. |
1284| NS-Int | | It is signaled when the target execution |
1285| | | context next enters the RUNNING state. |
1286+-------------------+----------+------------------------------------------------+
1287| BLOCKED | Signaled | Both preempted and target execution contexts |
1288| | | must have been part of the Normal world |
1289| | | scheduled call chain. Refer scenario 1 of |
1290| | | Table 8.4 in the FF-A v1.1 EAC0 spec. |
1291+-------------------+----------+------------------------------------------------+
1292| RUNNING | NA | The target execution context is running on a |
1293| | | different CPU. This scenario is not supported |
1294| | | by current SPMC implementation and execution |
1295| | | hits panic. |
1296+-------------------+----------+------------------------------------------------+
1297
1298The following figure describes interrupt handling flow when a secure interrupt
1299triggers while execution is in secure world. We assume OS kernel sends a direct
1300request message to SP1. Further, SP1 sends a direct request message to SP2. SP1
1301enters BLOCKED state and SPMC resumes SP2.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001302
1303.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-swd.png
1304
1305A brief description of the events:
1306
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001307 - 1) Secure interrupt triggers while SP2 is running.
1308 - 2) SP2 gets preempted and execution traps to SPMC as IRQ.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001309 - 3) SPMC finds the target vCPU of secure partition responsible for handling
1310 this secure interrupt. In this scenario, it is SP1.
1311 - 4) SPMC pends vIRQ for SP1 and signals through FFA_INTERRUPT interface.
Madhukar Pappireddy262d7b12022-10-03 18:09:32 -05001312 SPMC further resumes SP1 through ERET conduit. Note that SP1 remains in
1313 Normal world schedule mode.
1314 - 6) Execution traps to vIRQ handler in SP1 provided that the virtual
1315 interrupt is not masked i.e., PSTATE.I = 0
1316 - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized
1317 HVC call. SPMC clears the pending virtual interrupt state management
1318 and returns the pending virtual interrupt id.
1319 - 8) SP1 services the virtual interrupt and invokes the paravirtualized
1320 de-activation HVC call. SPMC de-activates the physical interrupt and
1321 clears the fields tracking the secure interrupt and resumes SP1 vCPU.
1322 - 9) Since SP1 direct request completed with FFA_INTERRUPT, it resumes the
1323 direct request to SP2 by invoking FFA_RUN.
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -05001324 - 9) SPMC resumes the pre-empted vCPU of SP2.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001325
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001326Power management
1327----------------
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001328
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001329In platforms with or without secure virtualization:
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001330
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001331- The NWd owns the platform PM policy.
1332- The Hypervisor or OS kernel is the component initiating PSCI service calls.
1333- The EL3 PSCI library is in charge of the PM coordination and control
1334 (eventually writing to platform registers).
1335- While coordinating PM events, the PSCI library calls backs into the Secure
1336 Payload Dispatcher for events the latter has statically registered to.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001337
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001338When using the SPMD as a Secure Payload Dispatcher:
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001339
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001340- A power management event is relayed through the SPD hook to the SPMC.
1341- In the current implementation only cpu on (svc_on_finish) and cpu off
1342 (svc_off) hooks are registered.
1343- The behavior for the cpu on event is described in `Secondary cores boot-up`_.
1344 The SPMC is entered through its secondary physical core entry point.
Olivier Deprez3de57e32022-04-28 18:18:36 +02001345- The cpu off event occurs when the NWd calls PSCI_CPU_OFF. The PM event is
1346 signaled to the SPMC through a power management framework message.
1347 It consists in a SPMD-to-SPMC direct request/response (`SPMC-SPMD direct
1348 requests/responses`_) conveying the event details and SPMC response.
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001349 The SPMD performs a synchronous entry into the SPMC. The SPMC is entered and
1350 updates its internal state to reflect the physical core is being turned off.
1351 In the current implementation no SP is resumed as a consequence. This behavior
1352 ensures a minimal support for CPU hotplug e.g. when initiated by the NWd linux
1353 userspace.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001354
Olivier Deprez3de57e32022-04-28 18:18:36 +02001355Arm architecture extensions for security hardening
1356==================================================
1357
1358Hafnium supports the following architecture extensions for security hardening:
1359
1360- Pointer authentication (FEAT_PAuth): the extension permits detection of forged
1361 pointers used by ROP type of attacks through the signing of the pointer
1362 value. Hafnium is built with the compiler branch protection option to permit
1363 generation of a pointer authentication code for return addresses (pointer
1364 authentication for instructions). The APIA key is used while Hafnium runs.
1365 A random key is generated at boot time and restored upon entry into Hafnium
1366 at run-time. APIA and other keys (APIB, APDA, APDB, APGA) are saved/restored
1367 in vCPU contexts permitting to enable pointer authentication in VMs/SPs.
1368- Branch Target Identification (FEAT_BTI): the extension permits detection of
1369 unexpected indirect branches used by JOP type of attacks. Hafnium is built
1370 with the compiler branch protection option, inserting land pads at function
1371 prologues that are reached by indirect branch instructions (BR/BLR).
1372 Hafnium code pages are marked as guarded in the EL2 Stage-1 MMU descriptors
1373 such that an indirect branch must always target a landpad. A fault is
1374 triggered otherwise. VMs/SPs can (independently) mark their code pages as
1375 guarded in the EL1&0 Stage-1 translation regime.
1376- Memory Tagging Extension (FEAT_MTE): the option permits detection of out of
1377 bound memory array accesses or re-use of an already freed memory region.
1378 Hafnium enables the compiler option permitting to leverage MTE stack tagging
1379 applied to core stacks. Core stacks are marked as normal tagged memory in the
1380 EL2 Stage-1 translation regime. A synchronous data abort is generated upon tag
1381 check failure on load/stores. A random seed is generated at boot time and
1382 restored upon entry into Hafnium. MTE system registers are saved/restored in
1383 vCPU contexts permitting MTE usage from VMs/SPs.
1384
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001385SMMUv3 support in Hafnium
1386=========================
Madhukar Pappireddya9859062021-02-28 14:01:34 -06001387
1388An SMMU is analogous to an MMU in a CPU. It performs address translations for
1389Direct Memory Access (DMA) requests from system I/O devices.
1390The responsibilities of an SMMU include:
1391
1392- Translation: Incoming DMA requests are translated from bus address space to
1393 system physical address space using translation tables compliant to
1394 Armv8/Armv7 VMSA descriptor format.
1395- Protection: An I/O device can be prohibited from read, write access to a
1396 memory region or allowed.
1397- Isolation: Traffic from each individial device can be independently managed.
1398 The devices are differentiated from each other using unique translation
1399 tables.
1400
1401The following diagram illustrates a typical SMMU IP integrated in a SoC with
1402several I/O devices along with Interconnect and Memory system.
1403
1404.. image:: ../resources/diagrams/MMU-600.png
1405
1406SMMU has several versions including SMMUv1, SMMUv2 and SMMUv3. Hafnium provides
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001407support for SMMUv3 driver in both normal and secure world. A brief introduction
Madhukar Pappireddya9859062021-02-28 14:01:34 -06001408of SMMUv3 functionality and the corresponding software support in Hafnium is
1409provided here.
1410
1411SMMUv3 features
1412---------------
1413
1414- SMMUv3 provides Stage1, Stage2 translation as well as nested (Stage1 + Stage2)
1415 translation support. It can either bypass or abort incoming translations as
1416 well.
1417- Traffic (memory transactions) from each upstream I/O peripheral device,
1418 referred to as Stream, can be independently managed using a combination of
1419 several memory based configuration structures. This allows the SMMUv3 to
1420 support a large number of streams with each stream assigned to a unique
1421 translation context.
1422- Support for Armv8.1 VMSA where the SMMU shares the translation tables with
1423 a Processing Element. AArch32(LPAE) and AArch64 translation table format
1424 are supported by SMMUv3.
1425- SMMUv3 offers non-secure stream support with secure stream support being
1426 optional. Logically, SMMUv3 behaves as if there is an indepdendent SMMU
1427 instance for secure and non-secure stream support.
1428- It also supports sub-streams to differentiate traffic from a virtualized
1429 peripheral associated with a VM/SP.
1430- Additionally, SMMUv3.2 provides support for PEs implementing Armv8.4-A
1431 extensions. Consequently, SPM depends on Secure EL2 support in SMMUv3.2
1432 for providing Secure Stage2 translation support to upstream peripheral
1433 devices.
1434
1435SMMUv3 Programming Interfaces
1436-----------------------------
1437
1438SMMUv3 has three software interfaces that are used by the Hafnium driver to
1439configure the behaviour of SMMUv3 and manage the streams.
1440
1441- Memory based data strutures that provide unique translation context for
1442 each stream.
1443- Memory based circular buffers for command queue and event queue.
1444- A large number of SMMU configuration registers that are memory mapped during
1445 boot time by Hafnium driver. Except a few registers, all configuration
1446 registers have independent secure and non-secure versions to configure the
1447 behaviour of SMMUv3 for translation of secure and non-secure streams
1448 respectively.
1449
1450Peripheral device manifest
1451--------------------------
1452
1453Currently, SMMUv3 driver in Hafnium only supports dependent peripheral devices.
1454These devices are dependent on PE endpoint to initiate and receive memory
1455management transactions on their behalf. The acccess to the MMIO regions of
1456any such device is assigned to the endpoint during boot. Moreover, SMMUv3 driver
1457uses the same stage 2 translations for the device as those used by partition
1458manager on behalf of the PE endpoint. This ensures that the peripheral device
1459has the same visibility of the physical address space as the endpoint. The
1460device node of the corresponding partition manifest (refer to `[1]`_ section 3.2
1461) must specify these additional properties for each peripheral device in the
1462system :
1463
1464- smmu-id: This field helps to identify the SMMU instance that this device is
1465 upstream of.
1466- stream-ids: List of stream IDs assigned to this device.
1467
1468.. code:: shell
1469
1470 smmuv3-testengine {
1471 base-address = <0x00000000 0x2bfe0000>;
1472 pages-count = <32>;
1473 attributes = <0x3>;
1474 smmu-id = <0>;
1475 stream-ids = <0x0 0x1>;
1476 interrupts = <0x2 0x3>, <0x4 0x5>;
1477 exclusive-access;
1478 };
1479
1480SMMUv3 driver limitations
1481-------------------------
1482
1483The primary design goal for the Hafnium SMMU driver is to support secure
1484streams.
1485
1486- Currently, the driver only supports Stage2 translations. No support for
1487 Stage1 or nested translations.
1488- Supports only AArch64 translation format.
1489- No support for features such as PCI Express (PASIDs, ATS, PRI), MSI, RAS,
1490 Fault handling, Performance Monitor Extensions, Event Handling, MPAM.
1491- No support for independent peripheral devices.
1492
Raghu Krishnamurthy7f3f7ce2021-10-17 16:48:29 -07001493S-EL0 Partition support
Olivier Deprez3de57e32022-04-28 18:18:36 +02001494=======================
Raghu Krishnamurthy7f3f7ce2021-10-17 16:48:29 -07001495The SPMC (Hafnium) has limited capability to run S-EL0 FF-A partitions using
1496FEAT_VHE (mandatory with ARMv8.1 in non-secure state, and in secure world
1497with ARMv8.4 and FEAT_SEL2).
1498
1499S-EL0 partitions are useful for simple partitions that don't require full
1500Trusted OS functionality. It is also useful to reduce jitter and cycle
1501stealing from normal world since they are more lightweight than VMs.
1502
1503S-EL0 partitions are presented, loaded and initialized the same as S-EL1 VMs by
1504the SPMC. They are differentiated primarily by the 'exception-level' property
1505and the 'execution-ctx-count' property in the SP manifest. They are host apps
1506under the single EL2&0 Stage-1 translation regime controlled by the SPMC and
1507call into the SPMC through SVCs as opposed to HVCs and SMCs. These partitions
1508can use FF-A defined services (FFA_MEM_PERM_*) to update or change permissions
1509for memory regions.
1510
1511S-EL0 partitions are required by the FF-A specification to be UP endpoints,
1512capable of migrating, and the SPMC enforces this requirement. The SPMC allows
1513a S-EL0 partition to accept a direct message from secure world and normal world,
1514and generate direct responses to them.
J-Alves56ac0972022-10-26 11:00:28 +01001515All S-EL0 partitions must use AArch64. AArch32 S-EL0 partitions are not supported.
Raghu Krishnamurthy7f3f7ce2021-10-17 16:48:29 -07001516
J-Alves56ac0972022-10-26 11:00:28 +01001517Memory sharing, indirect messaging, and notifications functionality with S-EL0
1518partitions is supported.
Raghu Krishnamurthy7f3f7ce2021-10-17 16:48:29 -07001519
J-Alves56ac0972022-10-26 11:00:28 +01001520Interrupt handling is not supported with S-EL0 partitions and is work in
1521progress.
Raghu Krishnamurthy7f3f7ce2021-10-17 16:48:29 -07001522
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001523References
1524==========
1525
1526.. _[1]:
1527
Olivier Deprez2b0be752021-09-01 10:25:21 +02001528[1] `Arm Firmware Framework for Arm A-profile <https://developer.arm.com/docs/den0077/latest>`__
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001529
1530.. _[2]:
1531
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05001532[2] :ref:`Secure Partition Manager using MM interface<Secure Partition Manager (MM)>`
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001533
1534.. _[3]:
1535
1536[3] `Trusted Boot Board Requirements
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001537Client <https://developer.arm.com/documentation/den0006/d/>`__
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001538
1539.. _[4]:
1540
1541[4] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime/aarch64/context.S#n45
1542
1543.. _[5]:
1544
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001545[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/spm/cactus/plat/arm/fvp/fdts/cactus.dts
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001546
1547.. _[6]:
1548
Olivier Deprez9938c132021-04-21 11:22:23 +02001549[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001550
1551.. _[7]:
1552
1553[7] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
1554
1555.. _[8]:
1556
Sandrine Bailleux1a4efb12022-04-21 10:17:22 +02001557[8] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/CFQFGU6H2D5GZYMUYGTGUSXIU3OYZP6U/
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001558
Olivier Deprez4ab7a4a2021-06-21 09:47:13 +02001559.. _[9]:
1560
1561[9] https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#dynamic-configuration-during-cold-boot
1562
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001563--------------
1564
Imre Kis3f370fd2022-02-08 18:06:18 +01001565*Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.*