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Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8/* Marvell CP110 SoC COMPHY unit driver */
9
10#ifndef _PHY_COMPHY_CP110_H
11#define _PHY_COMPHY_CP110_H
12
13#define SD_ADDR(base, lane) (base + 0x1000 * lane)
14#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
15#define COMPHY_ADDR(base, lane) (base + 0x28 * lane)
16
17#define MAX_NUM_OF_FFE 8
18#define RX_TRAINING_TIMEOUT 500
19
20/* Comphy registers */
21#define COMMON_PHY_CFG1_REG 0x0
22#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
23#define COMMON_PHY_CFG1_PWR_UP_MASK \
24 (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
25#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
26#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
27 (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
28#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 13
29#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
30 (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
31#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 14
32#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
33 (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
34#define COMMON_PHY_PHY_MODE_OFFSET 15
35#define COMMON_PHY_PHY_MODE_MASK \
36 (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
37
38#define COMMON_PHY_CFG6_REG 0x14
39#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
40#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
41 (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
42
43#define COMMON_PHY_CFG6_REG 0x14
44#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
45#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
46 (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
47
48#define COMMON_SELECTOR_PHY_REG_OFFSET 0x140
49#define COMMON_SELECTOR_PIPE_REG_OFFSET 0x144
50#define COMMON_SELECTOR_COMPHY_MASK 0xf
51#define COMMON_SELECTOR_COMPHYN_FIELD_WIDTH 4
52#define COMMON_SELECTOR_COMPHYN_SATA 0x4
53#define COMMON_SELECTOR_PIPE_COMPHY_PCIE 0x4
54#define COMMON_SELECTOR_PIPE_COMPHY_USBH 0x1
55#define COMMON_SELECTOR_PIPE_COMPHY_USBD 0x2
56
57/* SGMII/HS-SGMII/SFI/RXAUI */
58#define COMMON_SELECTOR_COMPHY0_1_2_NETWORK 0x1
59#define COMMON_SELECTOR_COMPHY3_RXAUI 0x1
60#define COMMON_SELECTOR_COMPHY3_SGMII 0x2
61#define COMMON_SELECTOR_COMPHY4_PORT1 0x1
62#define COMMON_SELECTOR_COMPHY4_ALL_OTHERS 0x2
63#define COMMON_SELECTOR_COMPHY5_RXAUI 0x2
64#define COMMON_SELECTOR_COMPHY5_SGMII 0x1
65
66#define COMMON_PHY_SD_CTRL1 0x148
67#define COMMON_PHY_SD_CTRL1_COMPHY_0_PORT_OFFSET 0
68#define COMMON_PHY_SD_CTRL1_COMPHY_1_PORT_OFFSET 4
69#define COMMON_PHY_SD_CTRL1_COMPHY_2_PORT_OFFSET 8
70#define COMMON_PHY_SD_CTRL1_COMPHY_3_PORT_OFFSET 12
71#define COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK 0xFFFF
72#define COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK 0xFF
73#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
74#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
75 (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
76#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
77#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
78 (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
79#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
80#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
81 (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
82#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
83#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
84 (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
85
86/* DFX register */
87#define DFX_BASE (0x400000)
88#define DFX_DEV_GEN_CTRL12_REG (0x280)
89#define DFX_DEV_GEN_PCIE_CLK_SRC_MUX (0x3)
90#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
91#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
92 (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
93
94/* SerDes IP registers */
95#define SD_EXTERNAL_CONFIG0_REG 0
96#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
97#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
98 (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
99#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
100#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
101 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
102#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
103#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
104 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
105#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
106#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
107 (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
108#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
109#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
110 (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
111#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
112#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
113 (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
114#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
115#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
116 (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
117
118#define SD_EXTERNAL_CONFIG1_REG 0x4
119#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
120#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
121 (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
122#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
123#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
124 (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
125#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
126#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
127 (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
128#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
129#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
130 (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
131
132#define SD_EXTERNAL_CONFIG2_REG 0x8
133#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
134#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
135 (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
136#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
137#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
138 (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
139
140#define SD_EXTERNAL_STATUS_REG 0xc
141#define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7
142#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \
143 (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET)
144
145#define SD_EXTERNAL_STATUS0_REG 0x18
146#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
147#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
148 (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
149#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
150#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
151 (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
152#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
153#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
154 (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
155
156#define SD_EXTERNAL_STATAUS1_REG 0x1c
157#define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_OFFSET 0
158#define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_MASK \
159 (1 << SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_OFFSET)
160#define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_OFFSET 1
161#define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_MASK \
162 (1 << SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_OFFSET)
163
164/* HPIPE registers */
165#define HPIPE_PWR_PLL_REG 0x4
166#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
167#define HPIPE_PWR_PLL_REF_FREQ_MASK \
168 (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
169#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
170#define HPIPE_PWR_PLL_PHY_MODE_MASK \
171 (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
172
173#define HPIPE_CAL_REG1_REG 0xc
174#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
175#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
176 (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
177#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
178#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
179 (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
180
181#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18
182#define HPIPE_SQUELCH_THRESH_IN_OFFSET 8
183#define HPIPE_SQUELCH_THRESH_IN_MASK \
184 (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET)
185#define HPIPE_SQUELCH_DETECTED_OFFSET 14
186#define HPIPE_SQUELCH_DETECTED_MASK \
187 (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET)
188
189#define HPIPE_DFE_REG0 0x1c
190#define HPIPE_DFE_RES_FORCE_OFFSET 15
191#define HPIPE_DFE_RES_FORCE_MASK \
192 (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
193
194#define HPIPE_DFE_F3_F5_REG 0x28
195#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
196#define HPIPE_DFE_F3_F5_DFE_EN_MASK \
197 (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
198#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
199#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
200 (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
201
202#define HPIPE_G1_SET_0_REG 0x34
203#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
204#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
205 (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
206#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
207#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
208 (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
209#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
210#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
211 (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
212#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
213#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
214 (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
215
216#define HPIPE_G1_SET_1_REG 0x38
217#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
218#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
219 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +0200220#define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET 3
221#define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK \
222 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET)
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300223#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
224#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
225 (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
226#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
227#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
228 (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
229#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
230#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
231 (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
232#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
233#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
234 (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
235
236#define HPIPE_G2_SET_0_REG 0x3c
237#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
238#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
239 (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
240#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
241#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
242 (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
243#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
244#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
245 (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
246#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
247#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
248 (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
249
250#define HPIPE_G2_SET_1_REG 0x40
251#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
252#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
253 (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +0200254#define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET 3
255#define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK \
256 (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET)
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300257#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
258#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
259 (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
260#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
261#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
262 (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
263#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
264#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
265 (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
266#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
267#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
268 (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
269
270#define HPIPE_G3_SET_0_REG 0x44
271#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
272#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
273 (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
274#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
275#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
276 (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
277#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
278#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
279 (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
280#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
281#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
282 (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
283#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
284#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
285 (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
286#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
287#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
288 (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
289
290#define HPIPE_G3_SET_1_REG 0x48
291#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
292#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
293 (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
294#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
295#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
296 (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
297#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
298#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
299 (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
300#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
301#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
302 (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
303#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
304#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
305 (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
306#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
307#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
308 (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
309#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
310#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
311 (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
312
313#define HPIPE_PHY_TEST_CONTROL_REG 0x54
314#define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4
315#define HPIPE_PHY_TEST_PATTERN_SEL_MASK \
316 (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET)
317#define HPIPE_PHY_TEST_RESET_OFFSET 14
318#define HPIPE_PHY_TEST_RESET_MASK \
319 (0x1 << HPIPE_PHY_TEST_RESET_OFFSET)
320#define HPIPE_PHY_TEST_EN_OFFSET 15
321#define HPIPE_PHY_TEST_EN_MASK \
322 (0x1 << HPIPE_PHY_TEST_EN_OFFSET)
323
324#define HPIPE_PHY_TEST_DATA_REG 0x6c
325#define HPIPE_PHY_TEST_DATA_OFFSET 0
326#define HPIPE_PHY_TEST_DATA_MASK \
327 (0xffff << HPIPE_PHY_TEST_DATA_OFFSET)
328
329#define HPIPE_LOOPBACK_REG 0x8c
330#define HPIPE_LOOPBACK_SEL_OFFSET 1
331#define HPIPE_LOOPBACK_SEL_MASK \
332 (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
333#define HPIPE_CDR_LOCK_OFFSET 7
334#define HPIPE_CDR_LOCK_MASK \
335 (0x1 << HPIPE_CDR_LOCK_OFFSET)
336#define HPIPE_CDR_LOCK_DET_EN_OFFSET 8
337#define HPIPE_CDR_LOCK_DET_EN_MASK \
338 (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET)
339
340#define HPIPE_INTERFACE_REG 0x94
341#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
342#define HPIPE_INTERFACE_GEN_MAX_MASK \
343 (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
344#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
345#define HPIPE_INTERFACE_DET_BYPASS_MASK \
346 (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
347#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
348#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
349 (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
350
351#define HPIPE_G1_SET_2_REG 0xf4
352#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
353#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
354 (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
355#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
356#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
357 (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET)
358
359#define HPIPE_G2_SET_2_REG 0xf8
360#define HPIPE_G2_TX_SSC_AMP_OFFSET 9
361#define HPIPE_G2_TX_SSC_AMP_MASK \
362 (0x7f << HPIPE_G2_TX_SSC_AMP_OFFSET)
363
364#define HPIPE_VDD_CAL_0_REG 0x108
365#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
366#define HPIPE_CAL_VDD_CONT_MODE_MASK \
367 (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
368
369#define HPIPE_VDD_CAL_CTRL_REG 0x114
370#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
371#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
372 (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
373
374#define HPIPE_PCIE_REG0 0x120
375#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
376#define HPIPE_PCIE_IDLE_SYNC_MASK \
377 (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
378#define HPIPE_PCIE_SEL_BITS_OFFSET 13
379#define HPIPE_PCIE_SEL_BITS_MASK \
380 (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
381
382#define HPIPE_LANE_ALIGN_REG 0x124
383#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
384#define HPIPE_LANE_ALIGN_OFF_MASK \
385 (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
386
387#define HPIPE_MISC_REG 0x13C
388#define HPIPE_MISC_CLK100M_125M_OFFSET 4
389#define HPIPE_MISC_CLK100M_125M_MASK \
390 (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
391#define HPIPE_MISC_ICP_FORCE_OFFSET 5
392#define HPIPE_MISC_ICP_FORCE_MASK \
393 (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
394#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
395#define HPIPE_MISC_TXDCLK_2X_MASK \
396 (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
397#define HPIPE_MISC_CLK500_EN_OFFSET 7
398#define HPIPE_MISC_CLK500_EN_MASK \
399 (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
400#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
401#define HPIPE_MISC_REFCLK_SEL_MASK \
402 (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
403
404#define HPIPE_RX_CONTROL_1_REG 0x140
405#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
406#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
407 (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
408#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
409#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
410 (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
411
412#define HPIPE_PWR_CTR_REG 0x148
413#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
414#define HPIPE_PWR_CTR_RST_DFE_MASK \
415 (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
416#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
417#define HPIPE_PWR_CTR_SFT_RST_MASK \
418 (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
419
420#define HPIPE_SPD_DIV_FORCE_REG 0x154
421#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
422#define HPIPE_TXDIGCK_DIV_FORCE_MASK \
423 (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
424#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
425#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
426 (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
427#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
428#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
429 (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
430#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
431#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
432 (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
433#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
434#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
435 (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
436
437#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
438#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
439#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
440 (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
441#define HPIPE_SMAPLER_OFFSET 12
442#define HPIPE_SMAPLER_MASK \
443 (0x1 << HPIPE_SMAPLER_OFFSET)
444
445#define HPIPE_TX_REG1_REG 0x174
446#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
447#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
448 (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
449#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
450#define HPIPE_TX_REG1_SLC_EN_MASK \
451 (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
452
453#define HPIPE_PWR_CTR_DTL_REG 0x184
454#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
455#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
456 (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
457#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
458#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
459 (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
460#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
461#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
462 (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
463#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
464#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
465 (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
466#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
467#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
468 (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
469#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
470#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
471 (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
472#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
473#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
474 (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
475
476#define HPIPE_PHASE_CONTROL_REG 0x188
477#define HPIPE_OS_PH_OFFSET_OFFSET 0
478#define HPIPE_OS_PH_OFFSET_MASK \
479 (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
480#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
481#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
482 (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
483#define HPIPE_OS_PH_VALID_OFFSET 8
484#define HPIPE_OS_PH_VALID_MASK \
485 (0x1 << HPIPE_OS_PH_VALID_OFFSET)
486
487#define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8
488#define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0
489#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \
490 (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET)
491#define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4
492#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \
493 (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET)
494#define HPIPE_SQ_DEGLITCH_EN_OFFSET 8
495#define HPIPE_SQ_DEGLITCH_EN_MASK \
496 (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET)
497
498#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
499#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
500#define HPIPE_TRAIN_PAT_NUM_MASK \
501 (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
502
503#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
504#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
505#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \
506 (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
507
508#define HPIPE_DME_REG 0x228
509#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
510#define HPIPE_DME_ETHERNET_MODE_MASK \
511 (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
512
513#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
514#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
515#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
516 (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
517
518#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
519#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
520#define HPIPE_TX_TRAIN_CTRL_G1_MASK \
521 (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
522#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
523#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
524 (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
525#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
526#define HPIPE_TX_TRAIN_CTRL_G0_MASK \
527 (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
528
529#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
530#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
531#define HPIPE_TRX_TRAIN_TIMER_MASK \
532 (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
533
534#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
535#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
536#define HPIPE_RX_TRAIN_TIMER_MASK \
537 (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
538#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
539#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
540 (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
541#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
542#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
543 (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
544#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
545#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
546 (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
547#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
548#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
549 (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
550
551#define HPIPE_TX_TRAIN_REG 0x31C
552#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
553#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
554 (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
555#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
556#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
557 (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
558#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
559#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \
560 (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
561#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
562#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
563 (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
564
565#define HPIPE_SAVED_DFE_VALUES_REG 0x328
566#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10
567#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \
568 (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET)
569
570#define HPIPE_CDR_CONTROL_REG 0x418
571#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14
572#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \
573 (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET)
574#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
575#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
576 (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
577#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
578#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
579 (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
580#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
581#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
582 (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
583
584#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
585#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
586#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
587 (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
588#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
589#define HPIPE_TX_NUM_OF_PRESET_MASK \
590 (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
591#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
592#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
593 (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
594
595#define HPIPE_G1_SETTINGS_3_REG 0x440
596#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
597#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
598 (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
599#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
600#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
601 (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
602#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
603#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
604 (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
605#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
606#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
607 (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
608#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
609#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
610 (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
611#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
612#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
613 (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
614
615#define HPIPE_G1_SETTINGS_4_REG 0x444
616#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
617#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
618 (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
619
620#define HPIPE_G2_SETTINGS_4_REG 0x44c
621#define HPIPE_G2_DFE_RES_OFFSET 8
622#define HPIPE_G2_DFE_RES_MASK \
623 (0x3 << HPIPE_G2_DFE_RES_OFFSET)
624
625#define HPIPE_G3_SETTING_3_REG 0x450
626#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
627#define HPIPE_G3_FFE_CAP_SEL_MASK \
628 (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
629#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
630#define HPIPE_G3_FFE_RES_SEL_MASK \
631 (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
632#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
633#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
634 (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
635#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
636#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
637 (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
638#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
639#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
640 (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
641
642#define HPIPE_G3_SETTING_4_REG 0x454
643#define HPIPE_G3_DFE_RES_OFFSET 8
644#define HPIPE_G3_DFE_RES_MASK (0x3 << HPIPE_G3_DFE_RES_OFFSET)
645
646#define HPIPE_TX_PRESET_INDEX_REG 0x468
647#define HPIPE_TX_PRESET_INDEX_OFFSET 0
648#define HPIPE_TX_PRESET_INDEX_MASK \
649 (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
650
651#define HPIPE_DFE_CONTROL_REG 0x470
652#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
653#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
654 (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
655
656#define HPIPE_DFE_CTRL_28_REG 0x49C
657#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
658#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
659 (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
660
661#define HPIPE_G1_SETTING_5_REG 0x538
662#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
663#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
664 (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
665
666#define HPIPE_G3_SETTING_5_REG 0x548
667#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
668#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
669 (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
670
671#define HPIPE_LANE_CONFIG0_REG 0x600
672#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
673#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
674 (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
675
676#define HPIPE_LANE_STATUS1_REG 0x60C
677#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
678#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
679 (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
680
681#define HPIPE_LANE_CFG4_REG 0x620
682#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
683#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
684 (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
685#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
686#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
687 (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
688#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
689#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
690 (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
691#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
692#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
693 (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
694
695#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
696#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
697#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
698 (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
699#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
700#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
701 (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
702#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
703#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
704 (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
705
706#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
707#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
708#define HPIPE_CFG_PHY_RC_EP_MASK \
709 (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
710
711#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
712#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
713#define HPIPE_CFG_UPDATE_POLARITY_MASK \
714 (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
715
716#define HPIPE_LANE_EQ_CFG2_REG 0x6a4
717#define HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET 14
718#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK \
719 (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET)
720
721#define HPIPE_RST_CLK_CTRL_REG 0x704
722#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
723#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
724 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
725#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
726#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
727 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
728#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
729#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
730 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
731#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
732#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
733 (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
734
735#define HPIPE_TST_MODE_CTRL_REG 0x708
736#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
737#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
738 (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
739
740#define HPIPE_CLK_SRC_LO_REG 0x70c
741#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
742#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
743 (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
744#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
745#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
746 (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
747#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
748#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
749 (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
750
751#define HPIPE_CLK_SRC_HI_REG 0x710
752#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
753#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
754 (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
755#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
756#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
757 (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
758#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
759#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
760 (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
761#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
762#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
763 (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
764
765#define HPIPE_GLOBAL_MISC_CTRL 0x718
766#define HPIPE_GLOBAL_PM_CTRL 0x740
767#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
768#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
769 (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
770
771/* General defines */
772#define PLL_LOCK_TIMEOUT 15000
773
774#endif /* _PHY_COMPHY_CP110_H */
775