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Jacky Bai07ed02c2020-06-03 14:28:45 +08001/*
Jacky Bai0e400552022-03-14 17:14:26 +08002 * Copyright 2020-2022 NXP
Jacky Bai07ed02c2020-06-03 14:28:45 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <stdbool.h>
9
10#include <arch_helpers.h>
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <context.h>
14#include <drivers/arm/tzc380.h>
15#include <drivers/console.h>
16#include <drivers/generic_delay_timer.h>
17#include <lib/el3_runtime/context_mgmt.h>
18#include <lib/mmio.h>
19#include <lib/xlat_tables/xlat_tables_v2.h>
20#include <plat/common/platform.h>
21
Jacky Bai9a6f62f2019-11-25 14:43:26 +080022#include <dram.h>
Jacky Bai07ed02c2020-06-03 14:28:45 +080023#include <gpc.h>
24#include <imx_aipstz.h>
25#include <imx_uart.h>
26#include <imx_rdc.h>
27#include <imx8m_caam.h>
Jacky Bai3c3c2682020-01-07 14:53:54 +080028#include <imx8m_csu.h>
Jacky Bai07ed02c2020-06-03 14:28:45 +080029#include <platform_def.h>
30#include <plat_imx8.h>
31
Jacky Bai26f9f882020-09-09 16:23:32 +080032#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
33
Jacky Bai07ed02c2020-06-03 14:28:45 +080034static const mmap_region_t imx_mmap[] = {
35 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP,
36 NOC_MAP, {0},
37};
38
39static const struct aipstz_cfg aipstz[] = {
40 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
41 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
42 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
43 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
44 {0},
45};
46
47static const struct imx_rdc_cfg rdc[] = {
48 /* Master domain assignment */
Jacky Bai0e400552022-03-14 17:14:26 +080049 RDC_MDAn(RDC_MDA_M7, DID1),
Jacky Bai07ed02c2020-06-03 14:28:45 +080050
51 /* peripherals domain permission */
Jacky Bai0e400552022-03-14 17:14:26 +080052 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
Jacky Bai07ed02c2020-06-03 14:28:45 +080053
54 /* memory region */
55
56 /* Sentinel */
57 {0},
58};
59
Jacky Bai3c3c2682020-01-07 14:53:54 +080060static const struct imx_csu_cfg csu_cfg[] = {
61 /* peripherals csl setting */
62 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED),
63 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED),
64
65 /* master HP0~1 */
66
67 /* SA setting */
68
69 /* HP control setting */
70
71 /* Sentinel */
72 {0}
73};
74
Jacky Bai07ed02c2020-06-03 14:28:45 +080075static entry_point_info_t bl32_image_ep_info;
76static entry_point_info_t bl33_image_ep_info;
77
78/* get SPSR for BL33 entry */
79static uint32_t get_spsr_for_bl33_entry(void)
80{
81 unsigned long el_status;
82 unsigned long mode;
83 uint32_t spsr;
84
85 /* figure out what mode we enter the non-secure world */
86 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
87 el_status &= ID_AA64PFR0_ELX_MASK;
88
89 mode = (el_status) ? MODE_EL2 : MODE_EL1;
90
91 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
92 return spsr;
93}
94
95static void bl31_tzc380_setup(void)
96{
97 unsigned int val;
98
99 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
100 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
101 return;
102
103 tzc380_init(IMX_TZASC_BASE);
104
105 /*
106 * Need to substact offset 0x40000000 from CPU address when
107 * programming tzasc region for i.mx8mp.
108 */
109
110 /* Enable 1G-5G S/NS RW */
111 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
112 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
113}
114
115void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
116 u_register_t arg2, u_register_t arg3)
117{
118 static console_t console;
Jacky Baif1d011c2021-04-16 14:31:09 +0800119 unsigned int val;
Jacky Bai07ed02c2020-06-03 14:28:45 +0800120 unsigned int i;
121
122 /* Enable CSU NS access permission */
123 for (i = 0; i < 64; i++) {
124 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
125 }
126
127 imx_aipstz_init(aipstz);
128
129 imx_rdc_init(rdc);
130
Jacky Bai3c3c2682020-01-07 14:53:54 +0800131 imx_csu_init(csu_cfg);
132
133 /* config the ocram memory range for secure access */
Jacky Baif1d011c2021-04-16 14:31:09 +0800134 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1);
135 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
136 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
Jacky Bai3c3c2682020-01-07 14:53:54 +0800137
Jacky Bai07ed02c2020-06-03 14:28:45 +0800138 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
139 IMX_CONSOLE_BAUDRATE, &console);
140 /* This console is only used for boot stage */
141 console_set_scope(&console, CONSOLE_FLAG_BOOT);
142
Andrey Zhizhikin6651ef82022-09-19 20:49:16 +0200143 imx8m_caam_init();
144
Jacky Bai07ed02c2020-06-03 14:28:45 +0800145 /*
146 * tell BL3-1 where the non-secure software image is located
147 * and the entry state information.
148 */
149 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
150 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
151 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
152
Jacky Bai26f9f882020-09-09 16:23:32 +0800153#if defined(SPD_opteed) || defined(SPD_trusty)
Jacky Bai07ed02c2020-06-03 14:28:45 +0800154 /* Populate entry point information for BL32 */
155 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
156 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
157 bl32_image_ep_info.pc = BL32_BASE;
158 bl32_image_ep_info.spsr = 0;
159
160 /* Pass TEE base and size to bl33 */
161 bl33_image_ep_info.args.arg1 = BL32_BASE;
162 bl33_image_ep_info.args.arg2 = BL32_SIZE;
Jacky Bai26f9f882020-09-09 16:23:32 +0800163
164#ifdef SPD_trusty
165 bl32_image_ep_info.args.arg0 = BL32_SIZE;
166 bl32_image_ep_info.args.arg1 = BL32_BASE;
Jacky Bai9168b462020-03-27 20:28:19 +0800167#else
168 /* Make sure memory is clean */
169 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
170 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
171 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
Jacky Bai26f9f882020-09-09 16:23:32 +0800172#endif
Jacky Bai07ed02c2020-06-03 14:28:45 +0800173#endif
174
175 bl31_tzc380_setup();
176}
177
178void bl31_plat_arch_setup(void)
179{
180 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
181 MT_MEMORY | MT_RW | MT_SECURE);
182 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
183 MT_MEMORY | MT_RO | MT_SECURE);
184#if USE_COHERENT_MEM
185 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
186 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE),
187 MT_DEVICE | MT_RW | MT_SECURE);
188#endif
Jacky Bai26f9f882020-09-09 16:23:32 +0800189
190 /* Map TEE memory */
191 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW);
192
Jacky Bai07ed02c2020-06-03 14:28:45 +0800193 mmap_add(imx_mmap);
194
195 init_xlat_tables();
196
197 enable_mmu_el3(0);
198}
199
200void bl31_platform_setup(void)
201{
202 generic_delay_timer_init();
203
204 /* select the CKIL source to 32K OSC */
205 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
206
Jacky Bai9a6f62f2019-11-25 14:43:26 +0800207 /* Init the dram info */
208 dram_info_init(SAVED_DRAM_TIMING_BASE);
209
Jacky Bai07ed02c2020-06-03 14:28:45 +0800210 plat_gic_driver_init();
211 plat_gic_init();
212
213 imx_gpc_init();
214}
215
216entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
217{
218 if (type == NON_SECURE) {
219 return &bl33_image_ep_info;
220 }
221
222 if (type == SECURE) {
223 return &bl32_image_ep_info;
224 }
225
226 return NULL;
227}
228
229unsigned int plat_get_syscnt_freq2(void)
230{
231 return COUNTER_FREQUENCY;
232}
Jacky Bai26f9f882020-09-09 16:23:32 +0800233
234#ifdef SPD_trusty
235void plat_trusty_set_boot_args(aapcs64_params_t *args)
236{
237 args->arg0 = BL32_SIZE;
238 args->arg1 = BL32_BASE;
239 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
240}
241#endif