Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 1 | /* |
Tamas Ban | 307b3d8 | 2023-05-08 13:51:27 +0200 | [diff] [blame] | 2 | * Copyright (c) 2018-2024, Arm Limited. All rights reserved. |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 9 | |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 10 | #include <plat/arm/board/common/v2m_def.h> |
| 11 | #include <plat/arm/common/arm_def.h> |
| 12 | #include <plat/arm/css/common/css_def.h> |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 13 | |
Deepak Pandey | b66a18e | 2018-12-18 17:10:24 +0530 | [diff] [blame] | 14 | /* UART related constants */ |
| 15 | #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 |
| 16 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 |
| 17 | |
Himanshu Sharma | a87b240 | 2022-06-20 06:06:34 +0000 | [diff] [blame] | 18 | /* IOFPGA UART0 */ |
| 19 | #define PLAT_ARM_RUN_UART_BASE 0x1C090000 |
| 20 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000 |
Deepak Pandey | b66a18e | 2018-12-18 17:10:24 +0530 | [diff] [blame] | 21 | |
| 22 | #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 |
| 23 | #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 |
| 24 | |
Usama Arif | 81eb5ce | 2019-02-11 16:35:42 +0000 | [diff] [blame] | 25 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 26 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
Deepak Pandey | b66a18e | 2018-12-18 17:10:24 +0530 | [diff] [blame] | 27 | |
Sami Mujawar | 2f3365b | 2019-05-09 13:43:30 +0100 | [diff] [blame] | 28 | #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 29 | #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) |
| 30 | |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 31 | #define MAX_IO_DEVICES U(3) |
| 32 | #define MAX_IO_HANDLES U(4) |
| 33 | |
| 34 | #define PLAT_ARM_FLASH_IMAGE_BASE 0x18200000 |
| 35 | #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE 0x00800000 |
| 36 | |
| 37 | #define PLAT_ARM_NVM_BASE 0x18200000 |
| 38 | #define PLAT_ARM_NVM_SIZE 0x00800000 |
| 39 | |
| 40 | #if defined NS_BL1U_BASE |
| 41 | # undef NS_BL1U_BASE |
| 42 | # define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000)) |
| 43 | #endif |
| 44 | |
| 45 | /* Non-volatile counters */ |
| 46 | #define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 |
| 47 | #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE) |
| 48 | #define TFW_NVCTR_SIZE U(4) |
| 49 | #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) |
| 50 | #define NTFW_CTR_SIZE U(4) |
| 51 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 52 | /* N1SDP remote chip at 4 TB offset */ |
| 53 | #define PLAT_ARM_REMOTE_CHIP_OFFSET (ULL(1) << 42) |
| 54 | |
| 55 | #define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \ |
| 56 | PLAT_ARM_REMOTE_CHIP_OFFSET |
| 57 | #define N1SDP_REMOTE_DRAM1_SIZE ARM_DRAM1_SIZE |
| 58 | |
| 59 | #define N1SDP_REMOTE_DRAM2_BASE PLAT_ARM_DRAM2_BASE + \ |
| 60 | PLAT_ARM_REMOTE_CHIP_OFFSET |
| 61 | #define N1SDP_REMOTE_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE |
| 62 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 63 | /* |
| 64 | * N1SDP platform supports RDIMMs with ECC capability. To use the ECC |
| 65 | * capability, the entire DDR memory space has to be zeroed out before |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 66 | * enabling the ECC bits in DMC620. To access the complete DDR memory |
| 67 | * along with remote chip's DDR memory, which is at 4 TB offset, physical |
| 68 | * and virtual address space limits are extended to 43-bits. |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 69 | */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 70 | #ifdef __aarch64__ |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 71 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) |
| 72 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 73 | #else |
| 74 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 75 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 76 | #endif |
Deepak Pandey | b66a18e | 2018-12-18 17:10:24 +0530 | [diff] [blame] | 77 | |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 78 | #if CSS_USE_SCMI_SDS_DRIVER |
| 79 | #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 |
Tamas Ban | 307b3d8 | 2023-05-08 13:51:27 +0200 | [diff] [blame] | 80 | /* |
| 81 | * Index of SDS region used in the communication with SCP |
| 82 | */ |
| 83 | #define SDS_SCP_AP_REGION_ID U(0) |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 84 | #else |
| 85 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 |
| 86 | #endif |
| 87 | |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 88 | /* |
| 89 | * Trusted SRAM in N1SDP is 512 KB but only the bottom 384 KB |
| 90 | * is used for trusted board boot flow. The top 128 KB is used |
| 91 | * to load AP-BL1 image. |
| 92 | */ |
| 93 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00060000 /* 384 KB */ |
| 94 | |
| 95 | /* |
| 96 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 97 | * plus a little space for growth. |
| 98 | */ |
Vishnu Banavath | 7cac3de | 2022-06-20 18:20:21 +0100 | [diff] [blame] | 99 | #define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 100 | |
| 101 | /* |
| 102 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 103 | */ |
| 104 | |
| 105 | #if USE_ROMLIB |
| 106 | # define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 |
| 107 | # define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 |
| 108 | #else |
| 109 | # define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) |
| 110 | # define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) |
| 111 | #endif |
| 112 | |
| 113 | /* |
| 114 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 115 | * little space for growth. |
| 116 | */ |
| 117 | #if TRUSTED_BOARD_BOOT |
Vishnu Banavath | 7cac3de | 2022-06-20 18:20:21 +0100 | [diff] [blame] | 118 | # define PLAT_ARM_MAX_BL2_SIZE 0x22000 |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 119 | #else |
| 120 | # define PLAT_ARM_MAX_BL2_SIZE 0x14000 |
| 121 | #endif |
| 122 | |
Vishnu Banavath | 7cac3de | 2022-06-20 18:20:21 +0100 | [diff] [blame] | 123 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x40000) |
| 124 | |
| 125 | #define PLAT_ARM_SPMC_BASE U(0x08000000) |
| 126 | #define PLAT_ARM_SPMC_SIZE UL(0x02000000) /* 32 MB */ |
| 127 | |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 128 | |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 129 | /******************************************************************************* |
| 130 | * N1SDP topology related constants |
| 131 | ******************************************************************************/ |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 132 | #define N1SDP_MAX_CPUS_PER_CLUSTER U(2) |
| 133 | #define PLAT_ARM_CLUSTER_COUNT U(2) |
| 134 | #define PLAT_N1SDP_CHIP_COUNT U(2) |
| 135 | #define N1SDP_MAX_CLUSTERS_PER_CHIP U(2) |
| 136 | #define N1SDP_MAX_PE_PER_CPU U(1) |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 137 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 138 | #define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \ |
| 139 | PLAT_ARM_CLUSTER_COUNT * \ |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 140 | N1SDP_MAX_CPUS_PER_CLUSTER * \ |
| 141 | N1SDP_MAX_PE_PER_CPU) |
| 142 | |
Chandni Cherukuri | 0fdcbc0 | 2018-10-16 15:19:54 +0530 | [diff] [blame] | 143 | /* System power domain level */ |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 144 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 145 | |
| 146 | /* |
| 147 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 148 | * plat_arm_mmap array defined for each BL stage. |
| 149 | */ |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 150 | |
| 151 | #ifdef IMAGE_BL1 |
| 152 | # define PLAT_ARM_MMAP_ENTRIES U(6) |
| 153 | # define MAX_XLAT_TABLES U(5) |
| 154 | #endif |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 155 | |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 156 | #ifdef IMAGE_BL2 |
| 157 | # define PLAT_ARM_MMAP_ENTRIES U(11) |
| 158 | # define MAX_XLAT_TABLES U(10) |
| 159 | #endif |
| 160 | |
| 161 | #ifdef IMAGE_BL31 |
| 162 | # define PLAT_ARM_MMAP_ENTRIES U(12) |
| 163 | # define MAX_XLAT_TABLES U(12) |
| 164 | #endif |
| 165 | |
| 166 | /* |
| 167 | * Size of cacheable stacks |
| 168 | */ |
| 169 | #if defined(IMAGE_BL1) |
| 170 | # if TRUSTED_BOARD_BOOT |
| 171 | # define PLATFORM_STACK_SIZE 0x1000 |
| 172 | # else |
| 173 | # define PLATFORM_STACK_SIZE 0x440 |
| 174 | # endif |
| 175 | #elif defined(IMAGE_BL2) |
| 176 | # if TRUSTED_BOARD_BOOT |
| 177 | # define PLATFORM_STACK_SIZE 0x1000 |
| 178 | # else |
| 179 | # define PLATFORM_STACK_SIZE 0x400 |
| 180 | # endif |
| 181 | #elif defined(IMAGE_BL2U) |
| 182 | # define PLATFORM_STACK_SIZE 0x400 |
| 183 | #elif defined(IMAGE_BL31) |
| 184 | # if SPM_MM |
| 185 | # define PLATFORM_STACK_SIZE 0x500 |
| 186 | # else |
| 187 | # define PLATFORM_STACK_SIZE 0x400 |
| 188 | # endif |
| 189 | #elif defined(IMAGE_BL32) |
| 190 | # define PLATFORM_STACK_SIZE 0x440 |
| 191 | #endif |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 192 | |
| 193 | #define PLAT_ARM_NSTIMER_FRAME_ID 0 |
| 194 | #define PLAT_CSS_MHU_BASE 0x45000000 |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 195 | #define PLAT_MAX_PWR_LVL 2 |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 196 | |
Werner Lewis | fddf8c0 | 2023-05-25 15:38:44 +0100 | [diff] [blame] | 197 | /* Interrupt handling constants */ |
| 198 | #define N1SDP_IRQ_MMU_TCU1_EVENT_Q_SEC U(257) |
| 199 | #define N1SDP_IRQ_MMU_TCU1_CMD_SYNC_SEC U(258) |
| 200 | #define N1SDP_IRQ_MMU_TCU1_GLOBAL U(259) |
| 201 | #define N1SDP_IRQ_MMU_TCU2_EVENT_Q_SEC U(264) |
| 202 | #define N1SDP_IRQ_MMU_TCU2_CMD_SYNC_SEC U(265) |
| 203 | #define N1SDP_IRQ_MMU_TCU2_GLOBAL U(266) |
| 204 | #define N1SDP_IRQ_CLUSTER0_MHU U(349) |
| 205 | #define N1SDP_IRQ_CLUSTER1_MHU U(351) |
| 206 | #define N1SDP_IRQ_P0_REFCLK U(412) |
| 207 | #define N1SDP_IRQ_P1_REFCLK U(413) |
| 208 | |
| 209 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 210 | ARM_G1S_IRQ_PROPS(grp), \ |
| 211 | INTR_PROP_DESC(CSS_IRQ_MHU, \ |
| 212 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 213 | INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, \ |
| 214 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 215 | INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, \ |
| 216 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 217 | INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_EVENT_Q_SEC, \ |
| 218 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 219 | INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_CMD_SYNC_SEC, \ |
| 220 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 221 | INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_GLOBAL, \ |
| 222 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 223 | INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_EVENT_Q_SEC, \ |
| 224 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 225 | INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_CMD_SYNC_SEC, \ |
| 226 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 227 | INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_GLOBAL, \ |
| 228 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 229 | INTR_PROP_DESC(N1SDP_IRQ_CLUSTER0_MHU, \ |
| 230 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 231 | INTR_PROP_DESC(N1SDP_IRQ_CLUSTER1_MHU, \ |
| 232 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 233 | INTR_PROP_DESC(N1SDP_IRQ_P0_REFCLK, \ |
| 234 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 235 | INTR_PROP_DESC(N1SDP_IRQ_P1_REFCLK, \ |
| 236 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL) |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 237 | |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 238 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 239 | |
| 240 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 241 | #define N1SDP_DEVICE_BASE ULL(0x08000000) |
| 242 | #define N1SDP_DEVICE_SIZE ULL(0x48000000) |
| 243 | #define N1SDP_REMOTE_DEVICE_BASE N1SDP_DEVICE_BASE + \ |
| 244 | PLAT_ARM_REMOTE_CHIP_OFFSET |
| 245 | #define N1SDP_REMOTE_DEVICE_SIZE N1SDP_DEVICE_SIZE |
| 246 | |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 247 | /* Real base is 0x0. Changed to load BL1 at this address */ |
| 248 | # define PLAT_ARM_TRUSTED_ROM_BASE 0x04060000 |
| 249 | # define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 /* 128KB */ |
| 250 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 251 | #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ |
| 252 | N1SDP_DEVICE_BASE, \ |
| 253 | N1SDP_DEVICE_SIZE, \ |
| 254 | MT_DEVICE | MT_RW | MT_SECURE) |
| 255 | |
| 256 | #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ |
| 257 | ARM_DRAM1_BASE, \ |
| 258 | ARM_DRAM1_SIZE, \ |
| 259 | MT_MEMORY | MT_RW | MT_NS) |
| 260 | |
| 261 | #define N1SDP_MAP_REMOTE_DEVICE MAP_REGION_FLAT( \ |
| 262 | N1SDP_REMOTE_DEVICE_BASE, \ |
| 263 | N1SDP_REMOTE_DEVICE_SIZE, \ |
| 264 | MT_DEVICE | MT_RW | MT_SECURE) |
| 265 | |
| 266 | #define N1SDP_MAP_REMOTE_DRAM1 MAP_REGION_FLAT( \ |
| 267 | N1SDP_REMOTE_DRAM1_BASE, \ |
| 268 | N1SDP_REMOTE_DRAM1_SIZE, \ |
| 269 | MT_MEMORY | MT_RW | MT_NS) |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 270 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 271 | #define N1SDP_MAP_REMOTE_DRAM2 MAP_REGION_FLAT( \ |
| 272 | N1SDP_REMOTE_DRAM2_BASE, \ |
| 273 | N1SDP_REMOTE_DRAM2_SIZE, \ |
| 274 | MT_MEMORY | MT_RW | MT_NS) |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 275 | |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 276 | /* GIC related constants */ |
| 277 | #define PLAT_ARM_GICD_BASE 0x30000000 |
| 278 | #define PLAT_ARM_GICC_BASE 0x2C000000 |
| 279 | #define PLAT_ARM_GICR_BASE 0x300C0000 |
| 280 | |
| 281 | /* Platform ID address */ |
| 282 | #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 283 | |
Aditya Angadi | 20b4841 | 2019-04-16 11:29:14 +0530 | [diff] [blame] | 284 | /* Secure Watchdog Constants */ |
| 285 | #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) |
| 286 | #define SBSA_SECURE_WDOG_TIMEOUT UL(100) |
| 287 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 288 | /* Number of SCMI channels on the platform */ |
| 289 | #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) |
| 290 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 291 | #endif /* PLATFORM_DEF_H */ |