n1sdp: add code for DDR ECC enablement and BL33 copy to DDR
N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
enabling the ECC bits in DMC620. Zeroing out several gigabytes of
memory from SCP is quite time consuming so functions are added that
zeros out the DDR memory from application processor which is
much faster compared to SCP. BL33 binary cannot be copied to DDR memory
before enabling ECC so this is also done by TF-A from IOFPGA-DDR3
memory to main DDR4 memory after ECC is enabled.
Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which
the entire DDR space cannot be accessed as DRAM2 starts in base
0x8080000000. So these macros are redefined for all ARM platforms.
Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
index 0964f56..ff583a9 100644
--- a/plat/arm/board/n1sdp/include/platform_def.h
+++ b/plat/arm/board/n1sdp/include/platform_def.h
@@ -25,7 +25,22 @@
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
-#define PLAT_ARM_DRAM2_SIZE ULL(0x780000000)
+#define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000)
+
+/*
+ * N1SDP platform supports RDIMMs with ECC capability. To use the ECC
+ * capability, the entire DDR memory space has to be zeroed out before
+ * enabling the ECC bits in DMC620. The access the complete DDR memory
+ * space the physical & virtual address space limits are extended to
+ * 40-bits.
+ */
+#ifndef AARCH32
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#endif
#if CSS_USE_SCMI_SDS_DRIVER
#define N1SDP_SCMI_PAYLOAD_BASE 0x45400000
@@ -55,8 +70,8 @@
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
*/
-#define PLAT_ARM_MMAP_ENTRIES 3
-#define MAX_XLAT_TABLES 4
+#define PLAT_ARM_MMAP_ENTRIES 6
+#define MAX_XLAT_TABLES 7
#define PLATFORM_STACK_SIZE 0x400
@@ -73,13 +88,18 @@
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
-#define N1SDP_DEVICE_BASE (0x20000000)
-#define N1SDP_DEVICE_SIZE (0x30000000)
+#define N1SDP_DEVICE_BASE (0x08000000)
+#define N1SDP_DEVICE_SIZE (0x48000000)
#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \
N1SDP_DEVICE_BASE, \
N1SDP_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
+#define ARM_MAP_DRAM1 MAP_REGION_FLAT( \
+ ARM_DRAM1_BASE, \
+ ARM_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
/* GIC related constants */
#define PLAT_ARM_GICD_BASE 0x30000000
#define PLAT_ARM_GICC_BASE 0x2C000000