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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#ifndef __PLAT_ARM_H__
7#define __PLAT_ARM_H__
8
Antonio Nino Diazf09d0032017-04-11 14:04:56 +01009#include <arm_xlat_tables.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <bakery_lock.h>
Dan Handley9df48042015-03-19 18:58:55 +000011#include <cassert.h>
12#include <cpu_data.h>
13#include <stdint.h>
Summer Qin5ce394c2018-03-12 11:28:26 +080014#include <tzc_common.h>
Scott Brandenbf404c02017-04-10 11:45:52 -070015#include <utils_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000016
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010017/*******************************************************************************
18 * Forward declarations
19 ******************************************************************************/
20struct bl31_params;
21struct meminfo;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010022struct image_info;
Soby Mathew96a1c6b2018-01-15 14:45:33 +000023struct bl_params;
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010024
Summer Qin5ce394c2018-03-12 11:28:26 +080025typedef struct arm_tzc_regions_info {
26 unsigned long long base;
27 unsigned long long end;
28 tzc_region_attributes_t sec_attr;
29 unsigned int nsaid_permissions;
30} arm_tzc_regions_info_t;
31
32/*******************************************************************************
33 * Default mapping definition of the TrustZone Controller for ARM standard
34 * platforms.
35 * Configure:
36 * - Region 0 with no access;
37 * - Region 1 with secure access only;
38 * - the remaining DRAM regions access from the given Non-Secure masters.
39 ******************************************************************************/
40#if ENABLE_SPM
41#define ARM_TZC_REGIONS_DEF \
42 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
43 TZC_REGION_S_RDWR, 0}, \
44 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
45 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
46 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
48 {ARM_SP_IMAGE_NS_BUF_BASE, (ARM_SP_IMAGE_NS_BUF_BASE + \
49 ARM_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
50 PLAT_ARM_TZC_NS_DEV_ACCESS}
51
52#else
53#define ARM_TZC_REGIONS_DEF \
54 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
55 TZC_REGION_S_RDWR, 0}, \
56 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
57 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
58 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
59 PLAT_ARM_TZC_NS_DEV_ACCESS}
60#endif
61
Chris Kay2b54c0c2018-05-09 15:46:07 +010062#define ARM_CASSERT_MMAP \
63 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \
64 assert_plat_arm_mmap_mismatch); \
65 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \
66 <= MAX_MMAP_REGIONS, \
Dan Handley9df48042015-03-19 18:58:55 +000067 assert_max_mmap_regions);
68
69/*
70 * Utility functions common to ARM standard platforms
71 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010072void arm_setup_page_tables(const mmap_region_t bl_regions[],
73 const mmap_region_t plat_regions[]);
Dan Handley9df48042015-03-19 18:58:55 +000074
Roberto Vargase3adc372018-05-23 09:27:06 +010075void arm_setup_romlib(void);
76
Soby Mathew074f6932017-02-28 22:58:29 +000077#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
Dan Handley9df48042015-03-19 18:58:55 +000078/*
79 * Use this macro to instantiate lock before it is used in below
80 * arm_lock_xxx() macros
81 */
Sandrine Bailleuxceb258e2018-07-11 13:59:18 +020082#define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock)
Soby Mathewea26bad2016-11-14 12:25:45 +000083#define ARM_LOCK_GET_INSTANCE (&arm_lock)
Dan Handley9df48042015-03-19 18:58:55 +000084/*
85 * These are wrapper macros to the Coherent Memory Bakery Lock API.
86 */
87#define arm_lock_init() bakery_lock_init(&arm_lock)
88#define arm_lock_get() bakery_lock_get(&arm_lock)
89#define arm_lock_release() bakery_lock_release(&arm_lock)
90
91#else
92
Dan Handley9df48042015-03-19 18:58:55 +000093/*
Yatharth Kochar2694cba2016-11-14 12:00:41 +000094 * Empty macros for all other BL stages other than BL31 and BL32
Dan Handley9df48042015-03-19 18:58:55 +000095 */
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +010096#define ARM_INSTANTIATE_LOCK static int arm_lock __unused
Soby Mathewea26bad2016-11-14 12:25:45 +000097#define ARM_LOCK_GET_INSTANCE 0
Dan Handley9df48042015-03-19 18:58:55 +000098#define arm_lock_init()
99#define arm_lock_get()
100#define arm_lock_release()
101
Soby Mathew074f6932017-02-28 22:58:29 +0000102#endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */
Dan Handley9df48042015-03-19 18:58:55 +0000103
Soby Mathew7799cf72015-04-16 14:49:09 +0100104#if ARM_RECOM_STATE_ID_ENC
105/*
106 * Macros used to parse state information from State-ID if it is using the
107 * recommended encoding for State-ID.
108 */
109#define ARM_LOCAL_PSTATE_WIDTH 4
110#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
111
112/* Macros to construct the composite power state */
113
114/* Make composite power state parameter till power level 0 */
115#if PSCI_EXTENDED_STATE_ID
116
117#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
118 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
119#else
120#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
121 (((lvl0_state) << PSTATE_ID_SHIFT) | \
122 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
123 ((type) << PSTATE_TYPE_SHIFT))
124#endif /* __PSCI_EXTENDED_STATE_ID__ */
125
126/* Make composite power state parameter till power level 1 */
127#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
128 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
129 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
130
Soby Mathewa869de12015-05-08 10:18:59 +0100131/* Make composite power state parameter till power level 2 */
132#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
133 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
134 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
135
Soby Mathew7799cf72015-04-16 14:49:09 +0100136#endif /* __ARM_RECOM_STATE_ID_ENC__ */
137
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000138/* ARM State switch error codes */
139#define STATE_SW_E_PARAM (-2)
140#define STATE_SW_E_DENIED (-3)
Dan Handley9df48042015-03-19 18:58:55 +0000141
Dan Handley9df48042015-03-19 18:58:55 +0000142/* IO storage utility functions */
143void arm_io_setup(void);
144
145/* Security utility functions */
Summer Qin5ce394c2018-03-12 11:28:26 +0800146void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +0000147struct tzc_dmc500_driver_data;
Summer Qin5ce394c2018-03-12 11:28:26 +0800148void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
149 const arm_tzc_regions_info_t *tzc_regions);
Dan Handley9df48042015-03-19 18:58:55 +0000150
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100151/* Console utility functions */
152void arm_console_boot_init(void);
153void arm_console_boot_end(void);
154void arm_console_runtime_init(void);
155void arm_console_runtime_end(void);
156
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100157/* Systimer utility function */
158void arm_configure_sys_timer(void);
159
Dan Handley9df48042015-03-19 18:58:55 +0000160/* PM utility functions */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100161int arm_validate_power_state(unsigned int power_state,
162 psci_power_state_t *req_state);
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100163int arm_validate_psci_entrypoint(uintptr_t entrypoint);
Soby Mathew0d9e8522015-07-15 13:36:24 +0100164int arm_validate_ns_entrypoint(uintptr_t entrypoint);
Soby Mathew9ca28062017-10-11 16:08:58 +0100165void arm_system_pwr_domain_save(void);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100166void arm_system_pwr_domain_resume(void);
Roberto Vargas1a6eed32018-02-12 12:36:17 +0000167int arm_psci_read_mem_protect(int *enabled);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100168int arm_nor_psci_write_mem_protect(int val);
Roberto Vargas550eb082018-01-05 16:00:05 +0000169void arm_nor_psci_do_static_mem_protect(void);
170void arm_nor_psci_do_dyn_mem_protect(void);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100171int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100172
173/* Topology utility function */
174int arm_check_mpidr(u_register_t mpidr);
Dan Handley9df48042015-03-19 18:58:55 +0000175
176/* BL1 utility functions */
177void arm_bl1_early_platform_setup(void);
178void arm_bl1_platform_setup(void);
179void arm_bl1_plat_arch_setup(void);
180
181/* BL2 utility functions */
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000182void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout);
Dan Handley9df48042015-03-19 18:58:55 +0000183void arm_bl2_platform_setup(void);
184void arm_bl2_plat_arch_setup(void);
185uint32_t arm_get_spsr_for_bl32_entry(void);
186uint32_t arm_get_spsr_for_bl33_entry(void);
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000187int arm_bl2_handle_post_image_load(unsigned int image_id);
Dan Handley9df48042015-03-19 18:58:55 +0000188
Roberto Vargas52207802017-11-17 13:22:18 +0000189/* BL2 at EL3 functions */
190void arm_bl2_el3_early_platform_setup(void);
191void arm_bl2_el3_plat_arch_setup(void);
192
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100193/* BL2U utility functions */
194void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
195 void *plat_info);
196void arm_bl2u_platform_setup(void);
197void arm_bl2u_plat_arch_setup(void);
198
Juan Castillo7d199412015-12-14 09:35:25 +0000199/* BL31 utility functions */
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100200#if LOAD_IMAGE_V2
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000201void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
202 uintptr_t hw_config, void *plat_params_from_bl2);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100203#else
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000204void arm_bl31_early_platform_setup(struct bl31_params *from_bl2, uintptr_t soc_fw_config,
205 uintptr_t hw_config, void *plat_params_from_bl2);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100206#endif /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +0000207void arm_bl31_platform_setup(void);
Soby Mathew2fd66be2015-12-09 11:38:43 +0000208void arm_bl31_plat_runtime_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +0000209void arm_bl31_plat_arch_setup(void);
210
211/* TSP utility functions */
212void arm_tsp_early_platform_setup(void);
213
Soby Mathew7b754182016-07-11 14:15:27 +0100214/* SP_MIN utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000215void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
216 uintptr_t hw_config, void *plat_params_from_bl2);
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100217void arm_sp_min_plat_runtime_setup(void);
Soby Mathew7b754182016-07-11 14:15:27 +0100218
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100219/* FIP TOC validity check */
220int arm_io_is_toc_valid(void);
Dan Handley9df48042015-03-19 18:58:55 +0000221
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000222/* Utility functions for Dynamic Config */
223void arm_load_tb_fw_config(void);
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000224void arm_bl2_set_tb_cfg_addr(void *dtb);
225void arm_bl2_dyn_cfg_init(void);
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000226
Dan Handley9df48042015-03-19 18:58:55 +0000227/*
228 * Mandatory functions required in ARM standard platforms
229 */
Soby Mathew47e43f22016-02-01 14:04:34 +0000230unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000231void plat_arm_gic_driver_init(void);
Dan Handley9df48042015-03-19 18:58:55 +0000232void plat_arm_gic_init(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000233void plat_arm_gic_cpuif_enable(void);
234void plat_arm_gic_cpuif_disable(void);
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000235void plat_arm_gic_redistif_on(void);
236void plat_arm_gic_redistif_off(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000237void plat_arm_gic_pcpu_init(void);
Soby Mathew9ca28062017-10-11 16:08:58 +0100238void plat_arm_gic_save(void);
239void plat_arm_gic_resume(void);
Dan Handley9df48042015-03-19 18:58:55 +0000240void plat_arm_security_setup(void);
241void plat_arm_pwrc_setup(void);
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000242void plat_arm_interconnect_init(void);
243void plat_arm_interconnect_enter_coherency(void);
244void plat_arm_interconnect_exit_coherency(void);
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100245void plat_arm_program_trusted_mailbox(uintptr_t address);
Dan Handley9df48042015-03-19 18:58:55 +0000246
Summer Qin93c812f2017-02-28 16:46:17 +0000247#if ARM_PLAT_MT
248unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
249#endif
250
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100251#if LOAD_IMAGE_V2
252/*
253 * This function is called after loading SCP_BL2 image and it is used to perform
254 * any platform-specific actions required to handle the SCP firmware.
255 */
256int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info);
257#endif
258
Dan Handley9df48042015-03-19 18:58:55 +0000259/*
260 * Optional functions required in ARM standard platforms
261 */
262void plat_arm_io_setup(void);
263int plat_arm_get_alt_image_source(
Juan Castillo3a66aca2015-04-13 17:36:19 +0100264 unsigned int image_id,
265 uintptr_t *dev_handle,
266 uintptr_t *image_spec);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100267unsigned int plat_arm_calc_core_pos(u_register_t mpidr);
Vikram Kanigiri07035432015-11-12 18:52:34 +0000268const mmap_region_t *plat_arm_get_mmap(void);
Dan Handley9df48042015-03-19 18:58:55 +0000269
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100270/* Allow platform to override psci_pm_ops during runtime */
271const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops);
272
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000273/* Execution state switch in ARM platforms */
274int arm_execution_state_switch(unsigned int smc_fid,
275 uint32_t pc_hi,
276 uint32_t pc_lo,
277 uint32_t cookie_hi,
278 uint32_t cookie_lo,
279 void *handle);
280
Soby Mathew6d07e672018-03-01 10:53:33 +0000281/* Optional functions for SP_MIN */
282void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
283 u_register_t arg2, u_register_t arg3);
284
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000285/* global variables */
286extern plat_psci_ops_t plat_arm_psci_pm_ops;
287extern const mmap_region_t plat_arm_mmap[];
Jeenu Viswambharan4542cfe2018-07-19 08:03:46 +0100288extern const unsigned int arm_pm_idle_states[];
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000289
Dan Handley9df48042015-03-19 18:58:55 +0000290#endif /* __PLAT_ARM_H__ */