blob: 49ba9f73b5bbb5effac4c11871fffc414acbe4e4 [file] [log] [blame]
Achin Gupta191e86e2014-05-09 10:03:15 +01001/*
Jeenu Viswambharanf4194ee2018-01-10 15:00:20 +00002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta191e86e2014-05-09 10:03:15 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta191e86e2014-05-09 10:03:15 +01005 */
6
7#ifndef __INTERRUPT_MGMT_H__
8#define __INTERRUPT_MGMT_H__
9
10#include <arch.h>
11
12/*******************************************************************************
13 * Constants for the types of interrupts recognised by the IM framework
14 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070015#define INTR_TYPE_S_EL1 U(0)
16#define INTR_TYPE_EL3 U(1)
17#define INTR_TYPE_NS U(2)
18#define MAX_INTR_TYPES U(3)
Achin Gupta191e86e2014-05-09 10:03:15 +010019#define INTR_TYPE_INVAL MAX_INTR_TYPES
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010020
21/* Interrupt routing modes */
22#define INTR_ROUTING_MODE_PE 0
23#define INTR_ROUTING_MODE_ANY 1
24
Achin Gupta191e86e2014-05-09 10:03:15 +010025/*
26 * Constant passed to the interrupt handler in the 'id' field when the
27 * framework does not read the gic registers to determine the interrupt id.
28 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070029#define INTR_ID_UNAVAILABLE U(0xFFFFFFFF)
Achin Gupta191e86e2014-05-09 10:03:15 +010030
31
32/*******************************************************************************
33 * Mask for _both_ the routing model bits in the 'flags' parameter and
34 * constants to define the valid routing models for each supported interrupt
35 * type
36 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070037#define INTR_RM_FLAGS_SHIFT U(0x0)
38#define INTR_RM_FLAGS_MASK U(0x3)
Achin Gupta191e86e2014-05-09 10:03:15 +010039/* Routed to EL3 from NS. Taken to S-EL1 from Secure */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070040#define INTR_SEL1_VALID_RM0 U(0x2)
Achin Gupta191e86e2014-05-09 10:03:15 +010041/* Routed to EL3 from NS and Secure */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070042#define INTR_SEL1_VALID_RM1 U(0x3)
Achin Gupta191e86e2014-05-09 10:03:15 +010043/* Routed to EL1/EL2 from NS and to S-EL1 from Secure */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070044#define INTR_NS_VALID_RM0 U(0x0)
Achin Gupta191e86e2014-05-09 10:03:15 +010045/* Routed to EL1/EL2 from NS and to EL3 from Secure */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070046#define INTR_NS_VALID_RM1 U(0x1)
Soby Mathew58e32d12015-11-23 13:58:45 +000047/* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070048#define INTR_EL3_VALID_RM0 U(0x2)
Soby Mathew58e32d12015-11-23 13:58:45 +000049/* Routed to EL3 from NS and Secure */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070050#define INTR_EL3_VALID_RM1 U(0x3)
Soby Mathew47903c02015-01-13 15:48:26 +000051/* This is the default routing model */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070052#define INTR_DEFAULT_RM U(0x0)
Achin Gupta191e86e2014-05-09 10:03:15 +010053
54/*******************************************************************************
55 * Constants for the _individual_ routing model bits in the 'flags' field for
56 * each interrupt type and mask to validate the 'flags' parameter while
57 * registering an interrupt handler
58 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070059#define INTR_TYPE_FLAGS_MASK U(0xFFFFFFFC)
Achin Gupta191e86e2014-05-09 10:03:15 +010060
61#define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */
62#define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070063#define INTR_RM_FROM_FLAG_MASK U(1)
Jeenu Viswambharan837cc9c2018-08-02 10:14:12 +010064#define get_interrupt_rm_flag(flag, ss) \
65 ((((flag) >> INTR_RM_FLAGS_SHIFT) >> (ss)) & INTR_RM_FROM_FLAG_MASK)
66#define set_interrupt_rm_flag(flag, ss) ((flag) |= U(1) << (ss))
67#define clr_interrupt_rm_flag(flag, ss) ((flag) &= ~(U(1) << (ss)))
Achin Gupta191e86e2014-05-09 10:03:15 +010068
69
70/*******************************************************************************
71 * Macros to validate the routing model bits in the 'flags' for a type
72 * of interrupt. If the model does not match one of the valid masks
73 * -EINVAL is returned.
74 ******************************************************************************/
Soby Mathew58e32d12015-11-23 13:58:45 +000075#define validate_sel1_interrupt_rm(x) ((x) == INTR_SEL1_VALID_RM0 ? 0 : \
76 ((x) == INTR_SEL1_VALID_RM1 ? 0 :\
Achin Gupta191e86e2014-05-09 10:03:15 +010077 -EINVAL))
78
Soby Mathew58e32d12015-11-23 13:58:45 +000079#define validate_ns_interrupt_rm(x) ((x) == INTR_NS_VALID_RM0 ? 0 : \
80 ((x) == INTR_NS_VALID_RM1 ? 0 :\
81 -EINVAL))
82
Jeenu Viswambharanf4194ee2018-01-10 15:00:20 +000083#if EL3_EXCEPTION_HANDLING
84/*
85 * With EL3 exception handling, EL3 interrupts are always routed to EL3 from
86 * both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is the only
87 * valid routing model.
88 */
89#define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM1 ? 0 : \
90 -EINVAL)
91#else
Soby Mathew58e32d12015-11-23 13:58:45 +000092#define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM0 ? 0 : \
93 ((x) == INTR_EL3_VALID_RM1 ? 0 :\
Achin Gupta191e86e2014-05-09 10:03:15 +010094 -EINVAL))
Jeenu Viswambharanf4194ee2018-01-10 15:00:20 +000095#endif
Achin Gupta191e86e2014-05-09 10:03:15 +010096
97/*******************************************************************************
98 * Macros to set the 'flags' parameter passed to an interrupt type handler. Only
99 * the flag to indicate the security state when the exception was generated is
100 * supported.
101 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700102#define INTR_SRC_SS_FLAG_SHIFT U(0) /* BIT[0] */
103#define INTR_SRC_SS_FLAG_MASK U(1)
Jeenu Viswambharan32ceef52018-08-02 10:14:12 +0100104#define set_interrupt_src_ss(flag, val) ((flag) |= (val) << INTR_SRC_SS_FLAG_SHIFT)
105#define clr_interrupt_src_ss(flag) ((flag) &= ~(U(1) << INTR_SRC_SS_FLAG_SHIFT))
106#define get_interrupt_src_ss(flag) (((flag) >> INTR_SRC_SS_FLAG_SHIFT) & \
Achin Gupta191e86e2014-05-09 10:03:15 +0100107 INTR_SRC_SS_FLAG_MASK)
108
109#ifndef __ASSEMBLY__
110
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100111#include <stdint.h>
112
Achin Gupta191e86e2014-05-09 10:03:15 +0100113/* Prototype for defining a handler for an interrupt type */
114typedef uint64_t (*interrupt_type_handler_t)(uint32_t id,
115 uint32_t flags,
116 void *handle,
117 void *cookie);
118
119/*******************************************************************************
120 * Function & variable prototypes
121 ******************************************************************************/
Dan Handleya17fefa2014-05-14 12:38:32 +0100122uint32_t get_scr_el3_from_routing_model(uint32_t security_state);
123int32_t set_routing_model(uint32_t type, uint32_t flags);
124int32_t register_interrupt_type_handler(uint32_t type,
125 interrupt_type_handler_t handler,
126 uint32_t flags);
Roberto Vargas777dd432018-02-12 12:36:17 +0000127interrupt_type_handler_t get_interrupt_type_handler(uint32_t type);
Soby Mathew47903c02015-01-13 15:48:26 +0000128int disable_intr_rm_local(uint32_t type, uint32_t security_state);
129int enable_intr_rm_local(uint32_t type, uint32_t security_state);
Achin Gupta191e86e2014-05-09 10:03:15 +0100130
131#endif /*__ASSEMBLY__*/
132#endif /* __INTERRUPT_MGMT_H__ */