commit ff957ed4d718d06226da5227c6322ce02babda34
author Jonathan Wright <jonathan.wright@arm.com> Wed Mar 14 15:24:00 2018 +0000
committer Jonathan Wright <jonathan.wright@arm.com> Mon Mar 26 12:43:05 2018 +0100
tree 48e9700b7154e62d0e8b43e732346e3929b938a3
parent de70183b8c3d2005a63d17569f1dfbbf4e2b03b8

plat: fix switch statements to comply with MISRA rules

Ensure (where possible) that switch statements in plat comply with MISRA
rules 16.1 - 16.7.

Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>

plat/rockchip/rk3399/drivers/dram/dfs.c

diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index d629e4b..70d9423 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -207,6 +207,9 @@
 		ptiming_config->rdbi = 0;
 		ptiming_config->wdbi = 0;
 		break;
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 	ptiming_config->dramds = drv_config->dram_side_drv;
 	ptiming_config->dramodt = drv_config->dram_side_dq_odt;

plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c

diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
index 2e196b5..3527f0e 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
+++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
@@ -1314,5 +1314,8 @@
 	case LPDDR4:
 		lpddr4_get_parameter(timing_config, pdram_timing);
 		break;
+	default:
+		/* Do nothing in default case */
+		break;
 	}
 }

plat/rockchip/rk3399/drivers/pmu/pmu.c

diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index caea7a7..ed1ea8b 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -310,6 +310,7 @@
 		pmu_bus_idle_req(BUS_ID_PERIHP, state);
 		break;
 	default:
+		/* Do nothing in default case */
 		break;
 	}
 
@@ -647,12 +648,8 @@
 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
 				 plat_local_state_t lvl_state)
 {
-	switch (lvl) {
-	case MPIDR_AFFLVL1:
+	if (lvl == MPIDR_AFFLVL1) {
 		clst_pwr_domain_suspend(lvl_state);
-		break;
-	default:
-		break;
 	}
 
 	return PSCI_E_SUCCESS;
@@ -675,12 +672,8 @@
 
 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state)
 {
-	switch (lvl) {
-	case MPIDR_AFFLVL1:
+	if (lvl == MPIDR_AFFLVL1) {
 		clst_pwr_domain_suspend(lvl_state);
-		break;
-	default:
-		break;
 	}
 
 	return PSCI_E_SUCCESS;
@@ -698,12 +691,8 @@
 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
 				       plat_local_state_t lvl_state)
 {
-	switch (lvl) {
-	case MPIDR_AFFLVL1:
+	if (lvl == MPIDR_AFFLVL1) {
 		clst_pwr_domain_resume(lvl_state);
-		break;
-	default:
-		break;
 	}
 
 	return PSCI_E_SUCCESS;
@@ -721,11 +710,8 @@
 
 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state)
 {
-	switch (lvl) {
-	case MPIDR_AFFLVL1:
+	if (lvl == MPIDR_AFFLVL1) {
 		clst_pwr_domain_resume(lvl_state);
-	default:
-		break;
 	}
 
 	return PSCI_E_SUCCESS;