plat: fix switch statements to comply with MISRA rules
Ensure (where possible) that switch statements in plat comply with MISRA
rules 16.1 - 16.7.
Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
diff --git a/plat/rockchip/common/rockchip_sip_svc.c b/plat/rockchip/common/rockchip_sip_svc.c
index 40cc94b..eca4f99 100644
--- a/plat/rockchip/common/rockchip_sip_svc.c
+++ b/plat/rockchip/common/rockchip_sip_svc.c
@@ -59,13 +59,11 @@
case SIP_SVC_UID:
/* Return UID to the caller */
SMC_UUID_RET(handle, rk_sip_svc_uid);
- break;
case SIP_SVC_VERSION:
/* Return the version of current implementation */
SMC_RET2(handle, RK_SIP_SVC_VERSION_MAJOR,
RK_SIP_SVC_VERSION_MINOR);
- break;
default:
return rockchip_plat_sip_handler(smc_fid, x1, x2, x3, x4,
diff --git a/plat/rockchip/rk3368/plat_sip_calls.c b/plat/rockchip/rk3368/plat_sip_calls.c
index 7383d2f..03fee88 100644
--- a/plat/rockchip/rk3368/plat_sip_calls.c
+++ b/plat/rockchip/rk3368/plat_sip_calls.c
@@ -19,9 +19,6 @@
void *handle,
uint64_t flags)
{
- switch (smc_fid) {
- default:
- ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
- SMC_RET1(handle, SMC_UNK);
- }
+ ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+ SMC_RET1(handle, SMC_UNK);
}
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index d629e4b..70d9423 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -207,6 +207,9 @@
ptiming_config->rdbi = 0;
ptiming_config->wdbi = 0;
break;
+ default:
+ /* Do nothing in default case */
+ break;
}
ptiming_config->dramds = drv_config->dram_side_drv;
ptiming_config->dramodt = drv_config->dram_side_dq_odt;
diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
index 2e196b5..3527f0e 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
+++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
@@ -1314,5 +1314,8 @@
case LPDDR4:
lpddr4_get_parameter(timing_config, pdram_timing);
break;
+ default:
+ /* Do nothing in default case */
+ break;
}
}
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index caea7a7..ed1ea8b 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -310,6 +310,7 @@
pmu_bus_idle_req(BUS_ID_PERIHP, state);
break;
default:
+ /* Do nothing in default case */
break;
}
@@ -647,12 +648,8 @@
int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
plat_local_state_t lvl_state)
{
- switch (lvl) {
- case MPIDR_AFFLVL1:
+ if (lvl == MPIDR_AFFLVL1) {
clst_pwr_domain_suspend(lvl_state);
- break;
- default:
- break;
}
return PSCI_E_SUCCESS;
@@ -675,12 +672,8 @@
int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state)
{
- switch (lvl) {
- case MPIDR_AFFLVL1:
+ if (lvl == MPIDR_AFFLVL1) {
clst_pwr_domain_suspend(lvl_state);
- break;
- default:
- break;
}
return PSCI_E_SUCCESS;
@@ -698,12 +691,8 @@
int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
plat_local_state_t lvl_state)
{
- switch (lvl) {
- case MPIDR_AFFLVL1:
+ if (lvl == MPIDR_AFFLVL1) {
clst_pwr_domain_resume(lvl_state);
- break;
- default:
- break;
}
return PSCI_E_SUCCESS;
@@ -721,11 +710,8 @@
int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state)
{
- switch (lvl) {
- case MPIDR_AFFLVL1:
+ if (lvl == MPIDR_AFFLVL1) {
clst_pwr_domain_resume(lvl_state);
- default:
- break;
}
return PSCI_E_SUCCESS;