| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame^] | 1 | /* Copyright 2016 MediaTek Inc. |
| 2 | * Author: Carlos Huang <carlos.huang@mediatek.com> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | #ifndef RA_SWITCH_H |
| 14 | #define RA_SWITCH_H |
| 15 | |
| 16 | extern struct net_device *dev_raether; |
| 17 | #define ANACAL_INIT 0x01 |
| 18 | #define ANACAL_ERROR 0xFD |
| 19 | #define ANACAL_SATURATION 0xFE |
| 20 | #define ANACAL_FINISH 0xFF |
| 21 | #define ANACAL_PAIR_A 0 |
| 22 | #define ANACAL_PAIR_B 1 |
| 23 | #define ANACAL_PAIR_C 2 |
| 24 | #define ANACAL_PAIR_D 3 |
| 25 | #define DAC_IN_0V 0x000 |
| 26 | #define DAC_IN_2V 0x0f0 |
| 27 | #define TX_AMP_OFFSET_0MV 0x20 |
| 28 | #define TX_AMP_OFFSET_VALID_BITS 6 |
| 29 | #define FE_CAL_P0 0 |
| 30 | #define FE_CAL_P1 1 |
| 31 | #if defined(CONFIG_MACH_LEOPARD) |
| 32 | #define FE_CAL_COMMON 1 |
| 33 | #else |
| 34 | #define FE_CAL_COMMON 0 |
| 35 | #endif |
| 36 | |
| 37 | void fe_sw_init(void); |
| 38 | void fe_sw_preinit(struct END_DEVICE *ei_local); |
| 39 | void fe_sw_deinit(struct END_DEVICE *ei_local); |
| 40 | void sw_ioctl(struct ra_switch_ioctl_data *ioctl_data); |
| 41 | irqreturn_t esw_interrupt(int irq, void *resv); |
| 42 | irqreturn_t gsw_interrupt(int irq, void *resv); |
| 43 | |
| 44 | /* struct mtk_gsw - the structure that holds the SoC specific data |
| 45 | * @dev: The Device struct |
| 46 | * @base: The base address |
| 47 | * @piac_offset: The PIAC base may change depending on SoC |
| 48 | * @irq: The IRQ we are using |
| 49 | * @port4: The port4 mode on MT7620 |
| 50 | * @autopoll: Is MDIO autopolling enabled |
| 51 | * @ethsys: The ethsys register map |
| 52 | * @pctl: The pin control register map |
| 53 | * @clk_trgpll: The trgmii pll clock |
| 54 | */ |
| 55 | struct mtk_gsw { |
| 56 | struct mtk_eth *eth; |
| 57 | struct device *dev; |
| 58 | void __iomem *base; |
| 59 | u32 piac_offset; |
| 60 | int irq; |
| 61 | int port4; |
| 62 | unsigned long int autopoll; |
| 63 | |
| 64 | struct regmap *ethsys; |
| 65 | struct regmap *pctl; |
| 66 | |
| 67 | int trgmii_force; |
| 68 | bool wllll; |
| 69 | bool mcm; |
| 70 | struct pinctrl *pins; |
| 71 | struct pinctrl_state *ps_default; |
| 72 | struct pinctrl_state *ps_reset; |
| 73 | int reset_pin; |
| 74 | struct regulator *supply; |
| 75 | struct regulator *b3v; |
| 76 | }; |
| 77 | |
| 78 | extern u8 fe_cal_flag; |
| 79 | extern u8 fe_cal_flag_mdix; |
| 80 | extern u8 fe_cal_tx_offset_flag; |
| 81 | extern u8 fe_cal_tx_offset_flag_mdix; |
| 82 | extern u8 fe_cal_r50_flag; |
| 83 | extern u8 fe_cal_vbg_flag; |
| 84 | void fe_cal_r50(u8 port_num, u32 delay); |
| 85 | void fe_cal_tx_amp(u8 port_num, u32 delay); |
| 86 | void fe_cal_tx_amp_mdix(u8 port_num, u32 delay); |
| 87 | void fe_cal_tx_offset(u8 port_num, u32 delay); |
| 88 | void fe_cal_tx_offset_mdix(u8 port_num, u32 delay); |
| 89 | void fe_cal_vbg(u8 port_num, u32 delay); |
| 90 | /*giga port calibration*/ |
| 91 | void ge_cal_r50(u8 port_num, u32 delay); |
| 92 | void ge_cal_tx_amp(u8 port_num, u32 delay); |
| 93 | void ge_cal_tx_offset(u8 port_num, u32 delay); |
| 94 | void do_ge_phy_all_analog_cal(u8 phyaddr); |
| 95 | #endif |