developer | e5e687d | 2023-08-08 16:05:33 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * Copyright (c) 2023 MediaTek Inc. All Rights Reserved. |
| 4 | * |
| 5 | * Author: Alvin Kuo <alvin.kuog@mediatek.com> |
| 6 | * Ren-Ting Wang <ren-ting.wang@mediatek.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef _TOPS_TRM_H_ |
| 10 | #define _TOPS_TRM_H_ |
| 11 | |
| 12 | #include <linux/platform_device.h> |
| 13 | |
| 14 | extern struct device *trm_dev; |
| 15 | |
| 16 | #define TRM_DBG(fmt, ...) dev_dbg(trm_dev, "[TRM] " fmt, ##__VA_ARGS__) |
| 17 | #define TRM_INFO(fmt, ...) dev_info(trm_dev, "[TRM] " fmt, ##__VA_ARGS__) |
| 18 | #define TRM_NOTICE(fmt, ...) dev_notice(trm_dev, "[TRM] " fmt, ##__VA_ARGS__) |
| 19 | #define TRM_WARN(fmt, ...) dev_warn(trm_dev, "[TRM] " fmt, ##__VA_ARGS__) |
| 20 | #define TRM_ERR(fmt, ...) dev_err(trm_dev, "[TRM] " fmt, ##__VA_ARGS__) |
| 21 | |
| 22 | #define TRM_CONFIG_NAME_MAX_LEN 32 |
| 23 | |
| 24 | /* TRM Configuration */ |
| 25 | #define TRM_CFG(_name, _addr, _len, _ofs, _size, _flag) \ |
| 26 | .name = _name, \ |
| 27 | .addr = _addr, \ |
| 28 | .len = _len, \ |
| 29 | .offset = _ofs, \ |
| 30 | .size = _size, \ |
| 31 | .flag = _flag, |
| 32 | |
| 33 | #define TRM_CFG_EN(name, addr, len, ofs, size, flag) \ |
| 34 | TRM_CFG(name, addr, len, ofs, size, TRM_CONFIG_F_ENABLE | (flag)) |
| 35 | |
| 36 | #define TRM_CFG_CORE_DUMP_EN(name, addr, len, ofs, size, flag, core_id) \ |
| 37 | TRM_CFG_EN(name, addr, len, ofs, size, TRM_CONFIG_F_CORE_DUMP | flag) \ |
| 38 | .core = core_id |
| 39 | |
| 40 | /* TRM configuration flags */ |
| 41 | #define TRM_CONFIG_F(trm_cfg_bit) \ |
| 42 | (BIT(TRM_CONFIG_F_ ## trm_cfg_bit ## _BIT)) |
| 43 | #define TRM_CONFIG_F_CX_CORE_DUMP_MASK (GENMASK(CORE_TOPS_NUM, 0)) |
| 44 | #define TRM_CONFIG_F_CX_CORE_DUMP_SHIFT (0) |
| 45 | |
| 46 | /* TRM reason flag */ |
| 47 | #define TRM_RSN(trm_rsn_bit) (BIT(TRM_RSN_ ## trm_rsn_bit ## _BIT)) |
| 48 | |
| 49 | /* TRM Reason */ |
| 50 | #define TRM_RSN_NULL (0x0000) |
| 51 | #define TRM_RSN_WDT_TIMEOUT_CORE0 (TRM_RSN(C0_WDT)) |
| 52 | #define TRM_RSN_WDT_TIMEOUT_CORE1 (TRM_RSN(C1_WDT)) |
| 53 | #define TRM_RSN_WDT_TIMEOUT_CORE2 (TRM_RSN(C2_WDT)) |
| 54 | #define TRM_RSN_WDT_TIMEOUT_CORE3 (TRM_RSN(C3_WDT)) |
| 55 | #define TRM_RSN_WDT_TIMEOUT_COREM (TRM_RSN(CM_WDT)) |
| 56 | #define TRM_RSN_FE_RESET (TRM_RSN(FE_RESET)) |
| 57 | #define TRM_RSN_MCU_STATE_ACT_FAIL (TRM_RSN(MCU_STATE_ACT_FAIL)) |
| 58 | |
developer | fbdb511 | 2023-08-21 15:12:14 +0800 | [diff] [blame^] | 59 | enum trm_cmd_type { |
| 60 | TRM_CMD_TYPE_NULL, |
| 61 | TRM_CMD_TYPE_CPU_UTILIZATION, |
| 62 | |
| 63 | __TRM_CMD_TYPE_MAX, |
| 64 | }; |
| 65 | |
developer | e5e687d | 2023-08-08 16:05:33 +0800 | [diff] [blame] | 66 | enum trm_config_flag { |
| 67 | TRM_CONFIG_F_ENABLE_BIT, |
| 68 | TRM_CONFIG_F_CORE_DUMP_BIT, |
| 69 | }; |
| 70 | |
| 71 | enum trm_rsn { |
| 72 | TRM_RSN_C0_WDT_BIT, |
| 73 | TRM_RSN_C1_WDT_BIT, |
| 74 | TRM_RSN_C2_WDT_BIT, |
| 75 | TRM_RSN_C3_WDT_BIT, |
| 76 | TRM_RSN_CM_WDT_BIT, |
| 77 | TRM_RSN_FE_RESET_BIT, |
| 78 | TRM_RSN_MCU_STATE_ACT_FAIL_BIT, |
| 79 | }; |
| 80 | |
| 81 | enum trm_hardware { |
| 82 | TRM_TOPS, |
| 83 | TRM_NETSYS, |
| 84 | TRM_TDMA, |
| 85 | |
| 86 | __TRM_HARDWARE_MAX, |
| 87 | }; |
| 88 | |
| 89 | struct trm_config { |
| 90 | char name[TRM_CONFIG_NAME_MAX_LEN]; |
| 91 | enum core_id core; /* valid if TRM_CONFIG_F_CORE_DUMP is set */ |
| 92 | u32 addr; /* memory address of the dump info */ |
| 93 | u32 len; /* total length of the dump info */ |
| 94 | u32 offset; /* dump offset */ |
| 95 | u32 size; /* dump size */ |
| 96 | u8 flag; |
| 97 | #define TRM_CONFIG_F_CORE_DUMP (TRM_CONFIG_F(CORE_DUMP)) |
| 98 | #define TRM_CONFIG_F_ENABLE (TRM_CONFIG_F(ENABLE)) |
| 99 | }; |
| 100 | |
| 101 | struct trm_hw_config { |
| 102 | struct trm_config *trm_cfgs; |
| 103 | u32 cfg_len; |
| 104 | int (*trm_hw_dump)(void *dst, u32 ofs, u32 len); |
| 105 | }; |
| 106 | |
developer | fbdb511 | 2023-08-21 15:12:14 +0800 | [diff] [blame^] | 107 | int mtk_trm_cpu_utilization(enum core_id core, u32 *cpu_utilization); |
developer | e5e687d | 2023-08-08 16:05:33 +0800 | [diff] [blame] | 108 | int mtk_trm_dump(u32 dump_rsn); |
| 109 | int mtk_trm_cfg_setup(char *name, u32 offset, u32 size, u8 enable); |
| 110 | int mtk_tops_trm_init(void); |
| 111 | void mtk_tops_trm_exit(void); |
| 112 | int mtk_trm_hw_config_register(enum trm_hardware trm_hw, |
| 113 | struct trm_hw_config *trm_hw_cfg); |
| 114 | void mtk_trm_hw_config_unregister(enum trm_hardware trm_hw, |
| 115 | struct trm_hw_config *trm_hw_cfg); |
| 116 | #endif /* _TOPS_TRM_H_ */ |