Gitiles
Code Review Sign In
git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / fbdb511811b97a641779c7a29eb96de104deb4dd / . / autobuild_mac80211_release / mt7988_mt7996_mac80211 / package / kernel / mt76 / patches / 1000-wifi-mt76-mt7996-add-debug-tool.patch
blob: fcc450e0243b6df372155caa2fc508cb73c01a9c [file] [log] [blame]
developerd04aab52023-06-29 17:01:37 +0800[diff] [blame]1From 16ea1c12d369ea1f315edcc7a8525efc6d78403a Mon Sep 17 00:00:00 2001
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Fri, 24 Mar 2023 14:02:32 +0800
developerd04aab52023-06-29 17:01:37 +0800[diff] [blame]4Subject: [PATCH] wifi: mt76: mt7996: add debug tool
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]5
6Change-Id: Ie10390b01f17db893dbfbf3221bf63a4bd1fe38f
7---
8 mt7996/Makefile | 3 +
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]9 mt7996/coredump.c | 10 +-
10 mt7996/coredump.h | 7 +
developerd04aab52023-06-29 17:01:37 +0800[diff] [blame]11 mt7996/debugfs.c | 24 +-
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]12 mt7996/mt7996.h | 14 +
13 mt7996/mtk_debug.h | 2165 ++++++++++++++++++++++++++++++++++++++
14 mt7996/mtk_debugfs.c | 2353 ++++++++++++++++++++++++++++++++++++++++++
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]15 mt7996/mtk_mcu.c | 18 +
16 mt7996/mtk_mcu.h | 16 +
17 tools/fwlog.c | 25 +-
developerd04aab52023-06-29 17:01:37 +0800[diff] [blame]18 10 files changed, 4617 insertions(+), 18 deletions(-)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]19 create mode 100644 mt7996/mtk_debug.h
20 create mode 100644 mt7996/mtk_debugfs.c
21 create mode 100644 mt7996/mtk_mcu.c
22 create mode 100644 mt7996/mtk_mcu.h
23
24diff --git a/mt7996/Makefile b/mt7996/Makefile
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]25index 7c2514a6..df131869 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]26--- a/mt7996/Makefile
27+++ b/mt7996/Makefile
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]28@@ -1,5 +1,6 @@
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]29 # SPDX-License-Identifier: ISC
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]30 EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]31+EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG
32
33 obj-$(CONFIG_MT7996E) += mt7996e.o
34
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]35@@ -9,3 +10,5 @@ mt7996e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
developerde9ecce2023-05-22 11:17:16 +0800[diff] [blame]36 mt7996e-$(CONFIG_DEV_COREDUMP) += coredump.o
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]37
38 mt7996e-$(CONFIG_NL80211_TESTMODE) += testmode.o
39+
40+mt7996e-y += mtk_debugfs.o mtk_mcu.o
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]41diff --git a/mt7996/coredump.c b/mt7996/coredump.c
42index 60b88085..a7f91b56 100644
43--- a/mt7996/coredump.c
44+++ b/mt7996/coredump.c
45@@ -195,7 +195,7 @@ mt7996_coredump_fw_stack(struct mt7996_dev *dev, u8 type, struct mt7996_coredump
46 }
47 }
48
49-static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type)
50+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
51 {
52 struct mt7996_crash_data *crash_data = dev->coredump.crash_data[type];
53 struct mt7996_coredump *dump;
54@@ -206,7 +206,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
55
56 len = hdr_len;
57
58- if (coredump_memdump && crash_data->memdump_buf_len)
59+ if (full_dump && coredump_memdump && crash_data->memdump_buf_len)
60 len += sizeof(*dump_mem) + crash_data->memdump_buf_len;
61
62 sofar += hdr_len;
63@@ -248,6 +248,9 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
64 mt7996_coredump_fw_state(dev, type, dump, &exception);
65 mt7996_coredump_fw_stack(dev, type, dump, exception);
66
67+ if (!full_dump)
68+ goto skip_dump_mem;
69+
70 /* gather memory content */
71 dump_mem = (struct mt7996_coredump_mem *)(buf + sofar);
72 dump_mem->len = crash_data->memdump_buf_len;
73@@ -255,6 +258,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
74 memcpy(dump_mem->data, crash_data->memdump_buf,
75 crash_data->memdump_buf_len);
76
77+skip_dump_mem:
78 mutex_unlock(&dev->dump_mutex);
79
80 return dump;
81@@ -264,7 +268,7 @@ int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
82 {
83 struct mt7996_coredump *dump;
84
85- dump = mt7996_coredump_build(dev, type);
86+ dump = mt7996_coredump_build(dev, type, true);
87 if (!dump) {
88 dev_warn(dev->mt76.dev, "no crash dump data found\n");
89 return -ENODATA;
90diff --git a/mt7996/coredump.h b/mt7996/coredump.h
91index 01ed3731..93cd84a0 100644
92--- a/mt7996/coredump.h
93+++ b/mt7996/coredump.h
94@@ -75,6 +75,7 @@ struct mt7996_mem_region {
95 const struct mt7996_mem_region *
96 mt7996_coredump_get_mem_layout(struct mt7996_dev *dev, u8 type, u32 *num);
97 struct mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type);
98+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump);
99 int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type);
100 int mt7996_coredump_register(struct mt7996_dev *dev);
101 void mt7996_coredump_unregister(struct mt7996_dev *dev);
102@@ -92,6 +93,12 @@ static inline int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
103 return 0;
104 }
105
106+static inline struct
107+mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
108+{
109+ return NULL;
110+}
111+
112 static inline struct
113 mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type)
114 {
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]115diff --git a/mt7996/debugfs.c b/mt7996/debugfs.c
developerd04aab52023-06-29 17:01:37 +0800[diff] [blame]116index ca4d615d..93581fef 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]117--- a/mt7996/debugfs.c
118+++ b/mt7996/debugfs.c
developerde9ecce2023-05-22 11:17:16 +0800[diff] [blame]119@@ -301,6 +301,9 @@ mt7996_fw_debug_wm_set(void *data, u64 val)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]120 int ret;
121
122 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
123+#ifdef CONFIG_MTK_DEBUG
124+ dev->fw_debug_wm = val;
125+#endif
126
127 if (dev->fw_debug_bin)
128 val = MCU_FW_LOG_RELAY;
developerd04aab52023-06-29 17:01:37 +0800[diff] [blame]129@@ -407,11 +410,12 @@ mt7996_fw_debug_bin_set(void *data, u64 val)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]130 };
131 struct mt7996_dev *dev = data;
132
133- if (!dev->relay_fwlog)
134+ if (!dev->relay_fwlog) {
135 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
136 1500, 512, &relay_cb, NULL);
137- if (!dev->relay_fwlog)
138- return -ENOMEM;
139+ if (!dev->relay_fwlog)
140+ return -ENOMEM;
141+ }
142
143 dev->fw_debug_bin = val;
144
developerd04aab52023-06-29 17:01:37 +0800[diff] [blame]145@@ -825,6 +829,11 @@ int mt7996_init_debugfs(struct mt7996_phy *phy)
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]146 if (phy == &dev->phy)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]147 dev->debugfs_dir = dir;
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]148
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]149+#ifdef CONFIG_MTK_DEBUG
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]150+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
151+ mt7996_mtk_init_debugfs(phy, dir);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]152+#endif
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]153+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]154 return 0;
155 }
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]156
developerd04aab52023-06-29 17:01:37 +0800[diff] [blame]157@@ -837,6 +846,12 @@ mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen,
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]158 void *dest;
159
160 spin_lock_irqsave(&lock, flags);
161+
162+ if (!dev->relay_fwlog) {
163+ spin_unlock_irqrestore(&lock, flags);
164+ return;
165+ }
166+
167 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
168 if (dest) {
169 *(u32 *)dest = hdrlen + len;
developerd04aab52023-06-29 17:01:37 +0800[diff] [blame]170@@ -869,9 +884,6 @@ void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]171 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
172 };
173
174- if (!dev->relay_fwlog)
175- return;
176-
177 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++);
178 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
179 hdr.len = *(__le16 *)data;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]180diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]181index 286fc1eb..6c76ec20 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]182--- a/mt7996/mt7996.h
183+++ b/mt7996/mt7996.h
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]184@@ -363,6 +363,16 @@ struct mt7996_dev {
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]185 u32 reg_l2_backup;
186
187 u8 wtbl_size_group;
188+
189+#ifdef CONFIG_MTK_DEBUG
190+ u16 wlan_idx;
191+ struct {
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]192+ u8 sku_disable;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]193+ u32 fw_dbg_module;
194+ u8 fw_dbg_lv;
195+ u32 bcn_total_cnt[__MT_MAX_BAND];
196+ } dbg;
197+#endif
198 };
199
200 enum {
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]201@@ -659,4 +669,8 @@ void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]202 struct ieee80211_sta *sta, struct dentry *dir);
203 #endif
204
205+#ifdef CONFIG_MTK_DEBUG
206+int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);
207+#endif
208+
209 #endif
210diff --git a/mt7996/mtk_debug.h b/mt7996/mtk_debug.h
211new file mode 100644
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]212index 00000000..eb40f9cb
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]213--- /dev/null
214+++ b/mt7996/mtk_debug.h
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]215@@ -0,0 +1,2165 @@
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]216+#ifndef __MTK_DEBUG_H
217+#define __MTK_DEBUG_H
218+
219+#ifdef CONFIG_MTK_DEBUG
220+#define NO_SHIFT_DEFINE 0xFFFFFFFF
221+#define BITS(m, n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n)))
222+
223+#define GET_FIELD(_field, _reg) \
224+ ({ \
225+ (((_reg) & (_field##_MASK)) >> (_field##_SHIFT)); \
226+ })
227+
228+/* AGG */
229+#define BN0_WF_AGG_TOP_BASE 0x820e2000
230+#define BN1_WF_AGG_TOP_BASE 0x820f2000
231+#define IP1_BN0_WF_AGG_TOP_BASE 0x830e2000
232+
233+#define BN0_WF_AGG_TOP_SCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x0) // 2000
234+#define BN0_WF_AGG_TOP_SCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x4) // 2004
235+#define BN0_WF_AGG_TOP_SCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x8) // 2008
236+#define BN0_WF_AGG_TOP_BCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xc) // 200C
237+#define BN0_WF_AGG_TOP_BWCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x10) // 2010
238+#define BN0_WF_AGG_TOP_ARCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x14) // 2014
239+#define BN0_WF_AGG_TOP_ARUCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x18) // 2018
240+#define BN0_WF_AGG_TOP_ARDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x1c) // 201C
241+#define BN0_WF_AGG_TOP_AALCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x20) // 2020
242+#define BN0_WF_AGG_TOP_AALCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x24) // 2024
243+#define BN0_WF_AGG_TOP_PCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x28) // 2028
244+#define BN0_WF_AGG_TOP_PCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c) // 202C
245+#define BN0_WF_AGG_TOP_TTCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x30) // 2030
246+#define BN0_WF_AGG_TOP_TTCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x34) // 2034
247+#define BN0_WF_AGG_TOP_ACR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x38) // 2038
248+#define BN0_WF_AGG_TOP_ACR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x3c) // 203C
249+#define BN0_WF_AGG_TOP_ACR5_ADDR (BN0_WF_AGG_TOP_BASE + 0x40) // 2040
250+#define BN0_WF_AGG_TOP_ACR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x44) // 2044
251+#define BN0_WF_AGG_TOP_ACR8_ADDR (BN0_WF_AGG_TOP_BASE + 0x4c) // 204C
252+#define BN0_WF_AGG_TOP_MRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x50) // 2050
253+#define BN0_WF_AGG_TOP_MMPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x54) // 2054
254+#define BN0_WF_AGG_TOP_GFPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x58) // 2058
255+#define BN0_WF_AGG_TOP_VHTPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x5c) // 205C
256+#define BN0_WF_AGG_TOP_HEPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x60) // 2060
257+#define BN0_WF_AGG_TOP_CTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x64) // 2064
258+#define BN0_WF_AGG_TOP_ATCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x68) // 2068
259+#define BN0_WF_AGG_TOP_SRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x6c) // 206C
260+#define BN0_WF_AGG_TOP_VBCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x70) // 2070
261+#define BN0_WF_AGG_TOP_TCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x74) // 2074
262+#define BN0_WF_AGG_TOP_SRHS_ADDR (BN0_WF_AGG_TOP_BASE + 0x78) // 2078
263+#define BN0_WF_AGG_TOP_DBRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x7c) // 207C
264+#define BN0_WF_AGG_TOP_DBRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x80) // 2080
265+#define BN0_WF_AGG_TOP_CTETCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x84) // 2084
266+#define BN0_WF_AGG_TOP_WPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x88) // 2088
267+#define BN0_WF_AGG_TOP_PLRPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x8c) // 208C
268+#define BN0_WF_AGG_TOP_CECR_ADDR (BN0_WF_AGG_TOP_BASE + 0x90) // 2090
269+#define BN0_WF_AGG_TOP_OMRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x94) // 2094
270+#define BN0_WF_AGG_TOP_OMRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x98) // 2098
271+#define BN0_WF_AGG_TOP_OMRCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x9c) // 209C
272+#define BN0_WF_AGG_TOP_OMRCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xa0) // 20A0
273+#define BN0_WF_AGG_TOP_TMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa4) // 20A4
274+#define BN0_WF_AGG_TOP_TWTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa8) // 20A8
275+#define BN0_WF_AGG_TOP_TWTSTACR_ADDR (BN0_WF_AGG_TOP_BASE + 0xac) // 20AC
276+#define BN0_WF_AGG_TOP_TWTE0TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb0) // 20B0
277+#define BN0_WF_AGG_TOP_TWTE1TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb4) // 20B4
278+#define BN0_WF_AGG_TOP_TWTE2TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb8) // 20B8
279+#define BN0_WF_AGG_TOP_TWTE3TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xbc) // 20BC
280+#define BN0_WF_AGG_TOP_TWTE4TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc0) // 20C0
281+#define BN0_WF_AGG_TOP_TWTE5TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc4) // 20C4
282+#define BN0_WF_AGG_TOP_TWTE6TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc8) // 20C8
283+#define BN0_WF_AGG_TOP_TWTE7TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xcc) // 20CC
284+#define BN0_WF_AGG_TOP_TWTE8TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd0) // 20D0
285+#define BN0_WF_AGG_TOP_TWTE9TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd4) // 20D4
286+#define BN0_WF_AGG_TOP_TWTEATB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd8) // 20D8
287+#define BN0_WF_AGG_TOP_TWTEBTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xdc) // 20DC
288+#define BN0_WF_AGG_TOP_TWTECTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe0) // 20E0
289+#define BN0_WF_AGG_TOP_TWTEDTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe4) // 20E4
290+#define BN0_WF_AGG_TOP_TWTEETB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe8) // 20E8
291+#define BN0_WF_AGG_TOP_TWTEFTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xec) // 20EC
292+#define BN0_WF_AGG_TOP_AALCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0xf0) // 20F0
293+#define BN0_WF_AGG_TOP_AALCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xf4) // 20F4
294+#define BN0_WF_AGG_TOP_AALCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0xf8) // 20F8
295+#define BN0_WF_AGG_TOP_AALCR5_ADDR (BN0_WF_AGG_TOP_BASE + 0xfc) // 20FC
296+#define BN0_WF_AGG_TOP_AALCR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x100) // 2100
297+#define BN0_WF_AGG_TOP_AALCR7_ADDR (BN0_WF_AGG_TOP_BASE + 0x104) // 2104
298+#define BN0_WF_AGG_TOP_ATCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x108) // 2108
299+#define BN0_WF_AGG_TOP_ATCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x10c) // 210C
300+#define BN0_WF_AGG_TOP_TCCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x110) // 2110
301+#define BN0_WF_AGG_TOP_TFCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x114) // 2114
302+#define BN0_WF_AGG_TOP_MUCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x118) // 2118
303+#define BN0_WF_AGG_TOP_MUCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x11c) // 211C
304+#define BN0_WF_AGG_TOP_CSDCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x120) // 2120
305+#define BN0_WF_AGG_TOP_CSDCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x124) // 2124
306+#define BN0_WF_AGG_TOP_CSDCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x128) // 2128
307+#define BN0_WF_AGG_TOP_CSDCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x12c) // 212C
308+#define BN0_WF_AGG_TOP_CSDCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x130) // 2130
309+#define BN0_WF_AGG_TOP_DYNSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x178) // 2178
310+#define BN0_WF_AGG_TOP_DYNSSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x198) // 2198
311+#define BN0_WF_AGG_TOP_TCDCNT0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c8) // 22C8
312+#define BN0_WF_AGG_TOP_TCDCNT1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2cc) // 22CC
313+#define BN0_WF_AGG_TOP_TCSR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d0) // 22D0
314+#define BN0_WF_AGG_TOP_TCSR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d4) // 22D4
315+#define BN0_WF_AGG_TOP_TCSR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d8) // 22D8
316+#define BN0_WF_AGG_TOP_DCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e4) // 22E4
317+#define BN0_WF_AGG_TOP_SMDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e8) // 22E8
318+#define BN0_WF_AGG_TOP_TXCMDSMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2ec) // 22EC
319+#define BN0_WF_AGG_TOP_SMCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f0) // 22F0
320+#define BN0_WF_AGG_TOP_SMCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f4) // 22F4
321+#define BN0_WF_AGG_TOP_SMCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f8) // 22F8
322+#define BN0_WF_AGG_TOP_SMCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x2fc) // 22FC
323+
324+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
325+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK 0x03FF0000 // AC01_AGG_LIMIT[25..16]
326+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT 16
327+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
328+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK 0x000003FF // AC00_AGG_LIMIT[9..0]
329+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT 0
330+
331+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
332+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK 0x03FF0000 // AC03_AGG_LIMIT[25..16]
333+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT 16
334+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
335+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK 0x000003FF // AC02_AGG_LIMIT[9..0]
336+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT 0
337+
338+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
339+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK 0x03FF0000 // AC11_AGG_LIMIT[25..16]
340+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT 16
341+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
342+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK 0x000003FF // AC10_AGG_LIMIT[9..0]
343+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT 0
344+
345+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
346+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK 0x03FF0000 // AC13_AGG_LIMIT[25..16]
347+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT 16
348+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
349+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK 0x000003FF // AC12_AGG_LIMIT[9..0]
350+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT 0
351+
352+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
353+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK 0x03FF0000 // AC21_AGG_LIMIT[25..16]
354+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT 16
355+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
356+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK 0x000003FF // AC20_AGG_LIMIT[9..0]
357+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT 0
358+
359+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
360+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK 0x03FF0000 // AC23_AGG_LIMIT[25..16]
361+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT 16
362+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
363+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK 0x000003FF // AC22_AGG_LIMIT[9..0]
364+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT 0
365+
366+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
367+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK 0x03FF0000 // AC31_AGG_LIMIT[25..16]
368+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT 16
369+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
370+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK 0x000003FF // AC30_AGG_LIMIT[9..0]
371+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT 0
372+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
373+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK 0x03FF0000 // AC33_AGG_LIMIT[25..16]
374+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT 16
375+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
376+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK 0x000003FF // AC32_AGG_LIMIT[9..0]
377+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT 0
378+
379+/* DMA */
380+struct queue_desc {
381+ u32 hw_desc_base;
382+ u16 ring_size;
383+ char *const ring_info;
384+};
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]385+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]386+// HOST DMA
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]387+#define WF_WFDMA_HOST_DMA0_BASE 0xd4000
388+
389+#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR \
390+ (WF_WFDMA_HOST_DMA0_BASE + 0x200) /* 4200 */
391+#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR \
392+ (WF_WFDMA_HOST_DMA0_BASE + 0X204) /* 4204 */
393+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR \
394+ (WF_WFDMA_HOST_DMA0_BASE + 0x208) /* 4208 */
395+
396+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR \
397+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
398+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK \
399+ 0x00000008 /* RX_DMA_BUSY[3] */
400+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
401+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR \
402+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
403+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK \
404+ 0x00000004 /* RX_DMA_EN[2] */
405+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
406+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR \
407+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
408+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK \
409+ 0x00000002 /* TX_DMA_BUSY[1] */
410+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
411+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR \
412+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
413+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK \
414+ 0x00000001 /* TX_DMA_EN[0] */
415+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
416+
417+
418+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR \
419+ (WF_WFDMA_HOST_DMA0_BASE + 0x300) /* 4300 */
420+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL1_ADDR \
421+ (WF_WFDMA_HOST_DMA0_BASE + 0x304) /* 4304 */
422+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL2_ADDR \
423+ (WF_WFDMA_HOST_DMA0_BASE + 0x308) /* 4308 */
424+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL3_ADDR \
425+ (WF_WFDMA_HOST_DMA0_BASE + 0x30c) /* 430C */
426+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR \
427+ (WF_WFDMA_HOST_DMA0_BASE + 0x310) /* 4310 */
428+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL1_ADDR \
429+ (WF_WFDMA_HOST_DMA0_BASE + 0x314) /* 4314 */
430+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL2_ADDR \
431+ (WF_WFDMA_HOST_DMA0_BASE + 0x318) /* 4318 */
432+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL3_ADDR \
433+ (WF_WFDMA_HOST_DMA0_BASE + 0x31c) /* 431C */
434+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR \
435+ (WF_WFDMA_HOST_DMA0_BASE + 0x320) /* 4320 */
436+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL1_ADDR \
437+ (WF_WFDMA_HOST_DMA0_BASE + 0x324) /* 4324 */
438+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL2_ADDR \
439+ (WF_WFDMA_HOST_DMA0_BASE + 0x328) /* 4328 */
440+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL3_ADDR \
441+ (WF_WFDMA_HOST_DMA0_BASE + 0x32c) /* 432C */
442+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR \
443+ (WF_WFDMA_HOST_DMA0_BASE + 0x330) /* 4330 */
444+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL1_ADDR \
445+ (WF_WFDMA_HOST_DMA0_BASE + 0x334) /* 4334 */
446+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL2_ADDR \
447+ (WF_WFDMA_HOST_DMA0_BASE + 0x338) /* 4338 */
448+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL3_ADDR \
449+ (WF_WFDMA_HOST_DMA0_BASE + 0x33c) /* 433C */
450+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR \
451+ (WF_WFDMA_HOST_DMA0_BASE + 0x340) /* 4340 */
452+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL1_ADDR \
453+ (WF_WFDMA_HOST_DMA0_BASE + 0x344) /* 4344 */
454+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL2_ADDR \
455+ (WF_WFDMA_HOST_DMA0_BASE + 0x348) /* 4348 */
456+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL3_ADDR \
457+ (WF_WFDMA_HOST_DMA0_BASE + 0x34c) /* 434C */
458+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR \
459+ (WF_WFDMA_HOST_DMA0_BASE + 0x350) /* 4350 */
460+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL1_ADDR \
461+ (WF_WFDMA_HOST_DMA0_BASE + 0x354) /* 4354 */
462+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL2_ADDR \
463+ (WF_WFDMA_HOST_DMA0_BASE + 0x358) /* 4358 */
464+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL3_ADDR \
465+ (WF_WFDMA_HOST_DMA0_BASE + 0x35c) /* 435C */
466+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR \
467+ (WF_WFDMA_HOST_DMA0_BASE + 0x360) /* 4360 */
468+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL1_ADDR \
469+ (WF_WFDMA_HOST_DMA0_BASE + 0x364) /* 4364 */
470+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL2_ADDR \
471+ (WF_WFDMA_HOST_DMA0_BASE + 0x368) /* 4368 */
472+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL3_ADDR \
473+ (WF_WFDMA_HOST_DMA0_BASE + 0x36c) /* 436C */
474+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR \
475+ (WF_WFDMA_HOST_DMA0_BASE + 0x400) /* 4400 */
476+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL1_ADDR \
477+ (WF_WFDMA_HOST_DMA0_BASE + 0x404) /* 4404 */
478+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL2_ADDR \
479+ (WF_WFDMA_HOST_DMA0_BASE + 0x408) /* 4408 */
480+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL3_ADDR \
481+ (WF_WFDMA_HOST_DMA0_BASE + 0x40c) /* 440C */
482+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR \
483+ (WF_WFDMA_HOST_DMA0_BASE + 0x410) /* 4410 */
484+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL1_ADDR \
485+ (WF_WFDMA_HOST_DMA0_BASE + 0x414) /* 4414 */
486+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL2_ADDR \
487+ (WF_WFDMA_HOST_DMA0_BASE + 0x418) /* 4418 */
488+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL3_ADDR \
489+ (WF_WFDMA_HOST_DMA0_BASE + 0x41c) /* 441C */
490+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR \
491+ (WF_WFDMA_HOST_DMA0_BASE + 0x420) /* 4420 */
492+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL1_ADDR \
493+ (WF_WFDMA_HOST_DMA0_BASE + 0x424) /* 4424 */
494+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL2_ADDR \
495+ (WF_WFDMA_HOST_DMA0_BASE + 0x428) /* 4428 */
496+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL3_ADDR \
497+ (WF_WFDMA_HOST_DMA0_BASE + 0x42c) /* 442C */
498+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR \
499+ (WF_WFDMA_HOST_DMA0_BASE + 0x430) /* 4430 */
500+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL1_ADDR \
501+ (WF_WFDMA_HOST_DMA0_BASE + 0x434) /* 4434 */
502+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL2_ADDR \
503+ (WF_WFDMA_HOST_DMA0_BASE + 0x438) /* 4438 */
504+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL3_ADDR \
505+ (WF_WFDMA_HOST_DMA0_BASE + 0x43c) /* 443C */
506+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR \
507+ (WF_WFDMA_HOST_DMA0_BASE + 0x440) /* 4440 */
508+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL1_ADDR \
509+ (WF_WFDMA_HOST_DMA0_BASE + 0x444) /* 4444 */
510+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL2_ADDR \
511+ (WF_WFDMA_HOST_DMA0_BASE + 0x448) /* 4448 */
512+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL3_ADDR \
513+ (WF_WFDMA_HOST_DMA0_BASE + 0x44c) /* 444C */
514+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR \
515+ (WF_WFDMA_HOST_DMA0_BASE + 0x450) /* 4450 */
516+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL1_ADDR \
517+ (WF_WFDMA_HOST_DMA0_BASE + 0x454) /* 4454 */
518+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL2_ADDR \
519+ (WF_WFDMA_HOST_DMA0_BASE + 0x458) /* 4458 */
520+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL3_ADDR \
521+ (WF_WFDMA_HOST_DMA0_BASE + 0x45c) /* 445c */
522+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x460) // 4460
523+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x464) // 4464
524+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x468) // 4468
525+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x46c) // 446C
526+
527+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR \
528+ (WF_WFDMA_HOST_DMA0_BASE + 0x500) /* 4500 */
529+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL1_ADDR \
530+ (WF_WFDMA_HOST_DMA0_BASE + 0x504) /* 4504 */
531+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL2_ADDR \
532+ (WF_WFDMA_HOST_DMA0_BASE + 0x508) /* 4508 */
533+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL3_ADDR \
534+ (WF_WFDMA_HOST_DMA0_BASE + 0x50c) /* 450C */
535+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR \
536+ (WF_WFDMA_HOST_DMA0_BASE + 0x510) /* 4510 */
537+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL1_ADDR \
538+ (WF_WFDMA_HOST_DMA0_BASE + 0x514) /* 4514 */
539+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL2_ADDR \
540+ (WF_WFDMA_HOST_DMA0_BASE + 0x518) /* 4518 */
541+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL3_ADDR \
542+ (WF_WFDMA_HOST_DMA0_BASE + 0x51c) /* 451C */
543+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR \
544+ (WF_WFDMA_HOST_DMA0_BASE + 0x520) /* 4520 */
545+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL1_ADDR \
546+ (WF_WFDMA_HOST_DMA0_BASE + 0x524) /* 4524 */
547+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL2_ADDR \
548+ (WF_WFDMA_HOST_DMA0_BASE + 0x528) /* 4528 */
549+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL3_ADDR \
550+ (WF_WFDMA_HOST_DMA0_BASE + 0x52C) /* 452C */
551+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR \
552+ (WF_WFDMA_HOST_DMA0_BASE + 0x530) /* 4530 */
553+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL1_ADDR \
554+ (WF_WFDMA_HOST_DMA0_BASE + 0x534) /* 4534 */
555+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL2_ADDR \
556+ (WF_WFDMA_HOST_DMA0_BASE + 0x538) /* 4538 */
557+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL3_ADDR \
558+ (WF_WFDMA_HOST_DMA0_BASE + 0x53C) /* 453C */
559+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR \
560+ (WF_WFDMA_HOST_DMA0_BASE + 0x540) /* 4540 */
561+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL1_ADDR \
562+ (WF_WFDMA_HOST_DMA0_BASE + 0x544) /* 4544 */
563+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL2_ADDR \
564+ (WF_WFDMA_HOST_DMA0_BASE + 0x548) /* 4548 */
565+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL3_ADDR \
566+ (WF_WFDMA_HOST_DMA0_BASE + 0x54c) /* 454C */
567+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR \
568+ (WF_WFDMA_HOST_DMA0_BASE + 0x550) /* 4550 */
569+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL1_ADDR \
570+ (WF_WFDMA_HOST_DMA0_BASE + 0x554) /* 4554 */
571+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL2_ADDR \
572+ (WF_WFDMA_HOST_DMA0_BASE + 0x558) /* 4558 */
573+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL3_ADDR \
574+ (WF_WFDMA_HOST_DMA0_BASE + 0x55c) /* 455C */
575+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR \
576+ (WF_WFDMA_HOST_DMA0_BASE + 0x560) /* 4560 */
577+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL1_ADDR \
578+ (WF_WFDMA_HOST_DMA0_BASE + 0x564) /* 4564 */
579+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL2_ADDR \
580+ (WF_WFDMA_HOST_DMA0_BASE + 0x568) /* 4568 */
581+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL3_ADDR \
582+ (WF_WFDMA_HOST_DMA0_BASE + 0x56c) /* 456C */
583+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR \
584+ (WF_WFDMA_HOST_DMA0_BASE + 0x570) /* 4570 */
585+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL1_ADDR \
586+ (WF_WFDMA_HOST_DMA0_BASE + 0x574) /* 4574 */
587+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL2_ADDR \
588+ (WF_WFDMA_HOST_DMA0_BASE + 0x578) /* 4578 */
589+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL3_ADDR \
590+ (WF_WFDMA_HOST_DMA0_BASE + 0x57c) /* 457C */
591+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR \
592+ (WF_WFDMA_HOST_DMA0_BASE + 0x580) /* 4580 */
593+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL1_ADDR \
594+ (WF_WFDMA_HOST_DMA0_BASE + 0x584) /* 4584 */
595+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL2_ADDR \
596+ (WF_WFDMA_HOST_DMA0_BASE + 0x588) /* 4588 */
597+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL3_ADDR \
598+ (WF_WFDMA_HOST_DMA0_BASE + 0x58c) /* 458C */
599+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR \
600+ (WF_WFDMA_HOST_DMA0_BASE + 0x590) /* 4590 */
601+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL1_ADDR \
602+ (WF_WFDMA_HOST_DMA0_BASE + 0x594) /* 4594 */
603+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL2_ADDR \
604+ (WF_WFDMA_HOST_DMA0_BASE + 0x598) /* 4598 */
605+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL3_ADDR \
606+ (WF_WFDMA_HOST_DMA0_BASE + 0x59c) /* 459C */
607+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a0) // 45A0
608+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a4) // 45A4
609+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a8) // 45A8
610+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5ac) // 45AC
611+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b0) // 45B0
612+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b4) // 45B4
613+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b8) // 45B8
614+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5bc) // 45BC
615+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C0) // 45C0
616+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C4) // 45C4
617+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C8) // 45C8
618+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5CC) // 45CC
619+
620+// HOST PCIE1 DMA
621+#define WF_WFDMA_HOST_DMA0_PCIE1_BASE 0xd8000
622+
623+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x200) // 8200
624+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0X204) // 8204
625+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x208) // 8208
626+
627+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_PDMA_BT_SIZE_SHFT 4
628+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008
629+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
630+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004
631+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
632+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002
633+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
634+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001
635+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
636+
637+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x450) // 8450
638+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x454) // 8454
639+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x458) // 8458
640+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x45c) // 845C
641+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x460) // 8460
642+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x464) // 8464
643+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x468) // 8468
644+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x46c) // 846C
645+
646+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x530) // 8530
647+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x534) // 8534
648+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x538) // 8538
649+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x53C) // 853C
650+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x550) // 8550
651+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x554) // 8554
652+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x558) // 8558
653+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x55c) // 855C
654+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x560) // 8560
655+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x564) // 8564
656+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x568) // 8568
657+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x56c) // 856C
658+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x570) // 8570
659+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x574) // 8574
660+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x578) // 8578
661+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x57c) // 857C
662+//MCU DMA
663+//#define WF_WFDMA_MCU_DMA0_BASE 0x02000
664+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
665+
666+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
667+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
668+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
669+
670+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
671+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
672+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
673+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
674+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
675+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
676+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
677+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
678+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
679+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
680+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
681+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
682+
683+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
684+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x304) // 0304
685+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x308) // 0308
686+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x30c) // 030C
687+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
688+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x314) // 0314
689+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x318) // 0318
690+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x31c) // 031C
691+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
692+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x324) // 0324
693+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x328) // 0328
694+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x32c) // 032C
695+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
696+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x334) // 0334
697+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x338) // 0338
698+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x33c) // 033C
699+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
700+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x344) // 0344
701+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x348) // 0348
702+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x34c) // 034C
703+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
704+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x354) // 0354
705+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x358) // 0358
706+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x35c) // 035C
707+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
708+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x364) // 0364
709+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x368) // 0368
710+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x36c) // 036C
711+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x370) // 0370
712+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x374) // 0374
713+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x378) // 0378
714+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x37c) // 037C
715+
716+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
717+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x504) // 0504
718+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x508) // 0508
719+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x50c) // 050C
720+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
721+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x514) // 0514
722+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x518) // 0518
723+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x51c) // 051C
724+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
725+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x524) // 0524
726+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x528) // 0528
727+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x52C) // 052C
728+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
729+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x534) // 0534
730+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x538) // 0538
731+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x53C) // 053C
732+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
733+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x544) // 0544
734+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x548) // 0548
735+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x54C) // 054C
736+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
737+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x554) // 0554
738+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x558) // 0558
739+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x55C) // 055C
740+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
741+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x564) // 0564
742+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x568) // 0568
743+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x56c) // 056C
744+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
745+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x574) // 0574
746+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x578) // 0578
747+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x57c) // 057C
748+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
749+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x584) // 0584
750+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x588) // 0588
751+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x58c) // 058C
752+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
753+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x594) // 0594
754+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x598) // 0598
755+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x59c) // 059C
756+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A0) // 05A0
757+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A4) // 05A4
758+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A8) // 05A8
759+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5Ac) // 05AC
760+
761+// MEM DMA
762+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
763+
764+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
765+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
766+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
767+
768+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
769+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
770+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
771+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
772+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
773+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
774+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
775+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
776+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
777+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
778+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
779+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
780+
781+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
782+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x304) // 0304
783+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x308) // 0308
784+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x30c) // 030C
785+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
786+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x314) // 0314
787+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x318) // 0318
788+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x31c) // 031C
789+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x320) // 0320
790+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x324) // 0324
791+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x328) // 0328
792+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x32c) // 032C
793+
794+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
795+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x504) // 0504
796+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x508) // 0508
797+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x50c) // 050C
798+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
799+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x514) // 0514
800+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x518) // 0518
801+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x51c) // 051C
802+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x520) // 0520
803+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x524) // 0524
804+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x528) // 0528
805+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x52C) // 052C
806+
807+/* MIB */
808+#define WF_UMIB_TOP_BASE 0x820cd000
809+#define BN0_WF_MIB_TOP_BASE 0x820ed000
810+#define BN1_WF_MIB_TOP_BASE 0x820fd000
811+#define IP1_BN0_WF_MIB_TOP_BASE 0x830ed000
812+
813+#define WF_UMIB_TOP_B0BROCR_ADDR (WF_UMIB_TOP_BASE + 0x484) // D484
814+#define WF_UMIB_TOP_B0BRBCR_ADDR (WF_UMIB_TOP_BASE + 0x4D4) // D4D4
815+#define WF_UMIB_TOP_B0BRDCR_ADDR (WF_UMIB_TOP_BASE + 0x524) // D524
816+#define WF_UMIB_TOP_B1BROCR_ADDR (WF_UMIB_TOP_BASE + 0x5E8) // D5E8
817+#define WF_UMIB_TOP_B2BROCR_ADDR (WF_UMIB_TOP_BASE + 0x74C) // D74C
818+
819+#define BN0_WF_MIB_TOP_M0SCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x000) // D000
820+#define BN0_WF_MIB_TOP_M0SDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x020) // D020
821+#define BN0_WF_MIB_TOP_M0SDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x024) // D024
822+#define BN0_WF_MIB_TOP_M0SDR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x030) // D030
823+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
824+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x450) // D450
825+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x590) // D590
826+#define BN0_WF_MIB_TOP_BTCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5A0) // D5A0
827+#define BN0_WF_MIB_TOP_RVSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x720) // D720
828+
829+#define BN0_WF_MIB_TOP_TSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B0) // D6B0
830+#define BN0_WF_MIB_TOP_TSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6BC) // D6BC
831+#define BN0_WF_MIB_TOP_TSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C0) // D6C0
832+#define BN0_WF_MIB_TOP_TSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C4) // D6C4
833+#define BN0_WF_MIB_TOP_TSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C8) // D6C8
834+#define BN0_WF_MIB_TOP_TSCR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x6D0) // D6D0
835+#define BN0_WF_MIB_TOP_TSCR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x6CC) // D6CC
836+
837+#define BN0_WF_MIB_TOP_TBCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6EC) // D6EC
838+#define BN0_WF_MIB_TOP_TBCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F0) // D6F0
839+#define BN0_WF_MIB_TOP_TBCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F4) // D6F4
840+#define BN0_WF_MIB_TOP_TBCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F8) // D6F8
841+#define BN0_WF_MIB_TOP_TBCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6FC) // D6FC
842+
843+#define BN0_WF_MIB_TOP_TDRCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x728) // D728
844+#define BN0_WF_MIB_TOP_TDRCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x72C) // D72C
845+#define BN0_WF_MIB_TOP_TDRCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x730) // D730
846+#define BN0_WF_MIB_TOP_TDRCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x734) // D734
847+#define BN0_WF_MIB_TOP_TDRCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x738) // D738
848+
849+#define BN0_WF_MIB_TOP_BTSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
850+#define BN0_WF_MIB_TOP_BTSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x5F0) // D5F0
851+#define BN0_WF_MIB_TOP_BTSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x600) // D600
852+#define BN0_WF_MIB_TOP_BTSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x610) // D610
853+#define BN0_WF_MIB_TOP_BTSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x620) // D620
854+#define BN0_WF_MIB_TOP_BTSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x788) // D788
855+#define BN0_WF_MIB_TOP_BTSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x798) // D798
856+
857+#define BN0_WF_MIB_TOP_RSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x7AC) // D7AC
858+#define BN0_WF_MIB_TOP_BSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D4) // D9D4
859+#define BN0_WF_MIB_TOP_TSCR18_ADDR (BN0_WF_MIB_TOP_BASE + 0xA1C) // DA1C
860+
861+#define BN0_WF_MIB_TOP_MSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0xA64) // DA64
862+#define BN0_WF_MIB_TOP_MSR1_ADDR (BN0_WF_MIB_TOP_BASE + 0xA68) // DA68
863+#define BN0_WF_MIB_TOP_MSR2_ADDR (BN0_WF_MIB_TOP_BASE + 0xA6C) // DA6C
864+#define BN0_WF_MIB_TOP_MCTR5_ADDR (BN0_WF_MIB_TOP_BASE + 0xA70) // DA70
865+#define BN0_WF_MIB_TOP_MCTR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xA74) // DA74
866+
867+#define BN0_WF_MIB_TOP_RSCR26_ADDR (BN0_WF_MIB_TOP_BASE + 0x950) // D950
868+#define BN0_WF_MIB_TOP_RSCR27_ADDR (BN0_WF_MIB_TOP_BASE + 0x954) // D954
869+#define BN0_WF_MIB_TOP_RSCR28_ADDR (BN0_WF_MIB_TOP_BASE + 0x958) // D958
870+#define BN0_WF_MIB_TOP_RSCR31_ADDR (BN0_WF_MIB_TOP_BASE + 0x964) // D964
871+#define BN0_WF_MIB_TOP_RSCR33_ADDR (BN0_WF_MIB_TOP_BASE + 0x96C) // D96C
872+#define BN0_WF_MIB_TOP_RSCR35_ADDR (BN0_WF_MIB_TOP_BASE + 0x974) // D974
873+#define BN0_WF_MIB_TOP_RSCR36_ADDR (BN0_WF_MIB_TOP_BASE + 0x978) // D978
874+
875+#define BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK 0xFFFFFFFF // AMPDU_MPDU_COUNT[31..0]
876+#define BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK 0xFFFFFFFF // AMPDU_ACKED_COUNT[31..0]
877+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
878+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
879+#define BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK 0xFFFFFFFF // RX_MDRDY_COUNT[31..0]
880+#define BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK 0xFFFFFFFF // CCK_MDRDY_TIME[31..0]
881+#define BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[31..0]
882+#define BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_GREEN_MDRDY_TIME[31..0]
883+#define BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK 0xFFFFFFFF // P_CCA_TIME[31..0]
884+#define BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK 0xFFFFFFFF // S_CCA_TIME[31..0]
885+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
886+#define BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK 0xFFFFFFFF // BEACONTXCOUNT[31..0]
887+#define BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK 0xFFFFFFFF // TX_20MHZ_CNT[31..0]
888+#define BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK 0xFFFFFFFF // TX_40MHZ_CNT[31..0]
889+#define BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK 0xFFFFFFFF // TX_80MHZ_CNT[31..0]
890+#define BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK 0xFFFFFFFF // TX_160MHZ_CNT[31..0]
891+#define BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK 0xFFFFFFFF // TX_320MHZ_CNT[31..0]
892+#define BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK 0xFFFFFFFF // MUBF_TX_COUNT[31..0]
893+#define BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK 0xFFFFFFFF // VEC_MISS_COUNT[31..0]
894+#define BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK 0xFFFFFFFF // DELIMITER_FAIL_COUNT[31..0]
895+#define BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK 0xFFFFFFFF // RX_FCS_ERROR_COUNT[31..0]
896+#define BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK 0xFFFFFFFF // RX_FIFO_FULL_COUNT[31..0]
897+#define BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK 0xFFFFFFFF // RX_LEN_MISMATCH[31..0]
898+#define BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
899+#define BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK 0xFFFFFFFF // RTSTXCOUNTn[31..0]
900+#define BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK 0xFFFFFFFF // RTSRETRYCOUNTn[31..0]
901+#define BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK 0xFFFFFFFF // BAMISSCOUNTn[31..0]
902+#define BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK 0xFFFFFFFF // ACKFAILCOUNTn[31..0]
903+#define BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK 0xFFFFFFFF // FRAMERETRYCOUNTn[31..0]
904+#define BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK 0xFFFFFFFF // FRAMERETRY2COUNTn[31..0]
905+#define BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK 0xFFFFFFFF // FRAMERETRY3COUNTn[31..0]
906+#define BN0_WF_MIB_TOP_TRARC0_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B0) // D0B0
907+#define BN0_WF_MIB_TOP_TRARC1_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B4) // D0B4
908+#define BN0_WF_MIB_TOP_TRARC2_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B8) // D0B8
909+#define BN0_WF_MIB_TOP_TRARC3_ADDR (BN0_WF_MIB_TOP_BASE + 0x0BC) // D0BC
910+#define BN0_WF_MIB_TOP_TRARC4_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C0) // D0C0
911+#define BN0_WF_MIB_TOP_TRARC5_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C4) // D0C4
912+#define BN0_WF_MIB_TOP_TRARC6_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C8) // D0C8
913+#define BN0_WF_MIB_TOP_TRARC7_ADDR (BN0_WF_MIB_TOP_BASE + 0x0CC) // D0CC
914+
915+#define BN0_WF_MIB_TOP_TRDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x9B4) // D9B4
916+#define BN0_WF_MIB_TOP_TRDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x9B8) // D9B8
917+#define BN0_WF_MIB_TOP_TRDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9BC) // D9BC
918+#define BN0_WF_MIB_TOP_TRDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C0) // D9C0
919+#define BN0_WF_MIB_TOP_TRDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C4) // D9C4
920+#define BN0_WF_MIB_TOP_TRDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C8) // D9C8
921+#define BN0_WF_MIB_TOP_TRDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x9CC) // D9CC
922+#define BN0_WF_MIB_TOP_TRDR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D0) // D9D0
923+#define BN0_WF_MIB_TOP_TRDR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D4) // D9D4
924+#define BN0_WF_MIB_TOP_TRDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D8) // D9D8
925+#define BN0_WF_MIB_TOP_TRDR10_ADDR (BN0_WF_MIB_TOP_BASE + 0x9DC) // D9DC
926+#define BN0_WF_MIB_TOP_TRDR11_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E0) // D9E0
927+#define BN0_WF_MIB_TOP_TRDR12_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E4) // D9E4
928+#define BN0_WF_MIB_TOP_TRDR13_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E8) // D9E8
929+#define BN0_WF_MIB_TOP_TRDR14_ADDR (BN0_WF_MIB_TOP_BASE + 0x9EC) // D9EC
930+#define BN0_WF_MIB_TOP_TRDR15_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F0) // D9F0
931+
932+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
933+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK 0x03FF0000 // AGG_RANG_SEL_1[25..16]
934+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT 16
935+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
936+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK 0x000003FF // AGG_RANG_SEL_0[9..0]
937+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT 0
938+
939+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
940+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK 0x03FF0000 // AGG_RANG_SEL_3[25..16]
941+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT 16
942+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
943+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK 0x000003FF // AGG_RANG_SEL_2[9..0]
944+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT 0
945+
946+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
947+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK 0x03FF0000 // AGG_RANG_SEL_5[25..16]
948+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT 16
949+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
950+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK 0x000003FF // AGG_RANG_SEL_4[9..0]
951+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT 0
952+
953+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
954+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK 0x03FF0000 // AGG_RANG_SEL_7[25..16]
955+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT 16
956+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
957+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK 0x000003FF // AGG_RANG_SEL_6[9..0]
958+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT 0
959+
960+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
961+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK 0x03FF0000 // AGG_RANG_SEL_9[25..16]
962+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT 16
963+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
964+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK 0x000003FF // AGG_RANG_SEL_8[9..0]
965+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT 0
966+
967+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
968+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK 0x03FF0000 // AGG_RANG_SEL_11[25..16]
969+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT 16
970+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
971+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK 0x000003FF // AGG_RANG_SEL_10[9..0]
972+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT 0
973+
974+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
975+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK 0x03FF0000 // AGG_RANG_SEL_13[25..16]
976+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT 16
977+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
978+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK 0x000003FF // AGG_RANG_SEL_12[9..0]
979+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT 0
980+
981+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_ADDR BN0_WF_MIB_TOP_TRARC7_ADDR
982+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK 0x000003FF // AGG_RANG_SEL_14[9..0]
983+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT 0
984+
985+/* RRO TOP */
986+#define WF_RRO_TOP_BASE 0xA000 /*0x820C2000 */
987+#define WF_RRO_TOP_IND_CMD_0_CTRL0_ADDR (WF_RRO_TOP_BASE + 0x40) // 2040
988+ //
989+/* WTBL */
990+enum mt7996_wtbl_type {
991+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
992+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
993+ WTBL_TYPE_KEY, /* Key Table */
994+ MAX_NUM_WTBL_TYPE
995+};
996+
997+struct berse_wtbl_parse {
998+ u8 *name;
999+ u32 mask;
1000+ u32 shift;
1001+ u8 new_line;
1002+};
1003+
1004+enum muar_idx {
1005+ MUAR_INDEX_OWN_MAC_ADDR_0 = 0,
1006+ MUAR_INDEX_OWN_MAC_ADDR_1,
1007+ MUAR_INDEX_OWN_MAC_ADDR_2,
1008+ MUAR_INDEX_OWN_MAC_ADDR_3,
1009+ MUAR_INDEX_OWN_MAC_ADDR_4,
1010+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC = 0xE,
1011+ MUAR_INDEX_UNMATCHED = 0xF,
1012+ MUAR_INDEX_OWN_MAC_ADDR_11 = 0x11,
1013+ MUAR_INDEX_OWN_MAC_ADDR_12,
1014+ MUAR_INDEX_OWN_MAC_ADDR_13,
1015+ MUAR_INDEX_OWN_MAC_ADDR_14,
1016+ MUAR_INDEX_OWN_MAC_ADDR_15,
1017+ MUAR_INDEX_OWN_MAC_ADDR_16,
1018+ MUAR_INDEX_OWN_MAC_ADDR_17,
1019+ MUAR_INDEX_OWN_MAC_ADDR_18,
1020+ MUAR_INDEX_OWN_MAC_ADDR_19,
1021+ MUAR_INDEX_OWN_MAC_ADDR_1A,
1022+ MUAR_INDEX_OWN_MAC_ADDR_1B,
1023+ MUAR_INDEX_OWN_MAC_ADDR_1C,
1024+ MUAR_INDEX_OWN_MAC_ADDR_1D,
1025+ MUAR_INDEX_OWN_MAC_ADDR_1E,
1026+ MUAR_INDEX_OWN_MAC_ADDR_1F,
1027+ MUAR_INDEX_OWN_MAC_ADDR_20,
1028+ MUAR_INDEX_OWN_MAC_ADDR_21,
1029+ MUAR_INDEX_OWN_MAC_ADDR_22,
1030+ MUAR_INDEX_OWN_MAC_ADDR_23,
1031+ MUAR_INDEX_OWN_MAC_ADDR_24,
1032+ MUAR_INDEX_OWN_MAC_ADDR_25,
1033+ MUAR_INDEX_OWN_MAC_ADDR_26,
1034+ MUAR_INDEX_OWN_MAC_ADDR_27,
1035+ MUAR_INDEX_OWN_MAC_ADDR_28,
1036+ MUAR_INDEX_OWN_MAC_ADDR_29,
1037+ MUAR_INDEX_OWN_MAC_ADDR_2A,
1038+ MUAR_INDEX_OWN_MAC_ADDR_2B,
1039+ MUAR_INDEX_OWN_MAC_ADDR_2C,
1040+ MUAR_INDEX_OWN_MAC_ADDR_2D,
1041+ MUAR_INDEX_OWN_MAC_ADDR_2E,
1042+ MUAR_INDEX_OWN_MAC_ADDR_2F
1043+};
1044+
1045+enum cipher_suit {
1046+ IGTK_CIPHER_SUIT_NONE = 0,
1047+ IGTK_CIPHER_SUIT_BIP,
1048+ IGTK_CIPHER_SUIT_BIP_256
1049+};
1050+
1051+#define LWTBL_LEN_IN_DW 36
1052+#define UWTBL_LEN_IN_DW 10
1053+
1054+#define MT_DBG_WTBL_BASE 0x820D8000
1055+
1056+#define MT_DBG_WTBLON_TOP_BASE 0x820d4000
1057+#define MT_DBG_WTBLON_TOP_WDUCR_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x0370) // 4370
1058+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
1059+
1060+#define MT_DBG_UWTBL_TOP_BASE 0x820c4000
1061+#define MT_DBG_UWTBL_TOP_WDUCR_ADDR (MT_DBG_UWTBL_TOP_BASE + 0x0104) // 4104
1062+#define MT_DBG_UWTBL_TOP_WDUCR_GROUP GENMASK(5, 0)
1063+#define MT_DBG_UWTBL_TOP_WDUCR_TARGET BIT(31)
1064+
1065+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1066+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1067+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1068+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1069+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1070+
1071+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1072+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1073+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1074+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1075+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1076+
1077+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1078+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1079+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1080+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1081+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1082+
1083+// UMAC WTBL
1084+// DW0
1085+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__DW 0
1086+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__ADDR 0
1087+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__MASK 0x0000ffff // 15- 0
1088+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__SHIFT 0
1089+#define WF_UWTBL_OWN_MLD_ID_DW 0
1090+#define WF_UWTBL_OWN_MLD_ID_ADDR 0
1091+#define WF_UWTBL_OWN_MLD_ID_MASK 0x003f0000 // 21-16
1092+#define WF_UWTBL_OWN_MLD_ID_SHIFT 16
1093+// DW1
1094+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__DW 1
1095+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__ADDR 4
1096+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__MASK 0xffffffff // 31- 0
1097+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__SHIFT 0
1098+// DW2
1099+#define WF_UWTBL_PN_31_0__DW 2
1100+#define WF_UWTBL_PN_31_0__ADDR 8
1101+#define WF_UWTBL_PN_31_0__MASK 0xffffffff // 31- 0
1102+#define WF_UWTBL_PN_31_0__SHIFT 0
1103+// DW3
1104+#define WF_UWTBL_PN_47_32__DW 3
1105+#define WF_UWTBL_PN_47_32__ADDR 12
1106+#define WF_UWTBL_PN_47_32__MASK 0x0000ffff // 15- 0
1107+#define WF_UWTBL_PN_47_32__SHIFT 0
1108+#define WF_UWTBL_COM_SN_DW 3
1109+#define WF_UWTBL_COM_SN_ADDR 12
1110+#define WF_UWTBL_COM_SN_MASK 0x0fff0000 // 27-16
1111+#define WF_UWTBL_COM_SN_SHIFT 16
1112+// DW4
1113+#define WF_UWTBL_TID0_SN_DW 4
1114+#define WF_UWTBL_TID0_SN_ADDR 16
1115+#define WF_UWTBL_TID0_SN_MASK 0x00000fff // 11- 0
1116+#define WF_UWTBL_TID0_SN_SHIFT 0
1117+#define WF_UWTBL_RX_BIPN_31_0__DW 4
1118+#define WF_UWTBL_RX_BIPN_31_0__ADDR 16
1119+#define WF_UWTBL_RX_BIPN_31_0__MASK 0xffffffff // 31- 0
1120+#define WF_UWTBL_RX_BIPN_31_0__SHIFT 0
1121+#define WF_UWTBL_TID1_SN_DW 4
1122+#define WF_UWTBL_TID1_SN_ADDR 16
1123+#define WF_UWTBL_TID1_SN_MASK 0x00fff000 // 23-12
1124+#define WF_UWTBL_TID1_SN_SHIFT 12
1125+#define WF_UWTBL_TID2_SN_7_0__DW 4
1126+#define WF_UWTBL_TID2_SN_7_0__ADDR 16
1127+#define WF_UWTBL_TID2_SN_7_0__MASK 0xff000000 // 31-24
1128+#define WF_UWTBL_TID2_SN_7_0__SHIFT 24
1129+// DW5
1130+#define WF_UWTBL_TID2_SN_11_8__DW 5
1131+#define WF_UWTBL_TID2_SN_11_8__ADDR 20
1132+#define WF_UWTBL_TID2_SN_11_8__MASK 0x0000000f // 3- 0
1133+#define WF_UWTBL_TID2_SN_11_8__SHIFT 0
1134+#define WF_UWTBL_RX_BIPN_47_32__DW 5
1135+#define WF_UWTBL_RX_BIPN_47_32__ADDR 20
1136+#define WF_UWTBL_RX_BIPN_47_32__MASK 0x0000ffff // 15- 0
1137+#define WF_UWTBL_RX_BIPN_47_32__SHIFT 0
1138+#define WF_UWTBL_TID3_SN_DW 5
1139+#define WF_UWTBL_TID3_SN_ADDR 20
1140+#define WF_UWTBL_TID3_SN_MASK 0x0000fff0 // 15- 4
1141+#define WF_UWTBL_TID3_SN_SHIFT 4
1142+#define WF_UWTBL_TID4_SN_DW 5
1143+#define WF_UWTBL_TID4_SN_ADDR 20
1144+#define WF_UWTBL_TID4_SN_MASK 0x0fff0000 // 27-16
1145+#define WF_UWTBL_TID4_SN_SHIFT 16
1146+#define WF_UWTBL_TID5_SN_3_0__DW 5
1147+#define WF_UWTBL_TID5_SN_3_0__ADDR 20
1148+#define WF_UWTBL_TID5_SN_3_0__MASK 0xf0000000 // 31-28
1149+#define WF_UWTBL_TID5_SN_3_0__SHIFT 28
1150+// DW6
1151+#define WF_UWTBL_TID5_SN_11_4__DW 6
1152+#define WF_UWTBL_TID5_SN_11_4__ADDR 24
1153+#define WF_UWTBL_TID5_SN_11_4__MASK 0x000000ff // 7- 0
1154+#define WF_UWTBL_TID5_SN_11_4__SHIFT 0
1155+#define WF_UWTBL_KEY_LOC2_DW 6
1156+#define WF_UWTBL_KEY_LOC2_ADDR 24
1157+#define WF_UWTBL_KEY_LOC2_MASK 0x00001fff // 12- 0
1158+#define WF_UWTBL_KEY_LOC2_SHIFT 0
1159+#define WF_UWTBL_TID6_SN_DW 6
1160+#define WF_UWTBL_TID6_SN_ADDR 24
1161+#define WF_UWTBL_TID6_SN_MASK 0x000fff00 // 19- 8
1162+#define WF_UWTBL_TID6_SN_SHIFT 8
1163+#define WF_UWTBL_TID7_SN_DW 6
1164+#define WF_UWTBL_TID7_SN_ADDR 24
1165+#define WF_UWTBL_TID7_SN_MASK 0xfff00000 // 31-20
1166+#define WF_UWTBL_TID7_SN_SHIFT 20
1167+// DW7
1168+#define WF_UWTBL_KEY_LOC0_DW 7
1169+#define WF_UWTBL_KEY_LOC0_ADDR 28
1170+#define WF_UWTBL_KEY_LOC0_MASK 0x00001fff // 12- 0
1171+#define WF_UWTBL_KEY_LOC0_SHIFT 0
1172+#define WF_UWTBL_KEY_LOC1_DW 7
1173+#define WF_UWTBL_KEY_LOC1_ADDR 28
1174+#define WF_UWTBL_KEY_LOC1_MASK 0x1fff0000 // 28-16
1175+#define WF_UWTBL_KEY_LOC1_SHIFT 16
1176+// DW8
1177+#define WF_UWTBL_AMSDU_CFG_DW 8
1178+#define WF_UWTBL_AMSDU_CFG_ADDR 32
1179+#define WF_UWTBL_AMSDU_CFG_MASK 0x00000fff // 11- 0
1180+#define WF_UWTBL_AMSDU_CFG_SHIFT 0
1181+#define WF_UWTBL_WMM_Q_DW 8
1182+#define WF_UWTBL_WMM_Q_ADDR 32
1183+#define WF_UWTBL_WMM_Q_MASK 0x06000000 // 26-25
1184+#define WF_UWTBL_WMM_Q_SHIFT 25
1185+#define WF_UWTBL_QOS_DW 8
1186+#define WF_UWTBL_QOS_ADDR 32
1187+#define WF_UWTBL_QOS_MASK 0x08000000 // 27-27
1188+#define WF_UWTBL_QOS_SHIFT 27
1189+#define WF_UWTBL_HT_DW 8
1190+#define WF_UWTBL_HT_ADDR 32
1191+#define WF_UWTBL_HT_MASK 0x10000000 // 28-28
1192+#define WF_UWTBL_HT_SHIFT 28
1193+#define WF_UWTBL_HDRT_MODE_DW 8
1194+#define WF_UWTBL_HDRT_MODE_ADDR 32
1195+#define WF_UWTBL_HDRT_MODE_MASK 0x20000000 // 29-29
1196+#define WF_UWTBL_HDRT_MODE_SHIFT 29
1197+// DW9
1198+#define WF_UWTBL_RELATED_IDX0_DW 9
1199+#define WF_UWTBL_RELATED_IDX0_ADDR 36
1200+#define WF_UWTBL_RELATED_IDX0_MASK 0x00000fff // 11- 0
1201+#define WF_UWTBL_RELATED_IDX0_SHIFT 0
1202+#define WF_UWTBL_RELATED_BAND0_DW 9
1203+#define WF_UWTBL_RELATED_BAND0_ADDR 36
1204+#define WF_UWTBL_RELATED_BAND0_MASK 0x00003000 // 13-12
1205+#define WF_UWTBL_RELATED_BAND0_SHIFT 12
1206+#define WF_UWTBL_PRIMARY_MLD_BAND_DW 9
1207+#define WF_UWTBL_PRIMARY_MLD_BAND_ADDR 36
1208+#define WF_UWTBL_PRIMARY_MLD_BAND_MASK 0x0000c000 // 15-14
1209+#define WF_UWTBL_PRIMARY_MLD_BAND_SHIFT 14
1210+#define WF_UWTBL_RELATED_IDX1_DW 9
1211+#define WF_UWTBL_RELATED_IDX1_ADDR 36
1212+#define WF_UWTBL_RELATED_IDX1_MASK 0x0fff0000 // 27-16
1213+#define WF_UWTBL_RELATED_IDX1_SHIFT 16
1214+#define WF_UWTBL_RELATED_BAND1_DW 9
1215+#define WF_UWTBL_RELATED_BAND1_ADDR 36
1216+#define WF_UWTBL_RELATED_BAND1_MASK 0x30000000 // 29-28
1217+#define WF_UWTBL_RELATED_BAND1_SHIFT 28
1218+#define WF_UWTBL_SECONDARY_MLD_BAND_DW 9
1219+#define WF_UWTBL_SECONDARY_MLD_BAND_ADDR 36
1220+#define WF_UWTBL_SECONDARY_MLD_BAND_MASK 0xc0000000 // 31-30
1221+#define WF_UWTBL_SECONDARY_MLD_BAND_SHIFT 30
1222+
1223+/* LMAC WTBL */
1224+// DW0
1225+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__DW 0
1226+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__ADDR 0
1227+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__MASK \
1228+ 0x0000ffff // 15- 0
1229+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__SHIFT 0
1230+#define WF_LWTBL_MUAR_DW 0
1231+#define WF_LWTBL_MUAR_ADDR 0
1232+#define WF_LWTBL_MUAR_MASK \
1233+ 0x003f0000 // 21-16
1234+#define WF_LWTBL_MUAR_SHIFT 16
1235+#define WF_LWTBL_RCA1_DW 0
1236+#define WF_LWTBL_RCA1_ADDR 0
1237+#define WF_LWTBL_RCA1_MASK \
1238+ 0x00400000 // 22-22
1239+#define WF_LWTBL_RCA1_SHIFT 22
1240+#define WF_LWTBL_KID_DW 0
1241+#define WF_LWTBL_KID_ADDR 0
1242+#define WF_LWTBL_KID_MASK \
1243+ 0x01800000 // 24-23
1244+#define WF_LWTBL_KID_SHIFT 23
1245+#define WF_LWTBL_RCID_DW 0
1246+#define WF_LWTBL_RCID_ADDR 0
1247+#define WF_LWTBL_RCID_MASK \
1248+ 0x02000000 // 25-25
1249+#define WF_LWTBL_RCID_SHIFT 25
1250+#define WF_LWTBL_BAND_DW 0
1251+#define WF_LWTBL_BAND_ADDR 0
1252+#define WF_LWTBL_BAND_MASK \
1253+ 0x0c000000 // 27-26
1254+#define WF_LWTBL_BAND_SHIFT 26
1255+#define WF_LWTBL_RV_DW 0
1256+#define WF_LWTBL_RV_ADDR 0
1257+#define WF_LWTBL_RV_MASK \
1258+ 0x10000000 // 28-28
1259+#define WF_LWTBL_RV_SHIFT 28
1260+#define WF_LWTBL_RCA2_DW 0
1261+#define WF_LWTBL_RCA2_ADDR 0
1262+#define WF_LWTBL_RCA2_MASK \
1263+ 0x20000000 // 29-29
1264+#define WF_LWTBL_RCA2_SHIFT 29
1265+#define WF_LWTBL_WPI_FLAG_DW 0
1266+#define WF_LWTBL_WPI_FLAG_ADDR 0
1267+#define WF_LWTBL_WPI_FLAG_MASK \
1268+ 0x40000000 // 30-30
1269+#define WF_LWTBL_WPI_FLAG_SHIFT 30
1270+// DW1
1271+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__DW 1
1272+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__ADDR 4
1273+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__MASK \
1274+ 0xffffffff // 31- 0
1275+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__SHIFT 0
1276+// DW2
1277+#define WF_LWTBL_AID_DW 2
1278+#define WF_LWTBL_AID_ADDR 8
1279+#define WF_LWTBL_AID_MASK \
1280+ 0x00000fff // 11- 0
1281+#define WF_LWTBL_AID_SHIFT 0
1282+#define WF_LWTBL_GID_SU_DW 2
1283+#define WF_LWTBL_GID_SU_ADDR 8
1284+#define WF_LWTBL_GID_SU_MASK \
1285+ 0x00001000 // 12-12
1286+#define WF_LWTBL_GID_SU_SHIFT 12
1287+#define WF_LWTBL_SPP_EN_DW 2
1288+#define WF_LWTBL_SPP_EN_ADDR 8
1289+#define WF_LWTBL_SPP_EN_MASK \
1290+ 0x00002000 // 13-13
1291+#define WF_LWTBL_SPP_EN_SHIFT 13
1292+#define WF_LWTBL_WPI_EVEN_DW 2
1293+#define WF_LWTBL_WPI_EVEN_ADDR 8
1294+#define WF_LWTBL_WPI_EVEN_MASK \
1295+ 0x00004000 // 14-14
1296+#define WF_LWTBL_WPI_EVEN_SHIFT 14
1297+#define WF_LWTBL_AAD_OM_DW 2
1298+#define WF_LWTBL_AAD_OM_ADDR 8
1299+#define WF_LWTBL_AAD_OM_MASK \
1300+ 0x00008000 // 15-15
1301+#define WF_LWTBL_AAD_OM_SHIFT 15
1302+#define WF_LWTBL_CIPHER_SUIT_PGTK_DW 2
1303+#define WF_LWTBL_CIPHER_SUIT_PGTK_ADDR 8
1304+#define WF_LWTBL_CIPHER_SUIT_PGTK_MASK \
1305+ 0x001f0000 // 20-16
1306+#define WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT 16
1307+#define WF_LWTBL_FD_DW 2
1308+#define WF_LWTBL_FD_ADDR 8
1309+#define WF_LWTBL_FD_MASK \
1310+ 0x00200000 // 21-21
1311+#define WF_LWTBL_FD_SHIFT 21
1312+#define WF_LWTBL_TD_DW 2
1313+#define WF_LWTBL_TD_ADDR 8
1314+#define WF_LWTBL_TD_MASK \
1315+ 0x00400000 // 22-22
1316+#define WF_LWTBL_TD_SHIFT 22
1317+#define WF_LWTBL_SW_DW 2
1318+#define WF_LWTBL_SW_ADDR 8
1319+#define WF_LWTBL_SW_MASK \
1320+ 0x00800000 // 23-23
1321+#define WF_LWTBL_SW_SHIFT 23
1322+#define WF_LWTBL_UL_DW 2
1323+#define WF_LWTBL_UL_ADDR 8
1324+#define WF_LWTBL_UL_MASK \
1325+ 0x01000000 // 24-24
1326+#define WF_LWTBL_UL_SHIFT 24
1327+#define WF_LWTBL_TX_PS_DW 2
1328+#define WF_LWTBL_TX_PS_ADDR 8
1329+#define WF_LWTBL_TX_PS_MASK \
1330+ 0x02000000 // 25-25
1331+#define WF_LWTBL_TX_PS_SHIFT 25
1332+#define WF_LWTBL_QOS_DW 2
1333+#define WF_LWTBL_QOS_ADDR 8
1334+#define WF_LWTBL_QOS_MASK \
1335+ 0x04000000 // 26-26
1336+#define WF_LWTBL_QOS_SHIFT 26
1337+#define WF_LWTBL_HT_DW 2
1338+#define WF_LWTBL_HT_ADDR 8
1339+#define WF_LWTBL_HT_MASK \
1340+ 0x08000000 // 27-27
1341+#define WF_LWTBL_HT_SHIFT 27
1342+#define WF_LWTBL_VHT_DW 2
1343+#define WF_LWTBL_VHT_ADDR 8
1344+#define WF_LWTBL_VHT_MASK \
1345+ 0x10000000 // 28-28
1346+#define WF_LWTBL_VHT_SHIFT 28
1347+#define WF_LWTBL_HE_DW 2
1348+#define WF_LWTBL_HE_ADDR 8
1349+#define WF_LWTBL_HE_MASK \
1350+ 0x20000000 // 29-29
1351+#define WF_LWTBL_HE_SHIFT 29
1352+#define WF_LWTBL_EHT_DW 2
1353+#define WF_LWTBL_EHT_ADDR 8
1354+#define WF_LWTBL_EHT_MASK \
1355+ 0x40000000 // 30-30
1356+#define WF_LWTBL_EHT_SHIFT 30
1357+#define WF_LWTBL_MESH_DW 2
1358+#define WF_LWTBL_MESH_ADDR 8
1359+#define WF_LWTBL_MESH_MASK \
1360+ 0x80000000 // 31-31
1361+#define WF_LWTBL_MESH_SHIFT 31
1362+// DW3
1363+#define WF_LWTBL_WMM_Q_DW 3
1364+#define WF_LWTBL_WMM_Q_ADDR 12
1365+#define WF_LWTBL_WMM_Q_MASK \
1366+ 0x00000003 // 1- 0
1367+#define WF_LWTBL_WMM_Q_SHIFT 0
1368+#define WF_LWTBL_EHT_SIG_MCS_DW 3
1369+#define WF_LWTBL_EHT_SIG_MCS_ADDR 12
1370+#define WF_LWTBL_EHT_SIG_MCS_MASK \
1371+ 0x0000000c // 3- 2
1372+#define WF_LWTBL_EHT_SIG_MCS_SHIFT 2
1373+#define WF_LWTBL_HDRT_MODE_DW 3
1374+#define WF_LWTBL_HDRT_MODE_ADDR 12
1375+#define WF_LWTBL_HDRT_MODE_MASK \
1376+ 0x00000010 // 4- 4
1377+#define WF_LWTBL_HDRT_MODE_SHIFT 4
1378+#define WF_LWTBL_BEAM_CHG_DW 3
1379+#define WF_LWTBL_BEAM_CHG_ADDR 12
1380+#define WF_LWTBL_BEAM_CHG_MASK \
1381+ 0x00000020 // 5- 5
1382+#define WF_LWTBL_BEAM_CHG_SHIFT 5
1383+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_DW 3
1384+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_ADDR 12
1385+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK \
1386+ 0x000000c0 // 7- 6
1387+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT 6
1388+#define WF_LWTBL_PFMU_IDX_DW 3
1389+#define WF_LWTBL_PFMU_IDX_ADDR 12
1390+#define WF_LWTBL_PFMU_IDX_MASK \
1391+ 0x0000ff00 // 15- 8
1392+#define WF_LWTBL_PFMU_IDX_SHIFT 8
1393+#define WF_LWTBL_ULPF_IDX_DW 3
1394+#define WF_LWTBL_ULPF_IDX_ADDR 12
1395+#define WF_LWTBL_ULPF_IDX_MASK \
1396+ 0x00ff0000 // 23-16
1397+#define WF_LWTBL_ULPF_IDX_SHIFT 16
1398+#define WF_LWTBL_RIBF_DW 3
1399+#define WF_LWTBL_RIBF_ADDR 12
1400+#define WF_LWTBL_RIBF_MASK \
1401+ 0x01000000 // 24-24
1402+#define WF_LWTBL_RIBF_SHIFT 24
1403+#define WF_LWTBL_ULPF_DW 3
1404+#define WF_LWTBL_ULPF_ADDR 12
1405+#define WF_LWTBL_ULPF_MASK \
1406+ 0x02000000 // 25-25
1407+#define WF_LWTBL_ULPF_SHIFT 25
1408+#define WF_LWTBL_TBF_HT_DW 3
1409+#define WF_LWTBL_TBF_HT_ADDR 12
1410+#define WF_LWTBL_TBF_HT_MASK \
1411+ 0x08000000 // 27-27
1412+#define WF_LWTBL_TBF_HT_SHIFT 27
1413+#define WF_LWTBL_TBF_VHT_DW 3
1414+#define WF_LWTBL_TBF_VHT_ADDR 12
1415+#define WF_LWTBL_TBF_VHT_MASK \
1416+ 0x10000000 // 28-28
1417+#define WF_LWTBL_TBF_VHT_SHIFT 28
1418+#define WF_LWTBL_TBF_HE_DW 3
1419+#define WF_LWTBL_TBF_HE_ADDR 12
1420+#define WF_LWTBL_TBF_HE_MASK \
1421+ 0x20000000 // 29-29
1422+#define WF_LWTBL_TBF_HE_SHIFT 29
1423+#define WF_LWTBL_TBF_EHT_DW 3
1424+#define WF_LWTBL_TBF_EHT_ADDR 12
1425+#define WF_LWTBL_TBF_EHT_MASK \
1426+ 0x40000000 // 30-30
1427+#define WF_LWTBL_TBF_EHT_SHIFT 30
1428+#define WF_LWTBL_IGN_FBK_DW 3
1429+#define WF_LWTBL_IGN_FBK_ADDR 12
1430+#define WF_LWTBL_IGN_FBK_MASK \
1431+ 0x80000000 // 31-31
1432+#define WF_LWTBL_IGN_FBK_SHIFT 31
1433+// DW4
1434+#define WF_LWTBL_ANT_ID0_DW 4
1435+#define WF_LWTBL_ANT_ID0_ADDR 16
1436+#define WF_LWTBL_ANT_ID0_MASK \
1437+ 0x00000007 // 2- 0
1438+#define WF_LWTBL_ANT_ID0_SHIFT 0
1439+#define WF_LWTBL_ANT_ID1_DW 4
1440+#define WF_LWTBL_ANT_ID1_ADDR 16
1441+#define WF_LWTBL_ANT_ID1_MASK \
1442+ 0x00000038 // 5- 3
1443+#define WF_LWTBL_ANT_ID1_SHIFT 3
1444+#define WF_LWTBL_ANT_ID2_DW 4
1445+#define WF_LWTBL_ANT_ID2_ADDR 16
1446+#define WF_LWTBL_ANT_ID2_MASK \
1447+ 0x000001c0 // 8- 6
1448+#define WF_LWTBL_ANT_ID2_SHIFT 6
1449+#define WF_LWTBL_ANT_ID3_DW 4
1450+#define WF_LWTBL_ANT_ID3_ADDR 16
1451+#define WF_LWTBL_ANT_ID3_MASK \
1452+ 0x00000e00 // 11- 9
1453+#define WF_LWTBL_ANT_ID3_SHIFT 9
1454+#define WF_LWTBL_ANT_ID4_DW 4
1455+#define WF_LWTBL_ANT_ID4_ADDR 16
1456+#define WF_LWTBL_ANT_ID4_MASK \
1457+ 0x00007000 // 14-12
1458+#define WF_LWTBL_ANT_ID4_SHIFT 12
1459+#define WF_LWTBL_ANT_ID5_DW 4
1460+#define WF_LWTBL_ANT_ID5_ADDR 16
1461+#define WF_LWTBL_ANT_ID5_MASK \
1462+ 0x00038000 // 17-15
1463+#define WF_LWTBL_ANT_ID5_SHIFT 15
1464+#define WF_LWTBL_ANT_ID6_DW 4
1465+#define WF_LWTBL_ANT_ID6_ADDR 16
1466+#define WF_LWTBL_ANT_ID6_MASK \
1467+ 0x001c0000 // 20-18
1468+#define WF_LWTBL_ANT_ID6_SHIFT 18
1469+#define WF_LWTBL_ANT_ID7_DW 4
1470+#define WF_LWTBL_ANT_ID7_ADDR 16
1471+#define WF_LWTBL_ANT_ID7_MASK \
1472+ 0x00e00000 // 23-21
1473+#define WF_LWTBL_ANT_ID7_SHIFT 21
1474+#define WF_LWTBL_PE_DW 4
1475+#define WF_LWTBL_PE_ADDR 16
1476+#define WF_LWTBL_PE_MASK \
1477+ 0x03000000 // 25-24
1478+#define WF_LWTBL_PE_SHIFT 24
1479+#define WF_LWTBL_DIS_RHTR_DW 4
1480+#define WF_LWTBL_DIS_RHTR_ADDR 16
1481+#define WF_LWTBL_DIS_RHTR_MASK \
1482+ 0x04000000 // 26-26
1483+#define WF_LWTBL_DIS_RHTR_SHIFT 26
1484+#define WF_LWTBL_LDPC_HT_DW 4
1485+#define WF_LWTBL_LDPC_HT_ADDR 16
1486+#define WF_LWTBL_LDPC_HT_MASK \
1487+ 0x08000000 // 27-27
1488+#define WF_LWTBL_LDPC_HT_SHIFT 27
1489+#define WF_LWTBL_LDPC_VHT_DW 4
1490+#define WF_LWTBL_LDPC_VHT_ADDR 16
1491+#define WF_LWTBL_LDPC_VHT_MASK \
1492+ 0x10000000 // 28-28
1493+#define WF_LWTBL_LDPC_VHT_SHIFT 28
1494+#define WF_LWTBL_LDPC_HE_DW 4
1495+#define WF_LWTBL_LDPC_HE_ADDR 16
1496+#define WF_LWTBL_LDPC_HE_MASK \
1497+ 0x20000000 // 29-29
1498+#define WF_LWTBL_LDPC_HE_SHIFT 29
1499+#define WF_LWTBL_LDPC_EHT_DW 4
1500+#define WF_LWTBL_LDPC_EHT_ADDR 16
1501+#define WF_LWTBL_LDPC_EHT_MASK \
1502+ 0x40000000 // 30-30
1503+#define WF_LWTBL_LDPC_EHT_SHIFT 30
1504+// DW5
1505+#define WF_LWTBL_AF_DW 5
1506+#define WF_LWTBL_AF_ADDR 20
1507+#define WF_LWTBL_AF_MASK \
1508+ 0x00000007 // 2- 0
1509+#define WF_LWTBL_AF_SHIFT 0
1510+#define WF_LWTBL_AF_HE_DW 5
1511+#define WF_LWTBL_AF_HE_ADDR 20
1512+#define WF_LWTBL_AF_HE_MASK \
1513+ 0x00000018 // 4- 3
1514+#define WF_LWTBL_AF_HE_SHIFT 3
1515+#define WF_LWTBL_RTS_DW 5
1516+#define WF_LWTBL_RTS_ADDR 20
1517+#define WF_LWTBL_RTS_MASK \
1518+ 0x00000020 // 5- 5
1519+#define WF_LWTBL_RTS_SHIFT 5
1520+#define WF_LWTBL_SMPS_DW 5
1521+#define WF_LWTBL_SMPS_ADDR 20
1522+#define WF_LWTBL_SMPS_MASK \
1523+ 0x00000040 // 6- 6
1524+#define WF_LWTBL_SMPS_SHIFT 6
1525+#define WF_LWTBL_DYN_BW_DW 5
1526+#define WF_LWTBL_DYN_BW_ADDR 20
1527+#define WF_LWTBL_DYN_BW_MASK \
1528+ 0x00000080 // 7- 7
1529+#define WF_LWTBL_DYN_BW_SHIFT 7
1530+#define WF_LWTBL_MMSS_DW 5
1531+#define WF_LWTBL_MMSS_ADDR 20
1532+#define WF_LWTBL_MMSS_MASK \
1533+ 0x00000700 // 10- 8
1534+#define WF_LWTBL_MMSS_SHIFT 8
1535+#define WF_LWTBL_USR_DW 5
1536+#define WF_LWTBL_USR_ADDR 20
1537+#define WF_LWTBL_USR_MASK \
1538+ 0x00000800 // 11-11
1539+#define WF_LWTBL_USR_SHIFT 11
1540+#define WF_LWTBL_SR_R_DW 5
1541+#define WF_LWTBL_SR_R_ADDR 20
1542+#define WF_LWTBL_SR_R_MASK \
1543+ 0x00007000 // 14-12
1544+#define WF_LWTBL_SR_R_SHIFT 12
1545+#define WF_LWTBL_SR_ABORT_DW 5
1546+#define WF_LWTBL_SR_ABORT_ADDR 20
1547+#define WF_LWTBL_SR_ABORT_MASK \
1548+ 0x00008000 // 15-15
1549+#define WF_LWTBL_SR_ABORT_SHIFT 15
1550+#define WF_LWTBL_TX_POWER_OFFSET_DW 5
1551+#define WF_LWTBL_TX_POWER_OFFSET_ADDR 20
1552+#define WF_LWTBL_TX_POWER_OFFSET_MASK \
1553+ 0x003f0000 // 21-16
1554+#define WF_LWTBL_TX_POWER_OFFSET_SHIFT 16
1555+#define WF_LWTBL_LTF_EHT_DW 5
1556+#define WF_LWTBL_LTF_EHT_ADDR 20
1557+#define WF_LWTBL_LTF_EHT_MASK \
1558+ 0x00c00000 // 23-22
1559+#define WF_LWTBL_LTF_EHT_SHIFT 22
1560+#define WF_LWTBL_GI_EHT_DW 5
1561+#define WF_LWTBL_GI_EHT_ADDR 20
1562+#define WF_LWTBL_GI_EHT_MASK \
1563+ 0x03000000 // 25-24
1564+#define WF_LWTBL_GI_EHT_SHIFT 24
1565+#define WF_LWTBL_DOPPL_DW 5
1566+#define WF_LWTBL_DOPPL_ADDR 20
1567+#define WF_LWTBL_DOPPL_MASK \
1568+ 0x04000000 // 26-26
1569+#define WF_LWTBL_DOPPL_SHIFT 26
1570+#define WF_LWTBL_TXOP_PS_CAP_DW 5
1571+#define WF_LWTBL_TXOP_PS_CAP_ADDR 20
1572+#define WF_LWTBL_TXOP_PS_CAP_MASK \
1573+ 0x08000000 // 27-27
1574+#define WF_LWTBL_TXOP_PS_CAP_SHIFT 27
1575+#define WF_LWTBL_DU_I_PSM_DW 5
1576+#define WF_LWTBL_DU_I_PSM_ADDR 20
1577+#define WF_LWTBL_DU_I_PSM_MASK \
1578+ 0x10000000 // 28-28
1579+#define WF_LWTBL_DU_I_PSM_SHIFT 28
1580+#define WF_LWTBL_I_PSM_DW 5
1581+#define WF_LWTBL_I_PSM_ADDR 20
1582+#define WF_LWTBL_I_PSM_MASK \
1583+ 0x20000000 // 29-29
1584+#define WF_LWTBL_I_PSM_SHIFT 29
1585+#define WF_LWTBL_PSM_DW 5
1586+#define WF_LWTBL_PSM_ADDR 20
1587+#define WF_LWTBL_PSM_MASK \
1588+ 0x40000000 // 30-30
1589+#define WF_LWTBL_PSM_SHIFT 30
1590+#define WF_LWTBL_SKIP_TX_DW 5
1591+#define WF_LWTBL_SKIP_TX_ADDR 20
1592+#define WF_LWTBL_SKIP_TX_MASK \
1593+ 0x80000000 // 31-31
1594+#define WF_LWTBL_SKIP_TX_SHIFT 31
1595+// DW6
1596+#define WF_LWTBL_CBRN_DW 6
1597+#define WF_LWTBL_CBRN_ADDR 24
1598+#define WF_LWTBL_CBRN_MASK \
1599+ 0x00000007 // 2- 0
1600+#define WF_LWTBL_CBRN_SHIFT 0
1601+#define WF_LWTBL_DBNSS_EN_DW 6
1602+#define WF_LWTBL_DBNSS_EN_ADDR 24
1603+#define WF_LWTBL_DBNSS_EN_MASK \
1604+ 0x00000008 // 3- 3
1605+#define WF_LWTBL_DBNSS_EN_SHIFT 3
1606+#define WF_LWTBL_BAF_EN_DW 6
1607+#define WF_LWTBL_BAF_EN_ADDR 24
1608+#define WF_LWTBL_BAF_EN_MASK \
1609+ 0x00000010 // 4- 4
1610+#define WF_LWTBL_BAF_EN_SHIFT 4
1611+#define WF_LWTBL_RDGBA_DW 6
1612+#define WF_LWTBL_RDGBA_ADDR 24
1613+#define WF_LWTBL_RDGBA_MASK \
1614+ 0x00000020 // 5- 5
1615+#define WF_LWTBL_RDGBA_SHIFT 5
1616+#define WF_LWTBL_R_DW 6
1617+#define WF_LWTBL_R_ADDR 24
1618+#define WF_LWTBL_R_MASK \
1619+ 0x00000040 // 6- 6
1620+#define WF_LWTBL_R_SHIFT 6
1621+#define WF_LWTBL_SPE_IDX_DW 6
1622+#define WF_LWTBL_SPE_IDX_ADDR 24
1623+#define WF_LWTBL_SPE_IDX_MASK \
1624+ 0x00000f80 // 11- 7
1625+#define WF_LWTBL_SPE_IDX_SHIFT 7
1626+#define WF_LWTBL_G2_DW 6
1627+#define WF_LWTBL_G2_ADDR 24
1628+#define WF_LWTBL_G2_MASK \
1629+ 0x00001000 // 12-12
1630+#define WF_LWTBL_G2_SHIFT 12
1631+#define WF_LWTBL_G4_DW 6
1632+#define WF_LWTBL_G4_ADDR 24
1633+#define WF_LWTBL_G4_MASK \
1634+ 0x00002000 // 13-13
1635+#define WF_LWTBL_G4_SHIFT 13
1636+#define WF_LWTBL_G8_DW 6
1637+#define WF_LWTBL_G8_ADDR 24
1638+#define WF_LWTBL_G8_MASK \
1639+ 0x00004000 // 14-14
1640+#define WF_LWTBL_G8_SHIFT 14
1641+#define WF_LWTBL_G16_DW 6
1642+#define WF_LWTBL_G16_ADDR 24
1643+#define WF_LWTBL_G16_MASK \
1644+ 0x00008000 // 15-15
1645+#define WF_LWTBL_G16_SHIFT 15
1646+#define WF_LWTBL_G2_LTF_DW 6
1647+#define WF_LWTBL_G2_LTF_ADDR 24
1648+#define WF_LWTBL_G2_LTF_MASK \
1649+ 0x00030000 // 17-16
1650+#define WF_LWTBL_G2_LTF_SHIFT 16
1651+#define WF_LWTBL_G4_LTF_DW 6
1652+#define WF_LWTBL_G4_LTF_ADDR 24
1653+#define WF_LWTBL_G4_LTF_MASK \
1654+ 0x000c0000 // 19-18
1655+#define WF_LWTBL_G4_LTF_SHIFT 18
1656+#define WF_LWTBL_G8_LTF_DW 6
1657+#define WF_LWTBL_G8_LTF_ADDR 24
1658+#define WF_LWTBL_G8_LTF_MASK \
1659+ 0x00300000 // 21-20
1660+#define WF_LWTBL_G8_LTF_SHIFT 20
1661+#define WF_LWTBL_G16_LTF_DW 6
1662+#define WF_LWTBL_G16_LTF_ADDR 24
1663+#define WF_LWTBL_G16_LTF_MASK \
1664+ 0x00c00000 // 23-22
1665+#define WF_LWTBL_G16_LTF_SHIFT 22
1666+#define WF_LWTBL_G2_HE_DW 6
1667+#define WF_LWTBL_G2_HE_ADDR 24
1668+#define WF_LWTBL_G2_HE_MASK \
1669+ 0x03000000 // 25-24
1670+#define WF_LWTBL_G2_HE_SHIFT 24
1671+#define WF_LWTBL_G4_HE_DW 6
1672+#define WF_LWTBL_G4_HE_ADDR 24
1673+#define WF_LWTBL_G4_HE_MASK \
1674+ 0x0c000000 // 27-26
1675+#define WF_LWTBL_G4_HE_SHIFT 26
1676+#define WF_LWTBL_G8_HE_DW 6
1677+#define WF_LWTBL_G8_HE_ADDR 24
1678+#define WF_LWTBL_G8_HE_MASK \
1679+ 0x30000000 // 29-28
1680+#define WF_LWTBL_G8_HE_SHIFT 28
1681+#define WF_LWTBL_G16_HE_DW 6
1682+#define WF_LWTBL_G16_HE_ADDR 24
1683+#define WF_LWTBL_G16_HE_MASK \
1684+ 0xc0000000 // 31-30
1685+#define WF_LWTBL_G16_HE_SHIFT 30
1686+// DW7
1687+#define WF_LWTBL_BA_WIN_SIZE0_DW 7
1688+#define WF_LWTBL_BA_WIN_SIZE0_ADDR 28
1689+#define WF_LWTBL_BA_WIN_SIZE0_MASK \
1690+ 0x0000000f // 3- 0
1691+#define WF_LWTBL_BA_WIN_SIZE0_SHIFT 0
1692+#define WF_LWTBL_BA_WIN_SIZE1_DW 7
1693+#define WF_LWTBL_BA_WIN_SIZE1_ADDR 28
1694+#define WF_LWTBL_BA_WIN_SIZE1_MASK \
1695+ 0x000000f0 // 7- 4
1696+#define WF_LWTBL_BA_WIN_SIZE1_SHIFT 4
1697+#define WF_LWTBL_BA_WIN_SIZE2_DW 7
1698+#define WF_LWTBL_BA_WIN_SIZE2_ADDR 28
1699+#define WF_LWTBL_BA_WIN_SIZE2_MASK \
1700+ 0x00000f00 // 11- 8
1701+#define WF_LWTBL_BA_WIN_SIZE2_SHIFT 8
1702+#define WF_LWTBL_BA_WIN_SIZE3_DW 7
1703+#define WF_LWTBL_BA_WIN_SIZE3_ADDR 28
1704+#define WF_LWTBL_BA_WIN_SIZE3_MASK \
1705+ 0x0000f000 // 15-12
1706+#define WF_LWTBL_BA_WIN_SIZE3_SHIFT 12
1707+#define WF_LWTBL_BA_WIN_SIZE4_DW 7
1708+#define WF_LWTBL_BA_WIN_SIZE4_ADDR 28
1709+#define WF_LWTBL_BA_WIN_SIZE4_MASK \
1710+ 0x000f0000 // 19-16
1711+#define WF_LWTBL_BA_WIN_SIZE4_SHIFT 16
1712+#define WF_LWTBL_BA_WIN_SIZE5_DW 7
1713+#define WF_LWTBL_BA_WIN_SIZE5_ADDR 28
1714+#define WF_LWTBL_BA_WIN_SIZE5_MASK \
1715+ 0x00f00000 // 23-20
1716+#define WF_LWTBL_BA_WIN_SIZE5_SHIFT 20
1717+#define WF_LWTBL_BA_WIN_SIZE6_DW 7
1718+#define WF_LWTBL_BA_WIN_SIZE6_ADDR 28
1719+#define WF_LWTBL_BA_WIN_SIZE6_MASK \
1720+ 0x0f000000 // 27-24
1721+#define WF_LWTBL_BA_WIN_SIZE6_SHIFT 24
1722+#define WF_LWTBL_BA_WIN_SIZE7_DW 7
1723+#define WF_LWTBL_BA_WIN_SIZE7_ADDR 28
1724+#define WF_LWTBL_BA_WIN_SIZE7_MASK \
1725+ 0xf0000000 // 31-28
1726+#define WF_LWTBL_BA_WIN_SIZE7_SHIFT 28
1727+// DW8
1728+#define WF_LWTBL_AC0_RTS_FAIL_CNT_DW 8
1729+#define WF_LWTBL_AC0_RTS_FAIL_CNT_ADDR 32
1730+#define WF_LWTBL_AC0_RTS_FAIL_CNT_MASK \
1731+ 0x0000001f // 4- 0
1732+#define WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT 0
1733+#define WF_LWTBL_AC1_RTS_FAIL_CNT_DW 8
1734+#define WF_LWTBL_AC1_RTS_FAIL_CNT_ADDR 32
1735+#define WF_LWTBL_AC1_RTS_FAIL_CNT_MASK \
1736+ 0x000003e0 // 9- 5
1737+#define WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT 5
1738+#define WF_LWTBL_AC2_RTS_FAIL_CNT_DW 8
1739+#define WF_LWTBL_AC2_RTS_FAIL_CNT_ADDR 32
1740+#define WF_LWTBL_AC2_RTS_FAIL_CNT_MASK \
1741+ 0x00007c00 // 14-10
1742+#define WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT 10
1743+#define WF_LWTBL_AC3_RTS_FAIL_CNT_DW 8
1744+#define WF_LWTBL_AC3_RTS_FAIL_CNT_ADDR 32
1745+#define WF_LWTBL_AC3_RTS_FAIL_CNT_MASK \
1746+ 0x000f8000 // 19-15
1747+#define WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT 15
1748+#define WF_LWTBL_PARTIAL_AID_DW 8
1749+#define WF_LWTBL_PARTIAL_AID_ADDR 32
1750+#define WF_LWTBL_PARTIAL_AID_MASK \
1751+ 0x1ff00000 // 28-20
1752+#define WF_LWTBL_PARTIAL_AID_SHIFT 20
1753+#define WF_LWTBL_CHK_PER_DW 8
1754+#define WF_LWTBL_CHK_PER_ADDR 32
1755+#define WF_LWTBL_CHK_PER_MASK \
1756+ 0x80000000 // 31-31
1757+#define WF_LWTBL_CHK_PER_SHIFT 31
1758+// DW9
1759+#define WF_LWTBL_RX_AVG_MPDU_SIZE_DW 9
1760+#define WF_LWTBL_RX_AVG_MPDU_SIZE_ADDR 36
1761+#define WF_LWTBL_RX_AVG_MPDU_SIZE_MASK \
1762+ 0x00003fff // 13- 0
1763+#define WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT 0
1764+#define WF_LWTBL_PRITX_SW_MODE_DW 9
1765+#define WF_LWTBL_PRITX_SW_MODE_ADDR 36
1766+#define WF_LWTBL_PRITX_SW_MODE_MASK \
1767+ 0x00008000 // 15-15
1768+#define WF_LWTBL_PRITX_SW_MODE_SHIFT 15
1769+#define WF_LWTBL_PRITX_ERSU_DW 9
1770+#define WF_LWTBL_PRITX_ERSU_ADDR 36
1771+#define WF_LWTBL_PRITX_ERSU_MASK \
1772+ 0x00010000 // 16-16
1773+#define WF_LWTBL_PRITX_ERSU_SHIFT 16
1774+#define WF_LWTBL_PRITX_PLR_DW 9
1775+#define WF_LWTBL_PRITX_PLR_ADDR 36
1776+#define WF_LWTBL_PRITX_PLR_MASK \
1777+ 0x00020000 // 17-17
1778+#define WF_LWTBL_PRITX_PLR_SHIFT 17
1779+#define WF_LWTBL_PRITX_DCM_DW 9
1780+#define WF_LWTBL_PRITX_DCM_ADDR 36
1781+#define WF_LWTBL_PRITX_DCM_MASK \
1782+ 0x00040000 // 18-18
1783+#define WF_LWTBL_PRITX_DCM_SHIFT 18
1784+#define WF_LWTBL_PRITX_ER106T_DW 9
1785+#define WF_LWTBL_PRITX_ER106T_ADDR 36
1786+#define WF_LWTBL_PRITX_ER106T_MASK \
1787+ 0x00080000 // 19-19
1788+#define WF_LWTBL_PRITX_ER106T_SHIFT 19
1789+#define WF_LWTBL_FCAP_DW 9
1790+#define WF_LWTBL_FCAP_ADDR 36
1791+#define WF_LWTBL_FCAP_MASK \
1792+ 0x00700000 // 22-20
1793+#define WF_LWTBL_FCAP_SHIFT 20
1794+#define WF_LWTBL_MPDU_FAIL_CNT_DW 9
1795+#define WF_LWTBL_MPDU_FAIL_CNT_ADDR 36
1796+#define WF_LWTBL_MPDU_FAIL_CNT_MASK \
1797+ 0x03800000 // 25-23
1798+#define WF_LWTBL_MPDU_FAIL_CNT_SHIFT 23
1799+#define WF_LWTBL_MPDU_OK_CNT_DW 9
1800+#define WF_LWTBL_MPDU_OK_CNT_ADDR 36
1801+#define WF_LWTBL_MPDU_OK_CNT_MASK \
1802+ 0x1c000000 // 28-26
1803+#define WF_LWTBL_MPDU_OK_CNT_SHIFT 26
1804+#define WF_LWTBL_RATE_IDX_DW 9
1805+#define WF_LWTBL_RATE_IDX_ADDR 36
1806+#define WF_LWTBL_RATE_IDX_MASK \
1807+ 0xe0000000 // 31-29
1808+#define WF_LWTBL_RATE_IDX_SHIFT 29
1809+// DW10
1810+#define WF_LWTBL_RATE1_DW 10
1811+#define WF_LWTBL_RATE1_ADDR 40
1812+#define WF_LWTBL_RATE1_MASK \
1813+ 0x00007fff // 14- 0
1814+#define WF_LWTBL_RATE1_SHIFT 0
1815+#define WF_LWTBL_RATE2_DW 10
1816+#define WF_LWTBL_RATE2_ADDR 40
1817+#define WF_LWTBL_RATE2_MASK \
1818+ 0x7fff0000 // 30-16
1819+#define WF_LWTBL_RATE2_SHIFT 16
1820+// DW11
1821+#define WF_LWTBL_RATE3_DW 11
1822+#define WF_LWTBL_RATE3_ADDR 44
1823+#define WF_LWTBL_RATE3_MASK \
1824+ 0x00007fff // 14- 0
1825+#define WF_LWTBL_RATE3_SHIFT 0
1826+#define WF_LWTBL_RATE4_DW 11
1827+#define WF_LWTBL_RATE4_ADDR 44
1828+#define WF_LWTBL_RATE4_MASK \
1829+ 0x7fff0000 // 30-16
1830+#define WF_LWTBL_RATE4_SHIFT 16
1831+// DW12
1832+#define WF_LWTBL_RATE5_DW 12
1833+#define WF_LWTBL_RATE5_ADDR 48
1834+#define WF_LWTBL_RATE5_MASK \
1835+ 0x00007fff // 14- 0
1836+#define WF_LWTBL_RATE5_SHIFT 0
1837+#define WF_LWTBL_RATE6_DW 12
1838+#define WF_LWTBL_RATE6_ADDR 48
1839+#define WF_LWTBL_RATE6_MASK \
1840+ 0x7fff0000 // 30-16
1841+#define WF_LWTBL_RATE6_SHIFT 16
1842+// DW13
1843+#define WF_LWTBL_RATE7_DW 13
1844+#define WF_LWTBL_RATE7_ADDR 52
1845+#define WF_LWTBL_RATE7_MASK \
1846+ 0x00007fff // 14- 0
1847+#define WF_LWTBL_RATE7_SHIFT 0
1848+#define WF_LWTBL_RATE8_DW 13
1849+#define WF_LWTBL_RATE8_ADDR 52
1850+#define WF_LWTBL_RATE8_MASK \
1851+ 0x7fff0000 // 30-16
1852+#define WF_LWTBL_RATE8_SHIFT 16
1853+// DW14
1854+#define WF_LWTBL_RATE1_TX_CNT_DW 14
1855+#define WF_LWTBL_RATE1_TX_CNT_ADDR 56
1856+#define WF_LWTBL_RATE1_TX_CNT_MASK \
1857+ 0x0000ffff // 15- 0
1858+#define WF_LWTBL_RATE1_TX_CNT_SHIFT 0
1859+#define WF_LWTBL_CIPHER_SUIT_IGTK_DW 14
1860+#define WF_LWTBL_CIPHER_SUIT_IGTK_ADDR 56
1861+#define WF_LWTBL_CIPHER_SUIT_IGTK_MASK \
1862+ 0x00003000 // 13-12
1863+#define WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT 12
1864+#define WF_LWTBL_CIPHER_SUIT_BIGTK_DW 14
1865+#define WF_LWTBL_CIPHER_SUIT_BIGTK_ADDR 56
1866+#define WF_LWTBL_CIPHER_SUIT_BIGTK_MASK \
1867+ 0x0000c000 // 15-14
1868+#define WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT 14
1869+#define WF_LWTBL_RATE1_FAIL_CNT_DW 14
1870+#define WF_LWTBL_RATE1_FAIL_CNT_ADDR 56
1871+#define WF_LWTBL_RATE1_FAIL_CNT_MASK \
1872+ 0xffff0000 // 31-16
1873+#define WF_LWTBL_RATE1_FAIL_CNT_SHIFT 16
1874+// DW15
1875+#define WF_LWTBL_RATE2_OK_CNT_DW 15
1876+#define WF_LWTBL_RATE2_OK_CNT_ADDR 60
1877+#define WF_LWTBL_RATE2_OK_CNT_MASK \
1878+ 0x0000ffff // 15- 0
1879+#define WF_LWTBL_RATE2_OK_CNT_SHIFT 0
1880+#define WF_LWTBL_RATE3_OK_CNT_DW 15
1881+#define WF_LWTBL_RATE3_OK_CNT_ADDR 60
1882+#define WF_LWTBL_RATE3_OK_CNT_MASK \
1883+ 0xffff0000 // 31-16
1884+#define WF_LWTBL_RATE3_OK_CNT_SHIFT 16
1885+// DW16
1886+#define WF_LWTBL_CURRENT_BW_TX_CNT_DW 16
1887+#define WF_LWTBL_CURRENT_BW_TX_CNT_ADDR 64
1888+#define WF_LWTBL_CURRENT_BW_TX_CNT_MASK \
1889+ 0x0000ffff // 15- 0
1890+#define WF_LWTBL_CURRENT_BW_TX_CNT_SHIFT 0
1891+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_DW 16
1892+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_ADDR 64
1893+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_MASK \
1894+ 0xffff0000 // 31-16
1895+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_SHIFT 16
1896+// DW17
1897+#define WF_LWTBL_OTHER_BW_TX_CNT_DW 17
1898+#define WF_LWTBL_OTHER_BW_TX_CNT_ADDR 68
1899+#define WF_LWTBL_OTHER_BW_TX_CNT_MASK \
1900+ 0x0000ffff // 15- 0
1901+#define WF_LWTBL_OTHER_BW_TX_CNT_SHIFT 0
1902+#define WF_LWTBL_OTHER_BW_FAIL_CNT_DW 17
1903+#define WF_LWTBL_OTHER_BW_FAIL_CNT_ADDR 68
1904+#define WF_LWTBL_OTHER_BW_FAIL_CNT_MASK \
1905+ 0xffff0000 // 31-16
1906+#define WF_LWTBL_OTHER_BW_FAIL_CNT_SHIFT 16
1907+// DW18
1908+#define WF_LWTBL_RTS_OK_CNT_DW 18
1909+#define WF_LWTBL_RTS_OK_CNT_ADDR 72
1910+#define WF_LWTBL_RTS_OK_CNT_MASK \
1911+ 0x0000ffff // 15- 0
1912+#define WF_LWTBL_RTS_OK_CNT_SHIFT 0
1913+#define WF_LWTBL_RTS_FAIL_CNT_DW 18
1914+#define WF_LWTBL_RTS_FAIL_CNT_ADDR 72
1915+#define WF_LWTBL_RTS_FAIL_CNT_MASK \
1916+ 0xffff0000 // 31-16
1917+#define WF_LWTBL_RTS_FAIL_CNT_SHIFT 16
1918+// DW19
1919+#define WF_LWTBL_DATA_RETRY_CNT_DW 19
1920+#define WF_LWTBL_DATA_RETRY_CNT_ADDR 76
1921+#define WF_LWTBL_DATA_RETRY_CNT_MASK \
1922+ 0x0000ffff // 15- 0
1923+#define WF_LWTBL_DATA_RETRY_CNT_SHIFT 0
1924+#define WF_LWTBL_MGNT_RETRY_CNT_DW 19
1925+#define WF_LWTBL_MGNT_RETRY_CNT_ADDR 76
1926+#define WF_LWTBL_MGNT_RETRY_CNT_MASK \
1927+ 0xffff0000 // 31-16
1928+#define WF_LWTBL_MGNT_RETRY_CNT_SHIFT 16
1929+// DW20
1930+#define WF_LWTBL_AC0_CTT_CDT_CRB_DW 20
1931+#define WF_LWTBL_AC0_CTT_CDT_CRB_ADDR 80
1932+#define WF_LWTBL_AC0_CTT_CDT_CRB_MASK \
1933+ 0xffffffff // 31- 0
1934+#define WF_LWTBL_AC0_CTT_CDT_CRB_SHIFT 0
1935+// DW21
1936+// DO NOT process repeat field(adm[0])
1937+// DW22
1938+#define WF_LWTBL_AC1_CTT_CDT_CRB_DW 22
1939+#define WF_LWTBL_AC1_CTT_CDT_CRB_ADDR 88
1940+#define WF_LWTBL_AC1_CTT_CDT_CRB_MASK \
1941+ 0xffffffff // 31- 0
1942+#define WF_LWTBL_AC1_CTT_CDT_CRB_SHIFT 0
1943+// DW23
1944+// DO NOT process repeat field(adm[1])
1945+// DW24
1946+#define WF_LWTBL_AC2_CTT_CDT_CRB_DW 24
1947+#define WF_LWTBL_AC2_CTT_CDT_CRB_ADDR 96
1948+#define WF_LWTBL_AC2_CTT_CDT_CRB_MASK \
1949+ 0xffffffff // 31- 0
1950+#define WF_LWTBL_AC2_CTT_CDT_CRB_SHIFT 0
1951+// DW25
1952+// DO NOT process repeat field(adm[2])
1953+// DW26
1954+#define WF_LWTBL_AC3_CTT_CDT_CRB_DW 26
1955+#define WF_LWTBL_AC3_CTT_CDT_CRB_ADDR 104
1956+#define WF_LWTBL_AC3_CTT_CDT_CRB_MASK \
1957+ 0xffffffff // 31- 0
1958+#define WF_LWTBL_AC3_CTT_CDT_CRB_SHIFT 0
1959+// DW27
1960+// DO NOT process repeat field(adm[3])
1961+// DW28
1962+#define WF_LWTBL_RELATED_IDX0_DW 28
1963+#define WF_LWTBL_RELATED_IDX0_ADDR 112
1964+#define WF_LWTBL_RELATED_IDX0_MASK \
1965+ 0x00000fff // 11- 0
1966+#define WF_LWTBL_RELATED_IDX0_SHIFT 0
1967+#define WF_LWTBL_RELATED_BAND0_DW 28
1968+#define WF_LWTBL_RELATED_BAND0_ADDR 112
1969+#define WF_LWTBL_RELATED_BAND0_MASK \
1970+ 0x00003000 // 13-12
1971+#define WF_LWTBL_RELATED_BAND0_SHIFT 12
1972+#define WF_LWTBL_PRIMARY_MLD_BAND_DW 28
1973+#define WF_LWTBL_PRIMARY_MLD_BAND_ADDR 112
1974+#define WF_LWTBL_PRIMARY_MLD_BAND_MASK \
1975+ 0x0000c000 // 15-14
1976+#define WF_LWTBL_PRIMARY_MLD_BAND_SHIFT 14
1977+#define WF_LWTBL_RELATED_IDX1_DW 28
1978+#define WF_LWTBL_RELATED_IDX1_ADDR 112
1979+#define WF_LWTBL_RELATED_IDX1_MASK \
1980+ 0x0fff0000 // 27-16
1981+#define WF_LWTBL_RELATED_IDX1_SHIFT 16
1982+#define WF_LWTBL_RELATED_BAND1_DW 28
1983+#define WF_LWTBL_RELATED_BAND1_ADDR 112
1984+#define WF_LWTBL_RELATED_BAND1_MASK \
1985+ 0x30000000 // 29-28
1986+#define WF_LWTBL_RELATED_BAND1_SHIFT 28
1987+#define WF_LWTBL_SECONDARY_MLD_BAND_DW 28
1988+#define WF_LWTBL_SECONDARY_MLD_BAND_ADDR 112
1989+#define WF_LWTBL_SECONDARY_MLD_BAND_MASK \
1990+ 0xc0000000 // 31-30
1991+#define WF_LWTBL_SECONDARY_MLD_BAND_SHIFT 30
1992+// DW29
1993+#define WF_LWTBL_DISPATCH_POLICY0_DW 29
1994+#define WF_LWTBL_DISPATCH_POLICY0_ADDR 116
1995+#define WF_LWTBL_DISPATCH_POLICY0_MASK \
1996+ 0x00000003 // 1- 0
1997+#define WF_LWTBL_DISPATCH_POLICY0_SHIFT 0
1998+#define WF_LWTBL_DISPATCH_POLICY1_DW 29
1999+#define WF_LWTBL_DISPATCH_POLICY1_ADDR 116
2000+#define WF_LWTBL_DISPATCH_POLICY1_MASK \
2001+ 0x0000000c // 3- 2
2002+#define WF_LWTBL_DISPATCH_POLICY1_SHIFT 2
2003+#define WF_LWTBL_DISPATCH_POLICY2_DW 29
2004+#define WF_LWTBL_DISPATCH_POLICY2_ADDR 116
2005+#define WF_LWTBL_DISPATCH_POLICY2_MASK \
2006+ 0x00000030 // 5- 4
2007+#define WF_LWTBL_DISPATCH_POLICY2_SHIFT 4
2008+#define WF_LWTBL_DISPATCH_POLICY3_DW 29
2009+#define WF_LWTBL_DISPATCH_POLICY3_ADDR 116
2010+#define WF_LWTBL_DISPATCH_POLICY3_MASK \
2011+ 0x000000c0 // 7- 6
2012+#define WF_LWTBL_DISPATCH_POLICY3_SHIFT 6
2013+#define WF_LWTBL_DISPATCH_POLICY4_DW 29
2014+#define WF_LWTBL_DISPATCH_POLICY4_ADDR 116
2015+#define WF_LWTBL_DISPATCH_POLICY4_MASK \
2016+ 0x00000300 // 9- 8
2017+#define WF_LWTBL_DISPATCH_POLICY4_SHIFT 8
2018+#define WF_LWTBL_DISPATCH_POLICY5_DW 29
2019+#define WF_LWTBL_DISPATCH_POLICY5_ADDR 116
2020+#define WF_LWTBL_DISPATCH_POLICY5_MASK \
2021+ 0x00000c00 // 11-10
2022+#define WF_LWTBL_DISPATCH_POLICY5_SHIFT 10
2023+#define WF_LWTBL_DISPATCH_POLICY6_DW 29
2024+#define WF_LWTBL_DISPATCH_POLICY6_ADDR 116
2025+#define WF_LWTBL_DISPATCH_POLICY6_MASK \
2026+ 0x00003000 // 13-12
2027+#define WF_LWTBL_DISPATCH_POLICY6_SHIFT 12
2028+#define WF_LWTBL_DISPATCH_POLICY7_DW 29
2029+#define WF_LWTBL_DISPATCH_POLICY7_ADDR 116
2030+#define WF_LWTBL_DISPATCH_POLICY7_MASK \
2031+ 0x0000c000 // 15-14
2032+#define WF_LWTBL_DISPATCH_POLICY7_SHIFT 14
2033+#define WF_LWTBL_OWN_MLD_ID_DW 29
2034+#define WF_LWTBL_OWN_MLD_ID_ADDR 116
2035+#define WF_LWTBL_OWN_MLD_ID_MASK \
2036+ 0x003f0000 // 21-16
2037+#define WF_LWTBL_OWN_MLD_ID_SHIFT 16
2038+#define WF_LWTBL_EMLSR0_DW 29
2039+#define WF_LWTBL_EMLSR0_ADDR 116
2040+#define WF_LWTBL_EMLSR0_MASK \
2041+ 0x00400000 // 22-22
2042+#define WF_LWTBL_EMLSR0_SHIFT 22
2043+#define WF_LWTBL_EMLMR0_DW 29
2044+#define WF_LWTBL_EMLMR0_ADDR 116
2045+#define WF_LWTBL_EMLMR0_MASK \
2046+ 0x00800000 // 23-23
2047+#define WF_LWTBL_EMLMR0_SHIFT 23
2048+#define WF_LWTBL_EMLSR1_DW 29
2049+#define WF_LWTBL_EMLSR1_ADDR 116
2050+#define WF_LWTBL_EMLSR1_MASK \
2051+ 0x01000000 // 24-24
2052+#define WF_LWTBL_EMLSR1_SHIFT 24
2053+#define WF_LWTBL_EMLMR1_DW 29
2054+#define WF_LWTBL_EMLMR1_ADDR 116
2055+#define WF_LWTBL_EMLMR1_MASK \
2056+ 0x02000000 // 25-25
2057+#define WF_LWTBL_EMLMR1_SHIFT 25
2058+#define WF_LWTBL_EMLSR2_DW 29
2059+#define WF_LWTBL_EMLSR2_ADDR 116
2060+#define WF_LWTBL_EMLSR2_MASK \
2061+ 0x04000000 // 26-26
2062+#define WF_LWTBL_EMLSR2_SHIFT 26
2063+#define WF_LWTBL_EMLMR2_DW 29
2064+#define WF_LWTBL_EMLMR2_ADDR 116
2065+#define WF_LWTBL_EMLMR2_MASK \
2066+ 0x08000000 // 27-27
2067+#define WF_LWTBL_EMLMR2_SHIFT 27
2068+#define WF_LWTBL_STR_BITMAP_DW 29
2069+#define WF_LWTBL_STR_BITMAP_ADDR 116
2070+#define WF_LWTBL_STR_BITMAP_MASK \
2071+ 0xe0000000 // 31-29
2072+#define WF_LWTBL_STR_BITMAP_SHIFT 29
2073+// DW30
2074+#define WF_LWTBL_DISPATCH_ORDER_DW 30
2075+#define WF_LWTBL_DISPATCH_ORDER_ADDR 120
2076+#define WF_LWTBL_DISPATCH_ORDER_MASK \
2077+ 0x0000007f // 6- 0
2078+#define WF_LWTBL_DISPATCH_ORDER_SHIFT 0
2079+#define WF_LWTBL_DISPATCH_RATIO_DW 30
2080+#define WF_LWTBL_DISPATCH_RATIO_ADDR 120
2081+#define WF_LWTBL_DISPATCH_RATIO_MASK \
2082+ 0x00003f80 // 13- 7
2083+#define WF_LWTBL_DISPATCH_RATIO_SHIFT 7
2084+#define WF_LWTBL_LINK_MGF_DW 30
2085+#define WF_LWTBL_LINK_MGF_ADDR 120
2086+#define WF_LWTBL_LINK_MGF_MASK \
2087+ 0xffff0000 // 31-16
2088+#define WF_LWTBL_LINK_MGF_SHIFT 16
2089+// DW31
2090+#define WF_LWTBL_NEGOTIATED_WINSIZE0_DW 31
2091+#define WF_LWTBL_NEGOTIATED_WINSIZE0_ADDR 124
2092+#define WF_LWTBL_NEGOTIATED_WINSIZE0_MASK \
2093+ 0x00000007 // 2- 0
2094+#define WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT 0
2095+#define WF_LWTBL_NEGOTIATED_WINSIZE1_DW 31
2096+#define WF_LWTBL_NEGOTIATED_WINSIZE1_ADDR 124
2097+#define WF_LWTBL_NEGOTIATED_WINSIZE1_MASK \
2098+ 0x00000038 // 5- 3
2099+#define WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT 3
2100+#define WF_LWTBL_NEGOTIATED_WINSIZE2_DW 31
2101+#define WF_LWTBL_NEGOTIATED_WINSIZE2_ADDR 124
2102+#define WF_LWTBL_NEGOTIATED_WINSIZE2_MASK \
2103+ 0x000001c0 // 8- 6
2104+#define WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT 6
2105+#define WF_LWTBL_NEGOTIATED_WINSIZE3_DW 31
2106+#define WF_LWTBL_NEGOTIATED_WINSIZE3_ADDR 124
2107+#define WF_LWTBL_NEGOTIATED_WINSIZE3_MASK \
2108+ 0x00000e00 // 11- 9
2109+#define WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT 9
2110+#define WF_LWTBL_NEGOTIATED_WINSIZE4_DW 31
2111+#define WF_LWTBL_NEGOTIATED_WINSIZE4_ADDR 124
2112+#define WF_LWTBL_NEGOTIATED_WINSIZE4_MASK \
2113+ 0x00007000 // 14-12
2114+#define WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT 12
2115+#define WF_LWTBL_NEGOTIATED_WINSIZE5_DW 31
2116+#define WF_LWTBL_NEGOTIATED_WINSIZE5_ADDR 124
2117+#define WF_LWTBL_NEGOTIATED_WINSIZE5_MASK \
2118+ 0x00038000 // 17-15
2119+#define WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT 15
2120+#define WF_LWTBL_NEGOTIATED_WINSIZE6_DW 31
2121+#define WF_LWTBL_NEGOTIATED_WINSIZE6_ADDR 124
2122+#define WF_LWTBL_NEGOTIATED_WINSIZE6_MASK \
2123+ 0x001c0000 // 20-18
2124+#define WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT 18
2125+#define WF_LWTBL_NEGOTIATED_WINSIZE7_DW 31
2126+#define WF_LWTBL_NEGOTIATED_WINSIZE7_ADDR 124
2127+#define WF_LWTBL_NEGOTIATED_WINSIZE7_MASK \
2128+ 0x00e00000 // 23-21
2129+#define WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT 21
2130+#define WF_LWTBL_CASCAD_DW 31
2131+#define WF_LWTBL_CASCAD_ADDR 124
2132+#define WF_LWTBL_CASCAD_MASK \
2133+ 0x02000000 // 25-25
2134+#define WF_LWTBL_CASCAD_SHIFT 25
2135+#define WF_LWTBL_ALL_ACK_DW 31
2136+#define WF_LWTBL_ALL_ACK_ADDR 124
2137+#define WF_LWTBL_ALL_ACK_MASK \
2138+ 0x04000000 // 26-26
2139+#define WF_LWTBL_ALL_ACK_SHIFT 26
2140+#define WF_LWTBL_MPDU_SIZE_DW 31
2141+#define WF_LWTBL_MPDU_SIZE_ADDR 124
2142+#define WF_LWTBL_MPDU_SIZE_MASK \
2143+ 0x18000000 // 28-27
2144+#define WF_LWTBL_MPDU_SIZE_SHIFT 27
2145+#define WF_LWTBL_BA_MODE_DW 31
2146+#define WF_LWTBL_BA_MODE_ADDR 124
2147+#define WF_LWTBL_BA_MODE_MASK \
2148+ 0xe0000000 // 31-29
2149+#define WF_LWTBL_BA_MODE_SHIFT 29
2150+// DW32
2151+#define WF_LWTBL_OM_INFO_DW 32
2152+#define WF_LWTBL_OM_INFO_ADDR 128
2153+#define WF_LWTBL_OM_INFO_MASK \
2154+ 0x00000fff // 11- 0
2155+#define WF_LWTBL_OM_INFO_SHIFT 0
2156+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_DW 32
2157+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_ADDR 128
2158+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK \
2159+ 0x00001000 // 12-12
2160+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_SHIFT 12
2161+#define WF_LWTBL_RXD_DUP_WHITE_LIST_DW 32
2162+#define WF_LWTBL_RXD_DUP_WHITE_LIST_ADDR 128
2163+#define WF_LWTBL_RXD_DUP_WHITE_LIST_MASK \
2164+ 0x01ffe000 // 24-13
2165+#define WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT 13
2166+#define WF_LWTBL_RXD_DUP_MODE_DW 32
2167+#define WF_LWTBL_RXD_DUP_MODE_ADDR 128
2168+#define WF_LWTBL_RXD_DUP_MODE_MASK \
2169+ 0x06000000 // 26-25
2170+#define WF_LWTBL_RXD_DUP_MODE_SHIFT 25
2171+#define WF_LWTBL_DROP_DW 32
2172+#define WF_LWTBL_DROP_ADDR 128
2173+#define WF_LWTBL_DROP_MASK \
2174+ 0x40000000 // 30-30
2175+#define WF_LWTBL_DROP_SHIFT 30
2176+#define WF_LWTBL_ACK_EN_DW 32
2177+#define WF_LWTBL_ACK_EN_ADDR 128
2178+#define WF_LWTBL_ACK_EN_MASK \
2179+ 0x80000000 // 31-31
2180+#define WF_LWTBL_ACK_EN_SHIFT 31
2181+// DW33
2182+#define WF_LWTBL_USER_RSSI_DW 33
2183+#define WF_LWTBL_USER_RSSI_ADDR 132
2184+#define WF_LWTBL_USER_RSSI_MASK \
2185+ 0x000001ff // 8- 0
2186+#define WF_LWTBL_USER_RSSI_SHIFT 0
2187+#define WF_LWTBL_USER_SNR_DW 33
2188+#define WF_LWTBL_USER_SNR_ADDR 132
2189+#define WF_LWTBL_USER_SNR_MASK \
2190+ 0x00007e00 // 14- 9
2191+#define WF_LWTBL_USER_SNR_SHIFT 9
2192+#define WF_LWTBL_RAPID_REACTION_RATE_DW 33
2193+#define WF_LWTBL_RAPID_REACTION_RATE_ADDR 132
2194+#define WF_LWTBL_RAPID_REACTION_RATE_MASK \
2195+ 0x0fff0000 // 27-16
2196+#define WF_LWTBL_RAPID_REACTION_RATE_SHIFT 16
2197+#define WF_LWTBL_HT_AMSDU_DW 33
2198+#define WF_LWTBL_HT_AMSDU_ADDR 132
2199+#define WF_LWTBL_HT_AMSDU_MASK \
2200+ 0x40000000 // 30-30
2201+#define WF_LWTBL_HT_AMSDU_SHIFT 30
2202+#define WF_LWTBL_AMSDU_CROSS_LG_DW 33
2203+#define WF_LWTBL_AMSDU_CROSS_LG_ADDR 132
2204+#define WF_LWTBL_AMSDU_CROSS_LG_MASK \
2205+ 0x80000000 // 31-31
2206+#define WF_LWTBL_AMSDU_CROSS_LG_SHIFT 31
2207+// DW34
2208+#define WF_LWTBL_RESP_RCPI0_DW 34
2209+#define WF_LWTBL_RESP_RCPI0_ADDR 136
2210+#define WF_LWTBL_RESP_RCPI0_MASK \
2211+ 0x000000ff // 7- 0
2212+#define WF_LWTBL_RESP_RCPI0_SHIFT 0
2213+#define WF_LWTBL_RESP_RCPI1_DW 34
2214+#define WF_LWTBL_RESP_RCPI1_ADDR 136
2215+#define WF_LWTBL_RESP_RCPI1_MASK \
2216+ 0x0000ff00 // 15- 8
2217+#define WF_LWTBL_RESP_RCPI1_SHIFT 8
2218+#define WF_LWTBL_RESP_RCPI2_DW 34
2219+#define WF_LWTBL_RESP_RCPI2_ADDR 136
2220+#define WF_LWTBL_RESP_RCPI2_MASK \
2221+ 0x00ff0000 // 23-16
2222+#define WF_LWTBL_RESP_RCPI2_SHIFT 16
2223+#define WF_LWTBL_RESP_RCPI3_DW 34
2224+#define WF_LWTBL_RESP_RCPI3_ADDR 136
2225+#define WF_LWTBL_RESP_RCPI3_MASK \
2226+ 0xff000000 // 31-24
2227+#define WF_LWTBL_RESP_RCPI3_SHIFT 24
2228+// DW35
2229+#define WF_LWTBL_SNR_RX0_DW 35
2230+#define WF_LWTBL_SNR_RX0_ADDR 140
2231+#define WF_LWTBL_SNR_RX0_MASK \
2232+ 0x0000003f // 5- 0
2233+#define WF_LWTBL_SNR_RX0_SHIFT 0
2234+#define WF_LWTBL_SNR_RX1_DW 35
2235+#define WF_LWTBL_SNR_RX1_ADDR 140
2236+#define WF_LWTBL_SNR_RX1_MASK \
2237+ 0x00000fc0 // 11- 6
2238+#define WF_LWTBL_SNR_RX1_SHIFT 6
2239+#define WF_LWTBL_SNR_RX2_DW 35
2240+#define WF_LWTBL_SNR_RX2_ADDR 140
2241+#define WF_LWTBL_SNR_RX2_MASK \
2242+ 0x0003f000 // 17-12
2243+#define WF_LWTBL_SNR_RX2_SHIFT 12
2244+#define WF_LWTBL_SNR_RX3_DW 35
2245+#define WF_LWTBL_SNR_RX3_ADDR 140
2246+#define WF_LWTBL_SNR_RX3_MASK \
2247+ 0x00fc0000 // 23-18
2248+#define WF_LWTBL_SNR_RX3_SHIFT 18
2249+
2250+/* WTBL Group - Packet Number */
2251+/* DW 2 */
2252+#define WTBL_PN0_MASK BITS(0, 7)
2253+#define WTBL_PN0_OFFSET 0
2254+#define WTBL_PN1_MASK BITS(8, 15)
2255+#define WTBL_PN1_OFFSET 8
2256+#define WTBL_PN2_MASK BITS(16, 23)
2257+#define WTBL_PN2_OFFSET 16
2258+#define WTBL_PN3_MASK BITS(24, 31)
2259+#define WTBL_PN3_OFFSET 24
2260+
2261+/* DW 3 */
2262+#define WTBL_PN4_MASK BITS(0, 7)
2263+#define WTBL_PN4_OFFSET 0
2264+#define WTBL_PN5_MASK BITS(8, 15)
2265+#define WTBL_PN5_OFFSET 8
2266+
2267+/* DW 4 */
2268+#define WTBL_BIPN0_MASK BITS(0, 7)
2269+#define WTBL_BIPN0_OFFSET 0
2270+#define WTBL_BIPN1_MASK BITS(8, 15)
2271+#define WTBL_BIPN1_OFFSET 8
2272+#define WTBL_BIPN2_MASK BITS(16, 23)
2273+#define WTBL_BIPN2_OFFSET 16
2274+#define WTBL_BIPN3_MASK BITS(24, 31)
2275+#define WTBL_BIPN3_OFFSET 24
2276+
2277+/* DW 5 */
2278+#define WTBL_BIPN4_MASK BITS(0, 7)
2279+#define WTBL_BIPN4_OFFSET 0
2280+#define WTBL_BIPN5_MASK BITS(8, 15)
2281+#define WTBL_BIPN5_OFFSET 8
2282+
2283+/* UWTBL DW 6 */
2284+#define WTBL_AMSDU_LEN_MASK BITS(0, 5)
2285+#define WTBL_AMSDU_LEN_OFFSET 0
2286+#define WTBL_AMSDU_NUM_MASK BITS(6, 10)
2287+#define WTBL_AMSDU_NUM_OFFSET 6
2288+#define WTBL_AMSDU_EN_MASK BIT(11)
2289+#define WTBL_AMSDU_EN_OFFSET 11
2290+
2291+/* LWTBL Rate field */
2292+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
2293+#define WTBL_RATE_TX_RATE_OFFSET 0
2294+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
2295+#define WTBL_RATE_TX_MODE_OFFSET 6
2296+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
2297+#define WTBL_RATE_NSTS_OFFSET 10
2298+#define WTBL_RATE_STBC_MASK BIT(14)
2299+#define WTBL_RATE_STBC_OFFSET 14
2300+
2301+/***** WTBL(LMAC) DW Offset *****/
2302+/* LMAC WTBL Group - Peer Unique Information */
2303+#define WTBL_GROUP_PEER_INFO_DW_0 0
2304+#define WTBL_GROUP_PEER_INFO_DW_1 1
2305+
2306+/* WTBL Group - TxRx Capability/Information */
2307+#define WTBL_GROUP_TRX_CAP_DW_2 2
2308+#define WTBL_GROUP_TRX_CAP_DW_3 3
2309+#define WTBL_GROUP_TRX_CAP_DW_4 4
2310+#define WTBL_GROUP_TRX_CAP_DW_5 5
2311+#define WTBL_GROUP_TRX_CAP_DW_6 6
2312+#define WTBL_GROUP_TRX_CAP_DW_7 7
2313+#define WTBL_GROUP_TRX_CAP_DW_8 8
2314+#define WTBL_GROUP_TRX_CAP_DW_9 9
2315+
2316+/* WTBL Group - Auto Rate Table*/
2317+#define WTBL_GROUP_AUTO_RATE_1_2 10
2318+#define WTBL_GROUP_AUTO_RATE_3_4 11
2319+#define WTBL_GROUP_AUTO_RATE_5_6 12
2320+#define WTBL_GROUP_AUTO_RATE_7_8 13
2321+
2322+/* WTBL Group - Tx Counter */
2323+#define WTBL_GROUP_TX_CNT_LINE_1 14
2324+#define WTBL_GROUP_TX_CNT_LINE_2 15
2325+#define WTBL_GROUP_TX_CNT_LINE_3 16
2326+#define WTBL_GROUP_TX_CNT_LINE_4 17
2327+#define WTBL_GROUP_TX_CNT_LINE_5 18
2328+#define WTBL_GROUP_TX_CNT_LINE_6 19
2329+
2330+/* WTBL Group - Admission Control Counter */
2331+#define WTBL_GROUP_ADM_CNT_LINE_1 20
2332+#define WTBL_GROUP_ADM_CNT_LINE_2 21
2333+#define WTBL_GROUP_ADM_CNT_LINE_3 22
2334+#define WTBL_GROUP_ADM_CNT_LINE_4 23
2335+#define WTBL_GROUP_ADM_CNT_LINE_5 24
2336+#define WTBL_GROUP_ADM_CNT_LINE_6 25
2337+#define WTBL_GROUP_ADM_CNT_LINE_7 26
2338+#define WTBL_GROUP_ADM_CNT_LINE_8 27
2339+
2340+/* WTBL Group -MLO Info */
2341+#define WTBL_GROUP_MLO_INFO_LINE_1 28
2342+#define WTBL_GROUP_MLO_INFO_LINE_2 29
2343+#define WTBL_GROUP_MLO_INFO_LINE_3 30
2344+
2345+/* WTBL Group -RESP Info */
2346+#define WTBL_GROUP_RESP_INFO_DW_31 31
2347+
2348+/* WTBL Group -RX DUP Info */
2349+#define WTBL_GROUP_RX_DUP_INFO_DW_32 32
2350+
2351+/* WTBL Group - Rx Statistics Counter */
2352+#define WTBL_GROUP_RX_STAT_CNT_LINE_1 33
2353+#define WTBL_GROUP_RX_STAT_CNT_LINE_2 34
2354+#define WTBL_GROUP_RX_STAT_CNT_LINE_3 35
2355+
2356+/* UWTBL Group - HW AMSDU */
2357+#define UWTBL_HW_AMSDU_DW WF_UWTBL_AMSDU_CFG_DW
2358+
2359+/* LWTBL DW 4 */
2360+#define WTBL_DIS_RHTR WF_LWTBL_DIS_RHTR_MASK
2361+
2362+/* UWTBL DW 5 */
2363+#define WTBL_KEY_LINK_DW_KEY_LOC0_MASK BITS(0, 10)
2364+#define WTBL_PSM WF_LWTBL_PSM_MASK
2365+
2366+/* Need to sync with FW define */
2367+#define INVALID_KEY_ENTRY WTBL_KEY_LINK_DW_KEY_LOC0_MASK
2368+
2369+// RATE
2370+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
2371+#define WTBL_RATE_TX_RATE_OFFSET 0
2372+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
2373+#define WTBL_RATE_TX_MODE_OFFSET 6
2374+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
2375+#define WTBL_RATE_NSTS_OFFSET 10
2376+#define WTBL_RATE_STBC_MASK BIT(14)
2377+#define WTBL_RATE_STBC_OFFSET 14
2378+#endif
2379+
2380+#endif
2381diff --git a/mt7996/mtk_debugfs.c b/mt7996/mtk_debugfs.c
2382new file mode 100644
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2383index 00000000..f04c300f
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2384--- /dev/null
2385+++ b/mt7996/mtk_debugfs.c
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2386@@ -0,0 +1,2353 @@
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2387+// SPDX-License-Identifier: ISC
2388+/*
2389+ * Copyright (C) 2023 MediaTek Inc.
2390+ */
2391+#include "mt7996.h"
2392+#include "../mt76.h"
2393+#include "mcu.h"
2394+#include "mac.h"
2395+#include "eeprom.h"
2396+#include "mtk_debug.h"
2397+#include "mtk_mcu.h"
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2398+#include "coredump.h"
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2399+
2400+#ifdef CONFIG_MTK_DEBUG
2401+
2402+/* AGG INFO */
2403+static int
2404+mt7996_agginfo_read_per_band(struct seq_file *s, int band_idx)
2405+{
2406+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2407+ u64 total_burst, total_ampdu, ampdu_cnt[16];
2408+ u32 value, idx, row_idx, col_idx, start_range, agg_rang_sel[16], burst_cnt[16], band_offset = 0;
2409+ u8 readFW = 0, partial_str[16] = {}, full_str[64] = {};
2410+
2411+ switch (band_idx) {
2412+ case 0:
2413+ band_offset = 0;
2414+ break;
2415+ case 1:
2416+ band_offset = BN1_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
2417+ break;
2418+ case 2:
2419+ band_offset = IP1_BN0_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
2420+ break;
2421+ default:
2422+ return 0;
2423+ }
2424+
2425+ seq_printf(s, "Band %d AGG Status\n", band_idx);
2426+ seq_printf(s, "===============================\n");
2427+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR0_ADDR + band_offset);
2428+ seq_printf(s, "AC00 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT);
2429+ seq_printf(s, "AC01 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT);
2430+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR1_ADDR + band_offset);
2431+ seq_printf(s, "AC02 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT);
2432+ seq_printf(s, "AC03 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT);
2433+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR2_ADDR + band_offset);
2434+ seq_printf(s, "AC10 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT);
2435+ seq_printf(s, "AC11 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT);
2436+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR3_ADDR + band_offset);
2437+ seq_printf(s, "AC12 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT);
2438+ seq_printf(s, "AC13 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT);
2439+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR4_ADDR + band_offset);
2440+ seq_printf(s, "AC20 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT);
2441+ seq_printf(s, "AC21 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT);
2442+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR5_ADDR + band_offset);
2443+ seq_printf(s, "AC22 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT);
2444+ seq_printf(s, "AC23 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT);
2445+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR6_ADDR + band_offset);
2446+ seq_printf(s, "AC30 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT);
2447+ seq_printf(s, "AC31 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT);
2448+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR7_ADDR + band_offset);
2449+ seq_printf(s, "AC32 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT);
2450+ seq_printf(s, "AC33 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT);
2451+
2452+ switch (band_idx) {
2453+ case 0:
2454+ band_offset = 0;
2455+ break;
2456+ case 1:
2457+ band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
2458+ break;
2459+ case 2:
2460+ band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
2461+ break;
2462+ default:
2463+ return 0;
2464+ }
2465+
2466+ seq_printf(s, "===AMPDU Related Counters===\n");
2467+
2468+ if (readFW) {
2469+ /* BELLWETHER TODO: Wait MIB counter API implement complete */
2470+ } else {
2471+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC0_ADDR + band_offset);
2472+ agg_rang_sel[0] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT;
2473+ agg_rang_sel[1] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT;
2474+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC1_ADDR + band_offset);
2475+ agg_rang_sel[2] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT;
2476+ agg_rang_sel[3] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT;
2477+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC2_ADDR + band_offset);
2478+ agg_rang_sel[4] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT;
2479+ agg_rang_sel[5] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT;
2480+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC3_ADDR + band_offset);
2481+ agg_rang_sel[6] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT;
2482+ agg_rang_sel[7] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT;
2483+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC4_ADDR + band_offset);
2484+ agg_rang_sel[8] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT;
2485+ agg_rang_sel[9] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT;
2486+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC5_ADDR + band_offset);
2487+ agg_rang_sel[10] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT;
2488+ agg_rang_sel[11] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT;
2489+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC6_ADDR + band_offset);
2490+ agg_rang_sel[12] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT;
2491+ agg_rang_sel[13] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT;
2492+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC7_ADDR + band_offset);
2493+ agg_rang_sel[14] = (value & BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK) >> BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT;
2494+
2495+ burst_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR0_ADDR + band_offset);
2496+ burst_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR1_ADDR + band_offset);
2497+ burst_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR2_ADDR + band_offset);
2498+ burst_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR3_ADDR + band_offset);
2499+ burst_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR4_ADDR + band_offset);
2500+ burst_cnt[5] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR5_ADDR + band_offset);
2501+ burst_cnt[6] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR6_ADDR + band_offset);
2502+ burst_cnt[7] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR7_ADDR + band_offset);
2503+ burst_cnt[8] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR8_ADDR + band_offset);
2504+ burst_cnt[9] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR9_ADDR + band_offset);
2505+ burst_cnt[10] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR10_ADDR + band_offset);
2506+ burst_cnt[11] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR11_ADDR + band_offset);
2507+ burst_cnt[12] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR12_ADDR + band_offset);
2508+ burst_cnt[13] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR13_ADDR + band_offset);
2509+ burst_cnt[14] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR14_ADDR + band_offset);
2510+ burst_cnt[15] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR15_ADDR + band_offset);
2511+ }
2512+
2513+ start_range = 1;
2514+ total_burst = 0;
2515+ total_ampdu = 0;
2516+ agg_rang_sel[15] = 1023;
2517+
2518+ /* Need to add 1 after read from AGG_RANG_SEL CR */
2519+ for (idx = 0; idx < 16; idx++) {
2520+ agg_rang_sel[idx]++;
2521+ total_burst += burst_cnt[idx];
2522+
2523+ if (start_range == agg_rang_sel[idx])
2524+ ampdu_cnt[idx] = (u64) start_range * burst_cnt[idx];
2525+ else
2526+ ampdu_cnt[idx] = (u64) ((start_range + agg_rang_sel[idx]) >> 1) * burst_cnt[idx];
2527+
2528+ start_range = agg_rang_sel[idx] + 1;
2529+ total_ampdu += ampdu_cnt[idx];
2530+ }
2531+
2532+ start_range = 1;
2533+ sprintf(full_str, "%13s ", "Tx Agg Range:");
2534+
2535+ for (row_idx = 0; row_idx < 4; row_idx++) {
2536+ for (col_idx = 0; col_idx < 4; col_idx++, idx++) {
2537+ idx = 4 * row_idx + col_idx;
2538+
2539+ if (start_range == agg_rang_sel[idx])
2540+ sprintf(partial_str, "%d", agg_rang_sel[idx]);
2541+ else
2542+ sprintf(partial_str, "%d~%d", start_range, agg_rang_sel[idx]);
2543+
2544+ start_range = agg_rang_sel[idx] + 1;
2545+ sprintf(full_str + strlen(full_str), "%-11s ", partial_str);
2546+ }
2547+
2548+ idx = 4 * row_idx;
2549+
2550+ seq_printf(s, "%s\n", full_str);
2551+ seq_printf(s, "%13s 0x%-9x 0x%-9x 0x%-9x 0x%-9x\n",
2552+ row_idx ? "" : "Burst count:",
2553+ burst_cnt[idx], burst_cnt[idx + 1],
2554+ burst_cnt[idx + 2], burst_cnt[idx + 3]);
2555+
2556+ if (total_burst != 0) {
2557+ if (row_idx == 0)
2558+ sprintf(full_str, "%13s ",
2559+ "Burst ratio:");
2560+ else
2561+ sprintf(full_str, "%13s ", "");
2562+
2563+ for (col_idx = 0; col_idx < 4; col_idx++) {
2564+ u64 count = (u64) burst_cnt[idx + col_idx] * 100;
2565+
2566+ sprintf(partial_str, "(%llu%%)",
2567+ div64_u64(count, total_burst));
2568+ sprintf(full_str + strlen(full_str),
2569+ "%-11s ", partial_str);
2570+ }
2571+
2572+ seq_printf(s, "%s\n", full_str);
2573+
2574+ if (row_idx == 0)
2575+ sprintf(full_str, "%13s ",
2576+ "MDPU ratio:");
2577+ else
2578+ sprintf(full_str, "%13s ", "");
2579+
2580+ for (col_idx = 0; col_idx < 4; col_idx++) {
2581+ u64 count = ampdu_cnt[idx + col_idx] * 100;
2582+
2583+ sprintf(partial_str, "(%llu%%)",
2584+ div64_u64(count, total_ampdu));
2585+ sprintf(full_str + strlen(full_str),
2586+ "%-11s ", partial_str);
2587+ }
2588+
2589+ seq_printf(s, "%s\n", full_str);
2590+ }
2591+
2592+ sprintf(full_str, "%13s ", "");
2593+ }
2594+
2595+ return 0;
2596+}
2597+
2598+static int mt7996_agginfo_read_band0(struct seq_file *s, void *data)
2599+{
2600+ mt7996_agginfo_read_per_band(s, MT_BAND0);
2601+ return 0;
2602+}
2603+
2604+static int mt7996_agginfo_read_band1(struct seq_file *s, void *data)
2605+{
2606+ mt7996_agginfo_read_per_band(s, MT_BAND1);
2607+ return 0;
2608+}
2609+
2610+static int mt7996_agginfo_read_band2(struct seq_file *s, void *data)
2611+{
2612+ mt7996_agginfo_read_per_band(s, MT_BAND2);
2613+ return 0;
2614+}
2615+
2616+/* AMSDU INFO */
2617+static int mt7996_amsdu_result_read(struct seq_file *s, void *data)
2618+{
2619+#define HW_MSDU_CNT_ADDR 0xf400
2620+#define HW_MSDU_NUM_MAX 33
2621+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2622+ u32 ple_stat[HW_MSDU_NUM_MAX] = {0}, total_amsdu = 0;
2623+ u8 i;
2624+
2625+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
2626+ ple_stat[i] = mt76_rr(dev, HW_MSDU_CNT_ADDR + i * 0x04);
2627+
2628+ seq_printf(s, "TXD counter status of MSDU:\n");
2629+
2630+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
2631+ total_amsdu += ple_stat[i];
2632+
2633+ for (i = 0; i < HW_MSDU_NUM_MAX; i++) {
2634+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i, ple_stat[i]);
2635+ if (total_amsdu != 0)
2636+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
2637+ else
2638+ seq_printf(s, "\n");
2639+ }
2640+
2641+ return 0;
2642+}
2643+
2644+/* DBG MODLE */
2645+static int
2646+mt7996_fw_debug_module_set(void *data, u64 module)
2647+{
2648+ struct mt7996_dev *dev = data;
2649+
2650+ dev->dbg.fw_dbg_module = module;
2651+ return 0;
2652+}
2653+
2654+static int
2655+mt7996_fw_debug_module_get(void *data, u64 *module)
2656+{
2657+ struct mt7996_dev *dev = data;
2658+
2659+ *module = dev->dbg.fw_dbg_module;
2660+ return 0;
2661+}
2662+
2663+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7996_fw_debug_module_get,
2664+ mt7996_fw_debug_module_set, "%lld\n");
2665+
2666+static int
2667+mt7996_fw_debug_level_set(void *data, u64 level)
2668+{
2669+ struct mt7996_dev *dev = data;
2670+
2671+ dev->dbg.fw_dbg_lv = level;
2672+ mt7996_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
2673+ return 0;
2674+}
2675+
2676+static int
2677+mt7996_fw_debug_level_get(void *data, u64 *level)
2678+{
2679+ struct mt7996_dev *dev = data;
2680+
2681+ *level = dev->dbg.fw_dbg_lv;
2682+ return 0;
2683+}
2684+
2685+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7996_fw_debug_level_get,
2686+ mt7996_fw_debug_level_set, "%lld\n");
2687+
2688+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
2689+static int
2690+mt7996_wa_set(void *data, u64 val)
2691+{
2692+ struct mt7996_dev *dev = data;
2693+ u32 arg1, arg2, arg3;
2694+
2695+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
2696+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
2697+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
2698+
2699+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
2700+ arg1, arg2, arg3);
2701+}
2702+
2703+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7996_wa_set,
2704+ "0x%llx\n");
2705+
2706+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
2707+static int
2708+mt7996_wa_query(void *data, u64 val)
2709+{
2710+ struct mt7996_dev *dev = data;
2711+ u32 arg1, arg2, arg3;
2712+
2713+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
2714+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
2715+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
2716+
2717+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
2718+ arg1, arg2, arg3);
2719+ return 0;
2720+}
2721+
2722+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7996_wa_query,
2723+ "0x%llx\n");
2724+
2725+static int mt7996_dump_version(struct seq_file *s, void *data)
2726+{
2727+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2728+ seq_printf(s, "Version: 3.3.10.0\n");
2729+
2730+ if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
2731+ return 0;
2732+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2733+ seq_printf(s, "Rom Patch Build Time: %.16s\n", dev->patch_build_date);
2734+ seq_printf(s, "WM Patch Build Time: %.15s, Mode: %s\n",
2735+ dev->ram_build_date[MT7996_RAM_TYPE_WM],
2736+ dev->testmode_enable ? "Testmode" : "Normal mode");
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2737+ seq_printf(s, "WA Patch Build Time: %.15s\n",
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2738+ dev->ram_build_date[MT7996_RAM_TYPE_WA]);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2739+ seq_printf(s, "DSP Patch Build Time: %.15s\n",
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2740+ dev->ram_build_date[MT7996_RAM_TYPE_DSP]);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2741+ return 0;
2742+}
2743+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2744+/* fw wm call trace info dump */
2745+void mt7996_show_lp_history(struct seq_file *s, u32 type)
2746+{
2747+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2748+ struct mt7996_crash_data *crash_data;
2749+ struct mt7996_coredump *dump;
2750+ u64 now = 0;
2751+ int i = 0;
2752+ u8 fw_type = !!type;
2753+
2754+ mutex_lock(&dev->dump_mutex);
2755+
2756+ crash_data = mt7996_coredump_new(dev, fw_type);
2757+ if (!crash_data) {
2758+ mutex_unlock(&dev->dump_mutex);
2759+ seq_printf(s, "the coredump is disable!\n");
2760+ return;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2761+ }
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2762+ mutex_unlock(&dev->dump_mutex);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2763+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2764+ dump = mt7996_coredump_build(dev, fw_type, false);
2765+ if (!dump) {
2766+ seq_printf(s, "no call stack data found!\n");
2767+ return;
2768+ }
2769+
2770+ seq_printf(s, "\x1b[32m%s log output\x1b[0m\n", dump->fw_type);
2771+ seq_printf(s, "\x1b[32mfw status: %s\n", dump->fw_state);
2772+ mt7996_dump_version(s, NULL);
2773+ /* PC log */
2774+ now = jiffies;
2775+ for (i = 0; i < 10; i++)
2776+ seq_printf(s, "\tCurrent PC=%x\n", dump->pc_cur[i]);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2777+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2778+ seq_printf(s, "PC log contorl=0x%x(T=%llu)(latest PC index = 0x%x)\n",
2779+ dump->pc_dbg_ctrl, now, dump->pc_cur_idx);
2780+ for (i = 0; i < 32; i++)
2781+ seq_printf(s, "\tPC log(%d)=0x%08x\n", i, dump->pc_stack[i]);
2782+
2783+ /* LR log */
2784+ now = jiffies;
2785+ seq_printf(s, "\nLR log contorl=0x%x(T=%llu)(latest LR index = 0x%x)\n",
2786+ dump->lr_dbg_ctrl, now, dump->lr_cur_idx);
2787+ for (i = 0; i < 32; i++)
2788+ seq_printf(s, "\tLR log(%d)=0x%08x\n", i, dump->lr_stack[i]);
2789+
2790+ vfree(dump);
2791+}
2792+
2793+static int mt7996_fw_wa_info_read(struct seq_file *s, void *data)
2794+{
2795+ seq_printf(s, "======[ShowPcLpHistory]======\n");
2796+ mt7996_show_lp_history(s, MT7996_RAM_TYPE_WA);
2797+ seq_printf(s, "======[End ShowPcLpHistory]==\n");
2798+
2799+ return 0;
2800+}
2801+
2802+static int mt7996_fw_wm_info_read(struct seq_file *s, void *data)
2803+{
2804+ seq_printf(s, "======[ShowPcLpHistory]======\n");
2805+ mt7996_show_lp_history(s, MT7996_RAM_TYPE_WM);
2806+ seq_printf(s, "======[End ShowPcLpHistory]==\n");
2807+
2808+ return 0;
2809+}
2810+
2811+/* dma info dump */
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2812+static void
2813+dump_dma_tx_ring_info(struct seq_file *s, struct mt7996_dev *dev, char *str1, char *str2, u32 ring_base)
2814+{
2815+ u32 base, cnt, cidx, didx, queue_cnt;
2816+
2817+ base= mt76_rr(dev, ring_base);
2818+ cnt = mt76_rr(dev, ring_base + 4);
2819+ cidx = mt76_rr(dev, ring_base + 8);
2820+ didx = mt76_rr(dev, ring_base + 12);
2821+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2822+
2823+ seq_printf(s, "%20s %6s %10x %15x %10x %10x %10x\n", str1, str2, base, cnt, cidx, didx, queue_cnt);
2824+}
2825+
2826+static void
2827+dump_dma_rx_ring_info(struct seq_file *s, struct mt7996_dev *dev, char *str1, char *str2, u32 ring_base)
2828+{
2829+ u32 base, ctrl1, cnt, cidx, didx, queue_cnt;
2830+
2831+ base= mt76_rr(dev, ring_base);
2832+ ctrl1 = mt76_rr(dev, ring_base + 4);
2833+ cidx = mt76_rr(dev, ring_base + 8) & 0xfff;
2834+ didx = mt76_rr(dev, ring_base + 12) & 0xfff;
2835+ cnt = ctrl1 & 0xfff;
2836+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2837+
2838+ seq_printf(s, "%20s %6s %10x %10x(%3x) %10x %10x %10x\n",
2839+ str1, str2, base, ctrl1, cnt, cidx, didx, queue_cnt);
2840+}
2841+
2842+static void
2843+mt7996_show_dma_info(struct seq_file *s, struct mt7996_dev *dev)
2844+{
2845+ u32 sys_ctrl[10];
2846+
2847+ /* HOST DMA0 information */
2848+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR);
2849+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR);
2850+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR);
2851+
2852+ seq_printf(s, "HOST_DMA Configuration\n");
2853+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2854+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2855+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2856+ "DMA0", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2],
2857+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
2858+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2859+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
2860+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2861+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
2862+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2863+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
2864+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2865+
2866+ if (dev->hif2) {
2867+ /* HOST DMA1 information */
2868+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR);
2869+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR);
2870+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR);
2871+
2872+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2873+ "DMA0P1", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2],
2874+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
2875+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2876+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
2877+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2878+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
2879+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2880+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
2881+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2882+ }
2883+
2884+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2885+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
2886+ "Name", "Used", "Base", "Ctrl1(Cnt)", "CIDX", "DIDX", "QCnt");
2887+ dump_dma_tx_ring_info(s, dev, "T0:TXD0(H2MAC)", "STA",
2888+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2889+ dump_dma_tx_ring_info(s, dev, "T1:TXD1(H2MAC)", "STA",
2890+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2891+ dump_dma_tx_ring_info(s, dev, "T2:TXD2(H2MAC)", "STA",
2892+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2893+ dump_dma_tx_ring_info(s, dev, "T3:", "STA",
2894+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2895+ dump_dma_tx_ring_info(s, dev, "T4:", "STA",
2896+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2897+ dump_dma_tx_ring_info(s, dev, "T5:", "STA",
2898+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2899+ dump_dma_tx_ring_info(s, dev, "T6:", "STA",
2900+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2901+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", "Both",
2902+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR);
2903+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", "Both",
2904+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR);
2905+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", "AP",
2906+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR);
2907+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", "AP",
2908+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR);
2909+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", "AP",
2910+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR);
2911+ dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP",
2912+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR);
2913+ dump_dma_tx_ring_info(s, dev, "T22:TXD3(H2WA)", "AP",
2914+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL0_ADDR);
2915+
2916+
2917+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", "Both",
2918+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2919+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", "AP",
2920+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2921+ dump_dma_rx_ring_info(s, dev, "R2:TxDone0(WA2H)", "AP",
2922+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2923+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP",
2924+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2925+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", "Both",
2926+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2927+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both",
2928+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2929+ dump_dma_rx_ring_info(s, dev, "R6:BUF1(MAC2H)", "Both",
2930+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2931+ dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "Both",
2932+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2933+ dump_dma_rx_ring_info(s, dev, "R8:BUF0(MAC2H)", "Both",
2934+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2935+ dump_dma_rx_ring_info(s, dev, "R9:TxDone0(MAC2H)", "Both",
2936+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2937+ dump_dma_rx_ring_info(s, dev, "R10:MSDU_PG0(MAC2H)", "Both",
2938+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR);
2939+ dump_dma_rx_ring_info(s, dev, "R11:MSDU_PG1(MAC2H)", "Both",
2940+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR);
2941+ dump_dma_rx_ring_info(s, dev, "R12:MSDU_PG2(MAC2H)", "Both",
2942+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL0_ADDR);
2943+ dump_dma_rx_ring_info(s, dev, "IND:IND_CMD(MAC2H)", "Both",
2944+ WF_RRO_TOP_IND_CMD_0_CTRL0_ADDR);
2945+
2946+ if (dev->hif2) {
2947+ seq_printf(s, "HOST_DMA0 PCIe1 Ring Configuration\n");
2948+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
2949+ "Name", "Used", "Base", "Ctrl1(Cnt)", "CIDX", "DIDX", "QCnt");
2950+ dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP",
2951+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL0_ADDR);
2952+ dump_dma_tx_ring_info(s, dev, "T22:TXD?(H2WA)", "AP",
2953+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL0_ADDR);
2954+
2955+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP",
2956+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2957+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both",
2958+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL0_ADDR);
2959+ dump_dma_rx_ring_info(s, dev, "R6:BUF1(MAC2H)", "Both",
2960+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL0_ADDR);
2961+ dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "Both",
2962+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL0_ADDR);
2963+ }
2964+
2965+ /* MCU DMA information */
2966+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2967+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2968+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2969+
2970+ seq_printf(s, "MCU_DMA Configuration\n");
2971+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2972+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2973+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2974+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2975+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
2976+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2977+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
2978+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2979+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
2980+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2981+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
2982+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2983+
2984+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2985+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
2986+ "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2987+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", "Both",
2988+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2989+ dump_dma_tx_ring_info(s, dev, "T1:Event(WA2H)", "AP",
2990+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2991+ dump_dma_tx_ring_info(s, dev, "T2:TxDone0(WA2H)", "AP",
2992+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2993+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1(WA2H)", "AP",
2994+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2995+ dump_dma_tx_ring_info(s, dev, "T4:TXD(WM2MAC)", "Both",
2996+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2997+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD(WM2MAC)", "Both",
2998+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2999+ dump_dma_tx_ring_info(s, dev, "T6:TXD(WA2MAC)", "AP",
3000+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
3001+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", "Both",
3002+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
3003+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", "Both",
3004+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
3005+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", "AP",
3006+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
3007+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", "AP",
3008+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
3009+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", "AP",
3010+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
3011+ dump_dma_rx_ring_info(s, dev, "R5:Data0(MAC2WM)", "Both",
3012+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
3013+ dump_dma_rx_ring_info(s, dev, "R6:TxDone(MAC2WM)", "Both",
3014+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
3015+ dump_dma_rx_ring_info(s, dev, "R7:SPL/RPT(MAC2WM)", "Both",
3016+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
3017+ dump_dma_rx_ring_info(s, dev, "R8:TxDone(MAC2WA)", "AP",
3018+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
3019+ dump_dma_rx_ring_info(s, dev, "R9:Data1(MAC2WM)", "Both",
3020+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
3021+ dump_dma_rx_ring_info(s, dev, "R10:TXD2(H2WA)", "AP",
3022+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR);
3023+
3024+ /* MEM DMA information */
3025+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
3026+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
3027+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
3028+
3029+ seq_printf(s, "MEM_DMA Configuration\n");
3030+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
3031+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
3032+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
3033+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
3034+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
3035+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
3036+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
3037+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
3038+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
3039+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
3040+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
3041+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
3042+
3043+ seq_printf(s, "MEM_DMA Ring Configuration\n");
3044+ seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n",
3045+ "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
3046+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", "AP",
3047+ WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
3048+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", "AP",
3049+ WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
3050+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", "AP",
3051+ WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
3052+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", "AP",
3053+ WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
3054+}
3055+
3056+static int mt7996_trinfo_read(struct seq_file *s, void *data)
3057+{
3058+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3059+ mt7996_show_dma_info(s, dev);
3060+ return 0;
3061+}
3062+
3063+/* MIB INFO */
3064+static int mt7996_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3065+{
3066+#define BSS_NUM 4
3067+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3068+ u8 bss_nums = BSS_NUM;
3069+ u32 idx;
3070+ u32 mac_val, band_offset = 0, band_offset_umib = 0;
3071+ u32 msdr6, msdr9, msdr18;
3072+ u32 rvsr0, rscr26, rscr35, mctr5, mctr6, msr0, msr1, msr2;
3073+ u32 tbcr0, tbcr1, tbcr2, tbcr3, tbcr4;
3074+ u32 btscr[7];
3075+ u32 tdrcr[5];
3076+ u32 mbtocr[16], mbtbcr[16], mbrocr[16], mbrbcr[16];
3077+ u32 btcr, btbcr, brocr, brbcr, btdcr, brdcr;
3078+ u32 mu_cnt[5];
3079+ u32 ampdu_cnt[3];
3080+ u64 per;
3081+
3082+ switch (band_idx) {
3083+ case 0:
3084+ band_offset = 0;
3085+ band_offset_umib = 0;
3086+ break;
3087+ case 1:
3088+ band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
3089+ band_offset_umib = WF_UMIB_TOP_B1BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR;
3090+ break;
3091+ case 2:
3092+ band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
3093+ band_offset_umib = WF_UMIB_TOP_B2BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR;
3094+ break;
3095+ default:
3096+ return true;
3097+ }
3098+
3099+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3100+ seq_printf(s, "===============================\n");
3101+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_M0SCR0_ADDR + band_offset);
3102+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3103+
3104+ msdr6 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR6_ADDR + band_offset);
3105+ rvsr0 = mt76_rr(dev, BN0_WF_MIB_TOP_RVSR0_ADDR + band_offset);
3106+ rscr35 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR35_ADDR + band_offset);
3107+ msdr9 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR9_ADDR + band_offset);
3108+ rscr26 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR26_ADDR + band_offset);
3109+ mctr5 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR5_ADDR + band_offset);
3110+ mctr6 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR6_ADDR + band_offset);
3111+ msdr18 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR18_ADDR + band_offset);
3112+ msr0 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR0_ADDR + band_offset);
3113+ msr1 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR1_ADDR + band_offset);
3114+ msr2 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR2_ADDR + band_offset);
3115+ ampdu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR0_ADDR + band_offset);
3116+ ampdu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR3_ADDR + band_offset);
3117+ ampdu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR4_ADDR + band_offset);
3118+ ampdu_cnt[1] &= BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK;
3119+ ampdu_cnt[2] &= BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK;
3120+
3121+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3122+ seq_printf(s, "\tChannelIdleCnt=0x%x\n",
3123+ msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3124+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n",
3125+ msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3126+ seq_printf(s, "\tRx_MDRDY_CNT=0x%x\n",
3127+ rscr26 & BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK);
3128+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x",
3129+ msr0 & BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK,
3130+ msr1 & BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK);
3131+ seq_printf(s, ", OFDM_GREEN_MDRDY_TIME=0x%x\n",
3132+ msr2 & BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK);
3133+ seq_printf(s, "\tPrim CCA Time=0x%x\n",
3134+ mctr5 & BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK);
3135+ seq_printf(s, "\tSec CCA Time=0x%x\n",
3136+ mctr6 & BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK);
3137+ seq_printf(s, "\tPrim ED Time=0x%x\n",
3138+ msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3139+
3140+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3141+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR18_ADDR + band_offset);
3142+ dev->dbg.bcn_total_cnt[band_idx] +=
3143+ (mac_val & BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK);
3144+ seq_printf(s, "\tBeaconTxCnt=0x%x\n", dev->dbg.bcn_total_cnt[band_idx]);
3145+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3146+
3147+ tbcr0 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR0_ADDR + band_offset);
3148+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n",
3149+ tbcr0 & BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK);
3150+ tbcr1 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR1_ADDR + band_offset);
3151+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n",
3152+ tbcr1 & BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK);
3153+ tbcr2 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR2_ADDR + band_offset);
3154+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n",
3155+ tbcr2 & BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK);
3156+ tbcr3 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR3_ADDR + band_offset);
3157+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n",
3158+ tbcr3 & BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK);
3159+ tbcr4 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR4_ADDR + band_offset);
3160+ seq_printf(s, "\tTx 320MHz Cnt=0x%x\n",
3161+ tbcr4 & BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK);
3162+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3163+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3164+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3165+ per = (ampdu_cnt[2] == 0 ?
3166+ 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3167+ seq_printf(s, "\tAMPDU MPDU PER=%llu.%1llu%%\n", per / 10, per % 10);
3168+
3169+ seq_printf(s, "===MU Related Counters===\n");
3170+ mu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSCR2_ADDR + band_offset);
3171+ mu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR5_ADDR + band_offset);
3172+ mu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR6_ADDR + band_offset);
3173+ mu_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR8_ADDR + band_offset);
3174+ mu_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR7_ADDR + band_offset);
3175+
3176+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n",
3177+ mu_cnt[0] & BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK);
3178+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3179+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3180+ seq_printf(s, "\tMU_TO_MU_FAIL_PPDU_COUNT=0x%x\n", mu_cnt[3]);
3181+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3182+
3183+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3184+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n",
3185+ rvsr0 & BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK);
3186+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n",
3187+ rscr35 & BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK);
3188+
3189+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR1_ADDR + band_offset);
3190+ seq_printf(s, "\tRxFCSErrCnt=0x%x\n",
3191+ (mac_val & BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK));
3192+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR33_ADDR + band_offset);
3193+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n",
3194+ (mac_val & BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK));
3195+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR36_ADDR + band_offset);
3196+ seq_printf(s, "\tRxLenMismatch=0x%x\n",
3197+ (mac_val & BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK));
3198+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR31_ADDR + band_offset);
3199+ seq_printf(s, "\tRxMPDUCnt=0x%x\n",
3200+ (mac_val & BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK));
3201+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR27_ADDR + band_offset);
3202+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3203+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR28_ADDR + band_offset);
3204+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3205+
3206+
3207+ /* Per-BSS T/RX Counters */
3208+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3209+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxOkCnt/DataCnt RxByteCnt\n");
3210+ for (idx = 0; idx < bss_nums; idx++) {
3211+ btcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTCR_ADDR + band_offset + idx * 4);
3212+ btdcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + idx * 4);
3213+ btbcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + idx * 4);
3214+
3215+ brocr = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + idx * 4);
3216+ brdcr = mt76_rr(dev, WF_UMIB_TOP_B0BRDCR_ADDR + band_offset_umib + idx * 4);
3217+ brbcr = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + idx * 4);
3218+
3219+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3220+ idx, btcr, btdcr, btbcr, brocr, brdcr, brbcr);
3221+ }
3222+
3223+ seq_printf(s, "===Per-BSS Related MIB Counters===\n");
3224+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3225+
3226+ /* Per-BSS TX Status */
3227+ for (idx = 0; idx < bss_nums; idx++) {
3228+ btscr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR5_ADDR + band_offset + idx * 4);
3229+ btscr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR6_ADDR + band_offset + idx * 4);
3230+ btscr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR0_ADDR + band_offset + idx * 4);
3231+ btscr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR1_ADDR + band_offset + idx * 4);
3232+ btscr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR2_ADDR + band_offset + idx * 4);
3233+ btscr[5] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR3_ADDR + band_offset + idx * 4);
3234+ btscr[6] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR4_ADDR + band_offset + idx * 4);
3235+
3236+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
3237+ idx, (btscr[0] & BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK),
3238+ (btscr[1] & BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK),
3239+ (btscr[2] & BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK),
3240+ (btscr[3] & BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK),
3241+ (btscr[4] & BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK),
3242+ (btscr[5] & BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK),
3243+ (btscr[6] & BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK));
3244+ }
3245+
3246+ /* Dummy delimiter insertion result */
3247+ seq_printf(s, "===Dummy delimiter insertion result===\n");
3248+ tdrcr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR0_ADDR + band_offset);
3249+ tdrcr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR1_ADDR + band_offset);
3250+ tdrcr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR2_ADDR + band_offset);
3251+ tdrcr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR3_ADDR + band_offset);
3252+ tdrcr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR4_ADDR + band_offset);
3253+
3254+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
3255+ tdrcr[0],
3256+ tdrcr[1],
3257+ tdrcr[2],
3258+ tdrcr[3],
3259+ tdrcr[4]);
3260+
3261+ /* Per-MBSS T/RX Counters */
3262+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3263+ seq_printf(s, "MBSSIdx TxOkCnt TxByteCnt RxOkCnt RxByteCnt\n");
3264+
3265+ for (idx = 0; idx < 16; idx++) {
3266+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (bss_nums + idx) * 4);
3267+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (bss_nums + idx) * 4);
3268+
3269+ mbrocr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + (bss_nums + idx) * 4);
3270+ mbrbcr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + (bss_nums + idx) * 4);
3271+ }
3272+
3273+ for (idx = 0; idx < 16; idx++) {
3274+ seq_printf(s, "%d\t 0x%x\t 0x%x \t 0x%x \t 0x%x\n",
3275+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
3276+ }
3277+
3278+ return 0;
3279+}
3280+
3281+static int mt7996_mibinfo_band0(struct seq_file *s, void *data)
3282+{
3283+ mt7996_mibinfo_read_per_band(s, MT_BAND0);
3284+ return 0;
3285+}
3286+
3287+static int mt7996_mibinfo_band1(struct seq_file *s, void *data)
3288+{
3289+ mt7996_mibinfo_read_per_band(s, MT_BAND1);
3290+ return 0;
3291+}
3292+
3293+static int mt7996_mibinfo_band2(struct seq_file *s, void *data)
3294+{
3295+ mt7996_mibinfo_read_per_band(s, MT_BAND2);
3296+ return 0;
3297+}
3298+
3299+/* WTBL INFO */
3300+static int
3301+mt7996_wtbl_read_raw(struct mt7996_dev *dev, u16 idx,
3302+ enum mt7996_wtbl_type type, u16 start_dw,
3303+ u16 len, void *buf)
3304+{
3305+ u32 *dest_cpy = (u32 *)buf;
3306+ u32 size_dw = len;
3307+ u32 src = 0;
3308+
3309+ if (!buf)
3310+ return 0xFF;
3311+
3312+ if (type == WTBL_TYPE_LMAC) {
3313+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR,
3314+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
3315+ src = LWTBL_IDX2BASE(idx, start_dw);
3316+ } else if (type == WTBL_TYPE_UMAC) {
3317+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3318+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3319+ src = UWTBL_IDX2BASE(idx, start_dw);
3320+ } else if (type == WTBL_TYPE_KEY) {
3321+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3322+ MT_DBG_UWTBL_TOP_WDUCR_TARGET |
3323+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3324+ src = KEYTBL_IDX2BASE(idx, start_dw);
3325+ }
3326+
3327+ while (size_dw--) {
3328+ *dest_cpy++ = mt76_rr(dev, src);
3329+ src += 4;
3330+ };
3331+
3332+ return 0;
3333+}
3334+
3335+#if 0
3336+static int
3337+mt7996_wtbl_write_raw(struct mt7996_dev *dev, u16 idx,
3338+ enum mt7996_wtbl_type type, u16 start_dw,
3339+ u32 val)
3340+{
3341+ u32 addr = 0;
3342+
3343+ if (type == WTBL_TYPE_LMAC) {
3344+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR,
3345+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
3346+ addr = LWTBL_IDX2BASE(idx, start_dw);
3347+ } else if (type == WTBL_TYPE_UMAC) {
3348+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3349+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3350+ addr = UWTBL_IDX2BASE(idx, start_dw);
3351+ } else if (type == WTBL_TYPE_KEY) {
3352+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3353+ MT_DBG_UWTBL_TOP_WDUCR_TARGET |
3354+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3355+ addr = KEYTBL_IDX2BASE(idx, start_dw);
3356+ }
3357+
3358+ mt76_wr(dev, addr, val);
3359+
3360+ return 0;
3361+}
3362+#endif
3363+
3364+static const struct berse_wtbl_parse WTBL_LMAC_DW0[] = {
3365+ {"MUAR_IDX", WF_LWTBL_MUAR_MASK, WF_LWTBL_MUAR_SHIFT,false},
3366+ {"RCA1", WF_LWTBL_RCA1_MASK, NO_SHIFT_DEFINE, false},
3367+ {"KID", WF_LWTBL_KID_MASK, WF_LWTBL_KID_SHIFT, false},
3368+ {"RCID", WF_LWTBL_RCID_MASK, NO_SHIFT_DEFINE, false},
3369+ {"BAND", WF_LWTBL_BAND_MASK, WF_LWTBL_BAND_SHIFT,false},
3370+ {"RV", WF_LWTBL_RV_MASK, NO_SHIFT_DEFINE, false},
3371+ {"RCA2", WF_LWTBL_RCA2_MASK, NO_SHIFT_DEFINE, false},
3372+ {"WPI_FLAG", WF_LWTBL_WPI_FLAG_MASK, NO_SHIFT_DEFINE,true},
3373+ {NULL,}
3374+};
3375+
3376+static void parse_fmac_lwtbl_dw0_1(struct seq_file *s, u8 *lwtbl)
3377+{
3378+ u32 *addr = 0;
3379+ u32 dw_value = 0;
3380+ u16 i = 0;
3381+
3382+ seq_printf(s, "\t\n");
3383+ seq_printf(s, "LinkAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
3384+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
3385+
3386+ /* LMAC WTBL DW 0 */
3387+ seq_printf(s, "\t\n");
3388+ seq_printf(s, "LWTBL DW 0/1\n");
3389+ addr = (u32 *)&(lwtbl[WTBL_GROUP_PEER_INFO_DW_0*4]);
3390+ dw_value = *addr;
3391+
3392+ while (WTBL_LMAC_DW0[i].name) {
3393+
3394+ if (WTBL_LMAC_DW0[i].shift == NO_SHIFT_DEFINE)
3395+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW0[i].name,
3396+ (dw_value & WTBL_LMAC_DW0[i].mask) ? 1 : 0);
3397+ else
3398+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW0[i].name,
3399+ (dw_value & WTBL_LMAC_DW0[i].mask) >> WTBL_LMAC_DW0[i].shift);
3400+ i++;
3401+ }
3402+}
3403+
3404+static const struct berse_wtbl_parse WTBL_LMAC_DW2[] = {
3405+ {"AID", WF_LWTBL_AID_MASK, WF_LWTBL_AID_SHIFT, false},
3406+ {"GID_SU", WF_LWTBL_GID_SU_MASK, NO_SHIFT_DEFINE, false},
3407+ {"SPP_EN", WF_LWTBL_SPP_EN_MASK, NO_SHIFT_DEFINE, false},
3408+ {"WPI_EVEN", WF_LWTBL_WPI_EVEN_MASK, NO_SHIFT_DEFINE, false},
3409+ {"AAD_OM", WF_LWTBL_AAD_OM_MASK, NO_SHIFT_DEFINE, false},
3410+ {"CIPHER_PGTK",WF_LWTBL_CIPHER_SUIT_PGTK_MASK, WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT, true},
3411+ {"FROM_DS", WF_LWTBL_FD_MASK, NO_SHIFT_DEFINE, false},
3412+ {"TO_DS", WF_LWTBL_TD_MASK, NO_SHIFT_DEFINE, false},
3413+ {"SW", WF_LWTBL_SW_MASK, NO_SHIFT_DEFINE, false},
3414+ {"UL", WF_LWTBL_UL_MASK, NO_SHIFT_DEFINE, false},
3415+ {"TX_POWER_SAVE", WF_LWTBL_TX_PS_MASK, NO_SHIFT_DEFINE, true},
3416+ {"QOS", WF_LWTBL_QOS_MASK, NO_SHIFT_DEFINE, false},
3417+ {"HT", WF_LWTBL_HT_MASK, NO_SHIFT_DEFINE, false},
3418+ {"VHT", WF_LWTBL_VHT_MASK, NO_SHIFT_DEFINE, false},
3419+ {"HE", WF_LWTBL_HE_MASK, NO_SHIFT_DEFINE, false},
3420+ {"EHT", WF_LWTBL_EHT_MASK, NO_SHIFT_DEFINE, false},
3421+ {"MESH", WF_LWTBL_MESH_MASK, NO_SHIFT_DEFINE, true},
3422+ {NULL,}
3423+};
3424+
3425+static void parse_fmac_lwtbl_dw2(struct seq_file *s, u8 *lwtbl)
3426+{
3427+ u32 *addr = 0;
3428+ u32 dw_value = 0;
3429+ u16 i = 0;
3430+
3431+ /* LMAC WTBL DW 2 */
3432+ seq_printf(s, "\t\n");
3433+ seq_printf(s, "LWTBL DW 2\n");
3434+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]);
3435+ dw_value = *addr;
3436+
3437+ while (WTBL_LMAC_DW2[i].name) {
3438+
3439+ if (WTBL_LMAC_DW2[i].shift == NO_SHIFT_DEFINE)
3440+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW2[i].name,
3441+ (dw_value & WTBL_LMAC_DW2[i].mask) ? 1 : 0);
3442+ else
3443+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW2[i].name,
3444+ (dw_value & WTBL_LMAC_DW2[i].mask) >> WTBL_LMAC_DW2[i].shift);
3445+ i++;
3446+ }
3447+}
3448+
3449+static const struct berse_wtbl_parse WTBL_LMAC_DW3[] = {
3450+ {"WMM_Q", WF_LWTBL_WMM_Q_MASK, WF_LWTBL_WMM_Q_SHIFT, false},
3451+ {"EHT_SIG_MCS", WF_LWTBL_EHT_SIG_MCS_MASK, WF_LWTBL_EHT_SIG_MCS_SHIFT, false},
3452+ {"HDRT_MODE", WF_LWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, false},
3453+ {"BEAM_CHG", WF_LWTBL_BEAM_CHG_MASK, NO_SHIFT_DEFINE, false},
3454+ {"EHT_LTF_SYM_NUM", WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK, WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT, true},
3455+ {"PFMU_IDX", WF_LWTBL_PFMU_IDX_MASK, WF_LWTBL_PFMU_IDX_SHIFT, false},
3456+ {"ULPF_IDX", WF_LWTBL_ULPF_IDX_MASK, WF_LWTBL_ULPF_IDX_SHIFT, false},
3457+ {"RIBF", WF_LWTBL_RIBF_MASK, NO_SHIFT_DEFINE, false},
3458+ {"ULPF", WF_LWTBL_ULPF_MASK, NO_SHIFT_DEFINE, true},
3459+ {"TBF_HT", WF_LWTBL_TBF_HT_MASK, NO_SHIFT_DEFINE, false},
3460+ {"TBF_VHT", WF_LWTBL_TBF_VHT_MASK, NO_SHIFT_DEFINE, false},
3461+ {"TBF_HE", WF_LWTBL_TBF_HE_MASK, NO_SHIFT_DEFINE, false},
3462+ {"TBF_EHT", WF_LWTBL_TBF_EHT_MASK, NO_SHIFT_DEFINE, false},
3463+ {"IGN_FBK", WF_LWTBL_IGN_FBK_MASK, NO_SHIFT_DEFINE, true},
3464+ {NULL,}
3465+};
3466+
3467+static void parse_fmac_lwtbl_dw3(struct seq_file *s, u8 *lwtbl)
3468+{
3469+ u32 *addr = 0;
3470+ u32 dw_value = 0;
3471+ u16 i = 0;
3472+
3473+ /* LMAC WTBL DW 3 */
3474+ seq_printf(s, "\t\n");
3475+ seq_printf(s, "LWTBL DW 3\n");
3476+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_3*4]);
3477+ dw_value = *addr;
3478+
3479+ while (WTBL_LMAC_DW3[i].name) {
3480+
3481+ if (WTBL_LMAC_DW3[i].shift == NO_SHIFT_DEFINE)
3482+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW3[i].name,
3483+ (dw_value & WTBL_LMAC_DW3[i].mask) ? 1 : 0);
3484+ else
3485+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW3[i].name,
3486+ (dw_value & WTBL_LMAC_DW3[i].mask) >> WTBL_LMAC_DW3[i].shift);
3487+ i++;
3488+ }
3489+}
3490+
3491+static const struct berse_wtbl_parse WTBL_LMAC_DW4[] = {
3492+ {"ANT_ID_STS0", WF_LWTBL_ANT_ID0_MASK, WF_LWTBL_ANT_ID0_SHIFT, false},
3493+ {"STS1", WF_LWTBL_ANT_ID1_MASK, WF_LWTBL_ANT_ID1_SHIFT, false},
3494+ {"STS2", WF_LWTBL_ANT_ID2_MASK, WF_LWTBL_ANT_ID2_SHIFT, false},
3495+ {"STS3", WF_LWTBL_ANT_ID3_MASK, WF_LWTBL_ANT_ID3_SHIFT, true},
3496+ {"ANT_ID_STS4", WF_LWTBL_ANT_ID4_MASK, WF_LWTBL_ANT_ID4_SHIFT, false},
3497+ {"STS5", WF_LWTBL_ANT_ID5_MASK, WF_LWTBL_ANT_ID5_SHIFT, false},
3498+ {"STS6", WF_LWTBL_ANT_ID6_MASK, WF_LWTBL_ANT_ID6_SHIFT, false},
3499+ {"STS7", WF_LWTBL_ANT_ID7_MASK, WF_LWTBL_ANT_ID7_SHIFT, true},
3500+ {"PE", WF_LWTBL_PE_MASK, WF_LWTBL_PE_SHIFT, false},
3501+ {"DIS_RHTR", WF_LWTBL_DIS_RHTR_MASK, NO_SHIFT_DEFINE, false},
3502+ {"LDPC_HT", WF_LWTBL_LDPC_HT_MASK, NO_SHIFT_DEFINE, false},
3503+ {"LDPC_VHT", WF_LWTBL_LDPC_VHT_MASK, NO_SHIFT_DEFINE, false},
3504+ {"LDPC_HE", WF_LWTBL_LDPC_HE_MASK, NO_SHIFT_DEFINE, false},
3505+ {"LDPC_EHT", WF_LWTBL_LDPC_EHT_MASK, NO_SHIFT_DEFINE, true},
3506+ {NULL,}
3507+};
3508+
3509+static void parse_fmac_lwtbl_dw4(struct seq_file *s, u8 *lwtbl)
3510+{
3511+ u32 *addr = 0;
3512+ u32 dw_value = 0;
3513+ u16 i = 0;
3514+
3515+ /* LMAC WTBL DW 4 */
3516+ seq_printf(s, "\t\n");
3517+ seq_printf(s, "LWTBL DW 4\n");
3518+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_4*4]);
3519+ dw_value = *addr;
3520+
3521+ while (WTBL_LMAC_DW4[i].name) {
3522+ if (WTBL_LMAC_DW4[i].shift == NO_SHIFT_DEFINE)
3523+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW4[i].name,
3524+ (dw_value & WTBL_LMAC_DW4[i].mask) ? 1 : 0);
3525+ else
3526+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW4[i].name,
3527+ (dw_value & WTBL_LMAC_DW4[i].mask) >> WTBL_LMAC_DW4[i].shift);
3528+ i++;
3529+ }
3530+}
3531+
3532+static const struct berse_wtbl_parse WTBL_LMAC_DW5[] = {
3533+ {"AF", WF_LWTBL_AF_MASK, WF_LWTBL_AF_SHIFT, false},
3534+ {"AF_HE", WF_LWTBL_AF_HE_MASK, WF_LWTBL_AF_HE_SHIFT,false},
3535+ {"RTS", WF_LWTBL_RTS_MASK, NO_SHIFT_DEFINE, false},
3536+ {"SMPS", WF_LWTBL_SMPS_MASK, NO_SHIFT_DEFINE, false},
3537+ {"DYN_BW", WF_LWTBL_DYN_BW_MASK, NO_SHIFT_DEFINE, true},
3538+ {"MMSS", WF_LWTBL_MMSS_MASK, WF_LWTBL_MMSS_SHIFT,false},
3539+ {"USR", WF_LWTBL_USR_MASK, NO_SHIFT_DEFINE, false},
3540+ {"SR_RATE", WF_LWTBL_SR_R_MASK, WF_LWTBL_SR_R_SHIFT,false},
3541+ {"SR_ABORT", WF_LWTBL_SR_ABORT_MASK, NO_SHIFT_DEFINE, true},
3542+ {"TX_POWER_OFFSET", WF_LWTBL_TX_POWER_OFFSET_MASK, WF_LWTBL_TX_POWER_OFFSET_SHIFT, false},
3543+ {"LTF_EHT", WF_LWTBL_LTF_EHT_MASK, WF_LWTBL_LTF_EHT_SHIFT, false},
3544+ {"GI_EHT", WF_LWTBL_GI_EHT_MASK, WF_LWTBL_GI_EHT_SHIFT, false},
3545+ {"DOPPL", WF_LWTBL_DOPPL_MASK, NO_SHIFT_DEFINE, false},
3546+ {"TXOP_PS_CAP", WF_LWTBL_TXOP_PS_CAP_MASK, NO_SHIFT_DEFINE, false},
3547+ {"DONOT_UPDATE_I_PSM", WF_LWTBL_DU_I_PSM_MASK, NO_SHIFT_DEFINE, true},
3548+ {"I_PSM", WF_LWTBL_I_PSM_MASK, NO_SHIFT_DEFINE, false},
3549+ {"PSM", WF_LWTBL_PSM_MASK, NO_SHIFT_DEFINE, false},
3550+ {"SKIP_TX", WF_LWTBL_SKIP_TX_MASK, NO_SHIFT_DEFINE, true},
3551+ {NULL,}
3552+};
3553+
3554+static void parse_fmac_lwtbl_dw5(struct seq_file *s, u8 *lwtbl)
3555+{
3556+ u32 *addr = 0;
3557+ u32 dw_value = 0;
3558+ u16 i = 0;
3559+
3560+ /* LMAC WTBL DW 5 */
3561+ seq_printf(s, "\t\n");
3562+ seq_printf(s, "LWTBL DW 5\n");
3563+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_5*4]);
3564+ dw_value = *addr;
3565+
3566+ while (WTBL_LMAC_DW5[i].name) {
3567+ if (WTBL_LMAC_DW5[i].shift == NO_SHIFT_DEFINE)
3568+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW5[i].name,
3569+ (dw_value & WTBL_LMAC_DW5[i].mask) ? 1 : 0);
3570+ else
3571+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW5[i].name,
3572+ (dw_value & WTBL_LMAC_DW5[i].mask) >> WTBL_LMAC_DW5[i].shift);
3573+ i++;
3574+ }
3575+}
3576+
3577+static const struct berse_wtbl_parse WTBL_LMAC_DW6[] = {
3578+ {"CBRN", WF_LWTBL_CBRN_MASK, WF_LWTBL_CBRN_SHIFT, false},
3579+ {"DBNSS_EN", WF_LWTBL_DBNSS_EN_MASK, NO_SHIFT_DEFINE, false},
3580+ {"BAF_EN", WF_LWTBL_BAF_EN_MASK, NO_SHIFT_DEFINE, false},
3581+ {"RDGBA", WF_LWTBL_RDGBA_MASK, NO_SHIFT_DEFINE, false},
3582+ {"RDG", WF_LWTBL_R_MASK, NO_SHIFT_DEFINE, false},
3583+ {"SPE_IDX", WF_LWTBL_SPE_IDX_MASK, WF_LWTBL_SPE_IDX_SHIFT, true},
3584+ {"G2", WF_LWTBL_G2_MASK, NO_SHIFT_DEFINE, false},
3585+ {"G4", WF_LWTBL_G4_MASK, NO_SHIFT_DEFINE, false},
3586+ {"G8", WF_LWTBL_G8_MASK, NO_SHIFT_DEFINE, false},
3587+ {"G16", WF_LWTBL_G16_MASK, NO_SHIFT_DEFINE, true},
3588+ {"G2_LTF", WF_LWTBL_G2_LTF_MASK, WF_LWTBL_G2_LTF_SHIFT, false},
3589+ {"G4_LTF", WF_LWTBL_G4_LTF_MASK, WF_LWTBL_G4_LTF_SHIFT, false},
3590+ {"G8_LTF", WF_LWTBL_G8_LTF_MASK, WF_LWTBL_G8_LTF_SHIFT, false},
3591+ {"G16_LTF", WF_LWTBL_G16_LTF_MASK, WF_LWTBL_G16_LTF_SHIFT, true},
3592+ {"G2_HE", WF_LWTBL_G2_HE_MASK, WF_LWTBL_G2_HE_SHIFT, false},
3593+ {"G4_HE", WF_LWTBL_G4_HE_MASK, WF_LWTBL_G4_HE_SHIFT, false},
3594+ {"G8_HE", WF_LWTBL_G8_HE_MASK, WF_LWTBL_G8_HE_SHIFT, false},
3595+ {"G16_HE", WF_LWTBL_G16_HE_MASK, WF_LWTBL_G16_HE_SHIFT, true},
3596+ {NULL,}
3597+};
3598+
3599+static void parse_fmac_lwtbl_dw6(struct seq_file *s, u8 *lwtbl)
3600+{
3601+ u32 *addr = 0;
3602+ u32 dw_value = 0;
3603+ u16 i = 0;
3604+
3605+ /* LMAC WTBL DW 6 */
3606+ seq_printf(s, "\t\n");
3607+ seq_printf(s, "LWTBL DW 6\n");
3608+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_6*4]);
3609+ dw_value = *addr;
3610+
3611+ while (WTBL_LMAC_DW6[i].name) {
3612+ if (WTBL_LMAC_DW6[i].shift == NO_SHIFT_DEFINE)
3613+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW6[i].name,
3614+ (dw_value & WTBL_LMAC_DW6[i].mask) ? 1 : 0);
3615+ else
3616+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW6[i].name,
3617+ (dw_value & WTBL_LMAC_DW6[i].mask) >> WTBL_LMAC_DW6[i].shift);
3618+ i++;
3619+ }
3620+}
3621+
3622+static void parse_fmac_lwtbl_dw7(struct seq_file *s, u8 *lwtbl)
3623+{
3624+ u32 *addr = 0;
3625+ u32 dw_value = 0;
3626+ int i = 0;
3627+
3628+ /* LMAC WTBL DW 7 */
3629+ seq_printf(s, "\t\n");
3630+ seq_printf(s, "LWTBL DW 7\n");
3631+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_7*4]);
3632+ dw_value = *addr;
3633+
3634+ for (i = 0; i < 8; i++) {
3635+ seq_printf(s, "\tBA_WIN_SIZE%u:%lu\n", i, ((dw_value & BITS(i*4, i*4+3)) >> i*4));
3636+ }
3637+}
3638+
3639+static const struct berse_wtbl_parse WTBL_LMAC_DW8[] = {
3640+ {"RTS_FAIL_CNT_AC0", WF_LWTBL_AC0_RTS_FAIL_CNT_MASK, WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT, false},
3641+ {"AC1", WF_LWTBL_AC1_RTS_FAIL_CNT_MASK, WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT, false},
3642+ {"AC2", WF_LWTBL_AC2_RTS_FAIL_CNT_MASK, WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT, false},
3643+ {"AC3", WF_LWTBL_AC3_RTS_FAIL_CNT_MASK, WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT, true},
3644+ {"PARTIAL_AID", WF_LWTBL_PARTIAL_AID_MASK, WF_LWTBL_PARTIAL_AID_SHIFT, false},
3645+ {"CHK_PER", WF_LWTBL_CHK_PER_MASK, NO_SHIFT_DEFINE, true},
3646+ {NULL,}
3647+};
3648+
3649+static void parse_fmac_lwtbl_dw8(struct seq_file *s, u8 *lwtbl)
3650+{
3651+ u32 *addr = 0;
3652+ u32 dw_value = 0;
3653+ u16 i = 0;
3654+
3655+ /* LMAC WTBL DW 8 */
3656+ seq_printf(s, "\t\n");
3657+ seq_printf(s, "LWTBL DW 8\n");
3658+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_8*4]);
3659+ dw_value = *addr;
3660+
3661+ while (WTBL_LMAC_DW8[i].name) {
3662+ if (WTBL_LMAC_DW8[i].shift == NO_SHIFT_DEFINE)
3663+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW8[i].name,
3664+ (dw_value & WTBL_LMAC_DW8[i].mask) ? 1 : 0);
3665+ else
3666+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW8[i].name,
3667+ (dw_value & WTBL_LMAC_DW8[i].mask) >> WTBL_LMAC_DW8[i].shift);
3668+ i++;
3669+ }
3670+}
3671+
3672+static const struct berse_wtbl_parse WTBL_LMAC_DW9[] = {
3673+ {"RX_AVG_MPDU_SIZE", WF_LWTBL_RX_AVG_MPDU_SIZE_MASK, WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT, false},
3674+ {"PRITX_SW_MODE", WF_LWTBL_PRITX_SW_MODE_MASK, NO_SHIFT_DEFINE, false},
3675+ {"PRITX_ERSU", WF_LWTBL_PRITX_ERSU_MASK, NO_SHIFT_DEFINE, false},
3676+ {"PRITX_PLR", WF_LWTBL_PRITX_PLR_MASK, NO_SHIFT_DEFINE, true},
3677+ {"PRITX_DCM", WF_LWTBL_PRITX_DCM_MASK, NO_SHIFT_DEFINE, false},
3678+ {"PRITX_ER106T", WF_LWTBL_PRITX_ER106T_MASK, NO_SHIFT_DEFINE, true},
3679+ /* {"FCAP(0:20 1:~40)", WTBL_FCAP_20_TO_160_MHZ, WTBL_FCAP_20_TO_160_MHZ_OFFSET}, */
3680+ {"MPDU_FAIL_CNT", WF_LWTBL_MPDU_FAIL_CNT_MASK, WF_LWTBL_MPDU_FAIL_CNT_SHIFT, false},
3681+ {"MPDU_OK_CNT", WF_LWTBL_MPDU_OK_CNT_MASK, WF_LWTBL_MPDU_OK_CNT_SHIFT, false},
3682+ {"RATE_IDX", WF_LWTBL_RATE_IDX_MASK, WF_LWTBL_RATE_IDX_SHIFT, true},
3683+ {NULL,}
3684+};
3685+
3686+char *fcap_name[] = {"20MHz", "20/40MHz", "20/40/80MHz", "20/40/80/160/80+80MHz", "20/40/80/160/80+80/320MHz"};
3687+
3688+static void parse_fmac_lwtbl_dw9(struct seq_file *s, u8 *lwtbl)
3689+{
3690+ u32 *addr = 0;
3691+ u32 dw_value = 0;
3692+ u16 i = 0;
3693+
3694+ /* LMAC WTBL DW 9 */
3695+ seq_printf(s, "\t\n");
3696+ seq_printf(s, "LWTBL DW 9\n");
3697+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_9*4]);
3698+ dw_value = *addr;
3699+
3700+ while (WTBL_LMAC_DW9[i].name) {
3701+ if (WTBL_LMAC_DW9[i].shift == NO_SHIFT_DEFINE)
3702+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW9[i].name,
3703+ (dw_value & WTBL_LMAC_DW9[i].mask) ? 1 : 0);
3704+ else
3705+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW9[i].name,
3706+ (dw_value & WTBL_LMAC_DW9[i].mask) >> WTBL_LMAC_DW9[i].shift);
3707+ i++;
3708+ }
3709+
3710+ /* FCAP parser */
3711+ seq_printf(s, "\t\n");
3712+ seq_printf(s, "FCAP:%s\n", fcap_name[(dw_value & WF_LWTBL_FCAP_MASK) >> WF_LWTBL_FCAP_SHIFT]);
3713+}
3714+
3715+#define HW_TX_RATE_TO_MODE(_x) (((_x) & WTBL_RATE_TX_MODE_MASK) >> WTBL_RATE_TX_MODE_OFFSET)
3716+#define HW_TX_RATE_TO_MCS(_x, _mode) ((_x) & WTBL_RATE_TX_RATE_MASK >> WTBL_RATE_TX_RATE_OFFSET)
3717+#define HW_TX_RATE_TO_NSS(_x) (((_x) & WTBL_RATE_NSTS_MASK) >> WTBL_RATE_NSTS_OFFSET)
3718+#define HW_TX_RATE_TO_STBC(_x) (((_x) & WTBL_RATE_STBC_MASK) >> WTBL_RATE_STBC_OFFSET)
3719+
3720+#define MAX_TX_MODE 16
3721+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
3722+ "N/A", "N/A", "N/A",
3723+ "HE_SU", "HE_EXT_SU", "HE_TRIG", "HE_MU",
3724+ "N/A",
3725+ "EHT_EXT_SU", "EHT_TRIG", "EHT_MU",
3726+ "N/A"};
3727+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong", "N/A", "2Mshort", "5.5Mshort", "11Mshort", "N/A"};
3728+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M", "N/A"};
3729+
3730+static char *hw_rate_ofdm_str(uint16_t ofdm_idx)
3731+{
3732+ switch (ofdm_idx) {
3733+ case 11: /* 6M */
3734+ return HW_TX_RATE_OFDM_STR[0];
3735+
3736+ case 15: /* 9M */
3737+ return HW_TX_RATE_OFDM_STR[1];
3738+
3739+ case 10: /* 12M */
3740+ return HW_TX_RATE_OFDM_STR[2];
3741+
3742+ case 14: /* 18M */
3743+ return HW_TX_RATE_OFDM_STR[3];
3744+
3745+ case 9: /* 24M */
3746+ return HW_TX_RATE_OFDM_STR[4];
3747+
3748+ case 13: /* 36M */
3749+ return HW_TX_RATE_OFDM_STR[5];
3750+
3751+ case 8: /* 48M */
3752+ return HW_TX_RATE_OFDM_STR[6];
3753+
3754+ case 12: /* 54M */
3755+ return HW_TX_RATE_OFDM_STR[7];
3756+
3757+ default:
3758+ return HW_TX_RATE_OFDM_STR[8];
3759+ }
3760+}
3761+
3762+static char *hw_rate_str(u8 mode, uint16_t rate_idx)
3763+{
3764+ if (mode == 0)
3765+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
3766+ else if (mode == 1)
3767+ return hw_rate_ofdm_str(rate_idx);
3768+ else
3769+ return "MCS";
3770+}
3771+
3772+static void
3773+parse_rate(struct seq_file *s, uint16_t rate_idx, uint16_t txrate)
3774+{
3775+ uint16_t txmode, mcs, nss, stbc;
3776+
3777+ txmode = HW_TX_RATE_TO_MODE(txrate);
3778+ mcs = HW_TX_RATE_TO_MCS(txrate, txmode);
3779+ nss = HW_TX_RATE_TO_NSS(txrate);
3780+ stbc = HW_TX_RATE_TO_STBC(txrate);
3781+
3782+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
3783+ rate_idx + 1, txrate,
3784+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
3785+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
3786+}
3787+
3788+
3789+static const struct berse_wtbl_parse WTBL_LMAC_DW10[] = {
3790+ {"RATE1", WF_LWTBL_RATE1_MASK, WF_LWTBL_RATE1_SHIFT},
3791+ {"RATE2", WF_LWTBL_RATE2_MASK, WF_LWTBL_RATE2_SHIFT},
3792+ {NULL,}
3793+};
3794+
3795+static void parse_fmac_lwtbl_dw10(struct seq_file *s, u8 *lwtbl)
3796+{
3797+ u32 *addr = 0;
3798+ u32 dw_value = 0;
3799+ u16 i = 0;
3800+
3801+ /* LMAC WTBL DW 10 */
3802+ seq_printf(s, "\t\n");
3803+ seq_printf(s, "LWTBL DW 10\n");
3804+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_1_2*4]);
3805+ dw_value = *addr;
3806+
3807+ while (WTBL_LMAC_DW10[i].name) {
3808+ parse_rate(s, i, (dw_value & WTBL_LMAC_DW10[i].mask) >> WTBL_LMAC_DW10[i].shift);
3809+ i++;
3810+ }
3811+}
3812+
3813+static const struct berse_wtbl_parse WTBL_LMAC_DW11[] = {
3814+ {"RATE3", WF_LWTBL_RATE3_MASK, WF_LWTBL_RATE3_SHIFT},
3815+ {"RATE4", WF_LWTBL_RATE4_MASK, WF_LWTBL_RATE4_SHIFT},
3816+ {NULL,}
3817+};
3818+
3819+static void parse_fmac_lwtbl_dw11(struct seq_file *s, u8 *lwtbl)
3820+{
3821+ u32 *addr = 0;
3822+ u32 dw_value = 0;
3823+ u16 i = 0;
3824+
3825+ /* LMAC WTBL DW 11 */
3826+ seq_printf(s, "\t\n");
3827+ seq_printf(s, "LWTBL DW 11\n");
3828+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_3_4*4]);
3829+ dw_value = *addr;
3830+
3831+ while (WTBL_LMAC_DW11[i].name) {
3832+ parse_rate(s, i+2, (dw_value & WTBL_LMAC_DW11[i].mask) >> WTBL_LMAC_DW11[i].shift);
3833+ i++;
3834+ }
3835+}
3836+
3837+static const struct berse_wtbl_parse WTBL_LMAC_DW12[] = {
3838+ {"RATE5", WF_LWTBL_RATE5_MASK, WF_LWTBL_RATE5_SHIFT},
3839+ {"RATE6", WF_LWTBL_RATE6_MASK, WF_LWTBL_RATE6_SHIFT},
3840+ {NULL,}
3841+};
3842+
3843+static void parse_fmac_lwtbl_dw12(struct seq_file *s, u8 *lwtbl)
3844+{
3845+ u32 *addr = 0;
3846+ u32 dw_value = 0;
3847+ u16 i = 0;
3848+
3849+ /* LMAC WTBL DW 12 */
3850+ seq_printf(s, "\t\n");
3851+ seq_printf(s, "LWTBL DW 12\n");
3852+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_5_6*4]);
3853+ dw_value = *addr;
3854+
3855+ while (WTBL_LMAC_DW12[i].name) {
3856+ parse_rate(s, i+4, (dw_value & WTBL_LMAC_DW12[i].mask) >> WTBL_LMAC_DW12[i].shift);
3857+ i++;
3858+ }
3859+}
3860+
3861+static const struct berse_wtbl_parse WTBL_LMAC_DW13[] = {
3862+ {"RATE7", WF_LWTBL_RATE7_MASK, WF_LWTBL_RATE7_SHIFT},
3863+ {"RATE8", WF_LWTBL_RATE8_MASK, WF_LWTBL_RATE8_SHIFT},
3864+ {NULL,}
3865+};
3866+
3867+static void parse_fmac_lwtbl_dw13(struct seq_file *s, u8 *lwtbl)
3868+{
3869+ u32 *addr = 0;
3870+ u32 dw_value = 0;
3871+ u16 i = 0;
3872+
3873+ /* LMAC WTBL DW 13 */
3874+ seq_printf(s, "\t\n");
3875+ seq_printf(s, "LWTBL DW 13\n");
3876+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_7_8*4]);
3877+ dw_value = *addr;
3878+
3879+ while (WTBL_LMAC_DW13[i].name) {
3880+ parse_rate(s, i+6, (dw_value & WTBL_LMAC_DW13[i].mask) >> WTBL_LMAC_DW13[i].shift);
3881+ i++;
3882+ }
3883+}
3884+
3885+static const struct berse_wtbl_parse WTBL_LMAC_DW14_BMC[] = {
3886+ {"CIPHER_IGTK", WF_LWTBL_CIPHER_SUIT_IGTK_MASK, WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT, false},
3887+ {"CIPHER_BIGTK", WF_LWTBL_CIPHER_SUIT_BIGTK_MASK, WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT, true},
3888+ {NULL,}
3889+};
3890+
3891+static void parse_fmac_lwtbl_dw14(struct seq_file *s, u8 *lwtbl)
3892+{
3893+ u32 *addr, *muar_addr = 0;
3894+ u32 dw_value, muar_dw_value = 0;
3895+ u16 i = 0;
3896+
3897+ /* DUMP DW14 for BMC entry only */
3898+ muar_addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]);
3899+ muar_dw_value = *muar_addr;
3900+ if (((muar_dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT)
3901+ == MUAR_INDEX_OWN_MAC_ADDR_BC_MC) {
3902+ /* LMAC WTBL DW 14 */
3903+ seq_printf(s, "\t\n");
3904+ seq_printf(s, "LWTBL DW 14\n");
3905+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_IGTK_DW*4]);
3906+ dw_value = *addr;
3907+
3908+ while (WTBL_LMAC_DW14_BMC[i].name) {
3909+ parse_rate(s, i+6, (dw_value & WTBL_LMAC_DW14_BMC[i].mask) >> WTBL_LMAC_DW14_BMC[i].shift);
3910+ i++;
3911+ }
3912+ }
3913+}
3914+
3915+static const struct berse_wtbl_parse WTBL_LMAC_DW28[] = {
3916+ {"RELATED_IDX0", WF_LWTBL_RELATED_IDX0_MASK, WF_LWTBL_RELATED_IDX0_SHIFT, false},
3917+ {"RELATED_BAND0", WF_LWTBL_RELATED_BAND0_MASK, WF_LWTBL_RELATED_BAND0_SHIFT, false},
3918+ {"PRI_MLD_BAND", WF_LWTBL_PRIMARY_MLD_BAND_MASK, WF_LWTBL_PRIMARY_MLD_BAND_SHIFT, true},
3919+ {"RELATED_IDX0", WF_LWTBL_RELATED_IDX1_MASK, WF_LWTBL_RELATED_IDX1_SHIFT, false},
3920+ {"RELATED_BAND1", WF_LWTBL_RELATED_BAND1_MASK, WF_LWTBL_RELATED_BAND1_SHIFT, false},
3921+ {"SEC_MLD_BAND", WF_LWTBL_SECONDARY_MLD_BAND_MASK, WF_LWTBL_SECONDARY_MLD_BAND_SHIFT, true},
3922+ {NULL,}
3923+};
3924+
3925+static void parse_fmac_lwtbl_dw28(struct seq_file *s, u8 *lwtbl)
3926+{
3927+ u32 *addr = 0;
3928+ u32 dw_value = 0;
3929+ u16 i = 0;
3930+
3931+ /* LMAC WTBL DW 28 */
3932+ seq_printf(s, "\t\n");
3933+ seq_printf(s, "LWTBL DW 28\n");
3934+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_1*4]);
3935+ dw_value = *addr;
3936+
3937+ while (WTBL_LMAC_DW28[i].name) {
3938+ if (WTBL_LMAC_DW28[i].shift == NO_SHIFT_DEFINE)
3939+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW28[i].name,
3940+ (dw_value & WTBL_LMAC_DW28[i].mask) ? 1 : 0);
3941+ else
3942+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW28[i].name,
3943+ (dw_value & WTBL_LMAC_DW28[i].mask) >>
3944+ WTBL_LMAC_DW28[i].shift);
3945+ i++;
3946+ }
3947+}
3948+
3949+static const struct berse_wtbl_parse WTBL_LMAC_DW29[] = {
3950+ {"DISPATCH_POLICY_MLD_TID0", WF_LWTBL_DISPATCH_POLICY0_MASK, WF_LWTBL_DISPATCH_POLICY0_SHIFT, false},
3951+ {"MLD_TID1", WF_LWTBL_DISPATCH_POLICY1_MASK, WF_LWTBL_DISPATCH_POLICY1_SHIFT, false},
3952+ {"MLD_TID2", WF_LWTBL_DISPATCH_POLICY2_MASK, WF_LWTBL_DISPATCH_POLICY2_SHIFT, false},
3953+ {"MLD_TID3", WF_LWTBL_DISPATCH_POLICY3_MASK, WF_LWTBL_DISPATCH_POLICY3_SHIFT, true},
3954+ {"MLD_TID4", WF_LWTBL_DISPATCH_POLICY4_MASK, WF_LWTBL_DISPATCH_POLICY4_SHIFT, false},
3955+ {"MLD_TID5", WF_LWTBL_DISPATCH_POLICY5_MASK, WF_LWTBL_DISPATCH_POLICY5_SHIFT, false},
3956+ {"MLD_TID6", WF_LWTBL_DISPATCH_POLICY6_MASK, WF_LWTBL_DISPATCH_POLICY6_SHIFT, false},
3957+ {"MLD_TID7", WF_LWTBL_DISPATCH_POLICY7_MASK, WF_LWTBL_DISPATCH_POLICY7_SHIFT, true},
3958+ {"OMLD_ID", WF_LWTBL_OWN_MLD_ID_MASK, WF_LWTBL_OWN_MLD_ID_SHIFT, false},
3959+ {"EMLSR0", WF_LWTBL_EMLSR0_MASK, NO_SHIFT_DEFINE, false},
3960+ {"EMLMR0", WF_LWTBL_EMLMR0_MASK, NO_SHIFT_DEFINE, false},
3961+ {"EMLSR1", WF_LWTBL_EMLSR1_MASK, NO_SHIFT_DEFINE, false},
3962+ {"EMLMR1", WF_LWTBL_EMLMR1_MASK, NO_SHIFT_DEFINE, true},
3963+ {"EMLSR2", WF_LWTBL_EMLSR2_MASK, NO_SHIFT_DEFINE, false},
3964+ {"EMLMR2", WF_LWTBL_EMLMR2_MASK, NO_SHIFT_DEFINE, false},
3965+ {"STR_BITMAP", WF_LWTBL_STR_BITMAP_MASK, WF_LWTBL_STR_BITMAP_SHIFT, true},
3966+ {NULL,}
3967+};
3968+
3969+static void parse_fmac_lwtbl_dw29(struct seq_file *s, u8 *lwtbl)
3970+{
3971+ u32 *addr = 0;
3972+ u32 dw_value = 0;
3973+ u16 i = 0;
3974+
3975+ /* LMAC WTBL DW 29 */
3976+ seq_printf(s, "\t\n");
3977+ seq_printf(s, "LWTBL DW 29\n");
3978+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_2*4]);
3979+ dw_value = *addr;
3980+
3981+ while (WTBL_LMAC_DW29[i].name) {
3982+ if (WTBL_LMAC_DW29[i].shift == NO_SHIFT_DEFINE)
3983+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW29[i].name,
3984+ (dw_value & WTBL_LMAC_DW29[i].mask) ? 1 : 0);
3985+ else
3986+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW29[i].name,
3987+ (dw_value & WTBL_LMAC_DW29[i].mask) >>
3988+ WTBL_LMAC_DW29[i].shift);
3989+ i++;
3990+ }
3991+}
3992+
3993+static const struct berse_wtbl_parse WTBL_LMAC_DW30[] = {
3994+ {"DISPATCH_ORDER", WF_LWTBL_DISPATCH_ORDER_MASK, WF_LWTBL_DISPATCH_ORDER_SHIFT, false},
3995+ {"DISPATCH_RATIO", WF_LWTBL_DISPATCH_RATIO_MASK, WF_LWTBL_DISPATCH_RATIO_SHIFT, false},
3996+ {"LINK_MGF", WF_LWTBL_LINK_MGF_MASK, WF_LWTBL_LINK_MGF_SHIFT, true},
3997+ {NULL,}
3998+};
3999+
4000+static void parse_fmac_lwtbl_dw30(struct seq_file *s, u8 *lwtbl)
4001+{
4002+ u32 *addr = 0;
4003+ u32 dw_value = 0;
4004+ u16 i = 0;
4005+
4006+ /* LMAC WTBL DW 30 */
4007+ seq_printf(s, "\t\n");
4008+ seq_printf(s, "LWTBL DW 30\n");
4009+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_3*4]);
4010+ dw_value = *addr;
4011+
4012+
4013+ while (WTBL_LMAC_DW30[i].name) {
4014+ if (WTBL_LMAC_DW30[i].shift == NO_SHIFT_DEFINE)
4015+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW30[i].name,
4016+ (dw_value & WTBL_LMAC_DW30[i].mask) ? 1 : 0);
4017+ else
4018+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW30[i].name,
4019+ (dw_value & WTBL_LMAC_DW30[i].mask) >> WTBL_LMAC_DW30[i].shift);
4020+ i++;
4021+ }
4022+}
4023+
4024+static const struct berse_wtbl_parse WTBL_LMAC_DW31[] = {
4025+ {"NEGO_WINSIZE0", WF_LWTBL_NEGOTIATED_WINSIZE0_MASK, WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT, false},
4026+ {"WINSIZE1", WF_LWTBL_NEGOTIATED_WINSIZE1_MASK, WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT, false},
4027+ {"WINSIZE2", WF_LWTBL_NEGOTIATED_WINSIZE2_MASK, WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT, false},
4028+ {"WINSIZE3", WF_LWTBL_NEGOTIATED_WINSIZE3_MASK, WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT, true},
4029+ {"WINSIZE4", WF_LWTBL_NEGOTIATED_WINSIZE4_MASK, WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT, false},
4030+ {"WINSIZE5", WF_LWTBL_NEGOTIATED_WINSIZE5_MASK, WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT, false},
4031+ {"WINSIZE6", WF_LWTBL_NEGOTIATED_WINSIZE6_MASK, WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT, false},
4032+ {"WINSIZE7", WF_LWTBL_NEGOTIATED_WINSIZE7_MASK, WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT, true},
4033+ {"CASCAD", WF_LWTBL_CASCAD_MASK, NO_SHIFT_DEFINE, false},
4034+ {"ALL_ACK", WF_LWTBL_ALL_ACK_MASK, NO_SHIFT_DEFINE, false},
4035+ {"MPDU_SIZE", WF_LWTBL_MPDU_SIZE_MASK, WF_LWTBL_MPDU_SIZE_SHIFT, false},
4036+ {"BA_MODE", WF_LWTBL_BA_MODE_MASK, WF_LWTBL_BA_MODE_SHIFT, true},
4037+ {NULL,}
4038+};
4039+
4040+static void parse_fmac_lwtbl_dw31(struct seq_file *s, u8 *lwtbl)
4041+{
4042+ u32 *addr = 0;
4043+ u32 dw_value = 0;
4044+ u16 i = 0;
4045+
4046+ /* LMAC WTBL DW 31 */
4047+ seq_printf(s, "\t\n");
4048+ seq_printf(s, "LWTBL DW 31\n");
4049+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RESP_INFO_DW_31*4]);
4050+ dw_value = *addr;
4051+
4052+ while (WTBL_LMAC_DW31[i].name) {
4053+ if (WTBL_LMAC_DW31[i].shift == NO_SHIFT_DEFINE)
4054+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW31[i].name,
4055+ (dw_value & WTBL_LMAC_DW31[i].mask) ? 1 : 0);
4056+ else
4057+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW31[i].name,
4058+ (dw_value & WTBL_LMAC_DW31[i].mask) >>
4059+ WTBL_LMAC_DW31[i].shift);
4060+ i++;
4061+ }
4062+}
4063+
4064+static const struct berse_wtbl_parse WTBL_LMAC_DW32[] = {
4065+ {"OM_INFO", WF_LWTBL_OM_INFO_MASK, WF_LWTBL_OM_INFO_SHIFT, false},
4066+ {"OM_RXD_DUP_MODE", WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK, NO_SHIFT_DEFINE, false},
4067+ {"RXD_DUP_WHITE_LIST", WF_LWTBL_RXD_DUP_WHITE_LIST_MASK, WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT, false},
4068+ {"RXD_DUP_MODE", WF_LWTBL_RXD_DUP_MODE_MASK, WF_LWTBL_RXD_DUP_MODE_SHIFT, false},
4069+ {"DROP", WF_LWTBL_DROP_MASK, NO_SHIFT_DEFINE, false},
4070+ {"ACK_EN", WF_LWTBL_ACK_EN_MASK, NO_SHIFT_DEFINE, true},
4071+ {NULL,}
4072+};
4073+
4074+static void parse_fmac_lwtbl_dw32(struct seq_file *s, u8 *lwtbl)
4075+{
4076+ u32 *addr = 0;
4077+ u32 dw_value = 0;
4078+ u16 i = 0;
4079+
4080+ /* LMAC WTBL DW 32 */
4081+ seq_printf(s, "\t\n");
4082+ seq_printf(s, "LWTBL DW 32\n");
4083+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_DUP_INFO_DW_32*4]);
4084+ dw_value = *addr;
4085+
4086+ while (WTBL_LMAC_DW32[i].name) {
4087+ if (WTBL_LMAC_DW32[i].shift == NO_SHIFT_DEFINE)
4088+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW32[i].name,
4089+ (dw_value & WTBL_LMAC_DW32[i].mask) ? 1 : 0);
4090+ else
4091+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW32[i].name,
4092+ (dw_value & WTBL_LMAC_DW32[i].mask) >>
4093+ WTBL_LMAC_DW32[i].shift);
4094+ i++;
4095+ }
4096+}
4097+
4098+static const struct berse_wtbl_parse WTBL_LMAC_DW33[] = {
4099+ {"USER_RSSI", WF_LWTBL_USER_RSSI_MASK, WF_LWTBL_USER_RSSI_SHIFT, false},
4100+ {"USER_SNR", WF_LWTBL_USER_SNR_MASK, WF_LWTBL_USER_SNR_SHIFT, false},
4101+ {"RAPID_REACTION_RATE", WF_LWTBL_RAPID_REACTION_RATE_MASK, WF_LWTBL_RAPID_REACTION_RATE_SHIFT, true},
4102+ {"HT_AMSDU(Read Only)", WF_LWTBL_HT_AMSDU_MASK, NO_SHIFT_DEFINE, false},
4103+ {"AMSDU_CROSS_LG(Read Only)", WF_LWTBL_AMSDU_CROSS_LG_MASK, NO_SHIFT_DEFINE, true},
4104+ {NULL,}
4105+};
4106+
4107+static void parse_fmac_lwtbl_dw33(struct seq_file *s, u8 *lwtbl)
4108+{
4109+ u32 *addr = 0;
4110+ u32 dw_value = 0;
4111+ u16 i = 0;
4112+
4113+ /* LMAC WTBL DW 33 */
4114+ seq_printf(s, "\t\n");
4115+ seq_printf(s, "LWTBL DW 33\n");
4116+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_1*4]);
4117+ dw_value = *addr;
4118+
4119+ while (WTBL_LMAC_DW33[i].name) {
4120+ if (WTBL_LMAC_DW33[i].shift == NO_SHIFT_DEFINE)
4121+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW33[i].name,
4122+ (dw_value & WTBL_LMAC_DW33[i].mask) ? 1 : 0);
4123+ else
4124+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW33[i].name,
4125+ (dw_value & WTBL_LMAC_DW33[i].mask) >>
4126+ WTBL_LMAC_DW33[i].shift);
4127+ i++;
4128+ }
4129+}
4130+
4131+static const struct berse_wtbl_parse WTBL_LMAC_DW34[] = {
4132+ {"RESP_RCPI0", WF_LWTBL_RESP_RCPI0_MASK, WF_LWTBL_RESP_RCPI0_SHIFT, false},
4133+ {"RCPI1", WF_LWTBL_RESP_RCPI1_MASK, WF_LWTBL_RESP_RCPI1_SHIFT, false},
4134+ {"RCPI2", WF_LWTBL_RESP_RCPI2_MASK, WF_LWTBL_RESP_RCPI2_SHIFT, false},
4135+ {"RCPI3", WF_LWTBL_RESP_RCPI3_MASK, WF_LWTBL_RESP_RCPI3_SHIFT, true},
4136+ {NULL,}
4137+};
4138+
4139+static void parse_fmac_lwtbl_dw34(struct seq_file *s, u8 *lwtbl)
4140+{
4141+ u32 *addr = 0;
4142+ u32 dw_value = 0;
4143+ u16 i = 0;
4144+
4145+ /* LMAC WTBL DW 34 */
4146+ seq_printf(s, "\t\n");
4147+ seq_printf(s, "LWTBL DW 34\n");
4148+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_2*4]);
4149+ dw_value = *addr;
4150+
4151+
4152+ while (WTBL_LMAC_DW34[i].name) {
4153+ if (WTBL_LMAC_DW34[i].shift == NO_SHIFT_DEFINE)
4154+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW34[i].name,
4155+ (dw_value & WTBL_LMAC_DW34[i].mask) ? 1 : 0);
4156+ else
4157+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW34[i].name,
4158+ (dw_value & WTBL_LMAC_DW34[i].mask) >>
4159+ WTBL_LMAC_DW34[i].shift);
4160+ i++;
4161+ }
4162+}
4163+
4164+static const struct berse_wtbl_parse WTBL_LMAC_DW35[] = {
4165+ {"SNR 0", WF_LWTBL_SNR_RX0_MASK, WF_LWTBL_SNR_RX0_SHIFT, false},
4166+ {"SNR 1", WF_LWTBL_SNR_RX1_MASK, WF_LWTBL_SNR_RX1_SHIFT, false},
4167+ {"SNR 2", WF_LWTBL_SNR_RX2_MASK, WF_LWTBL_SNR_RX2_SHIFT, false},
4168+ {"SNR 3", WF_LWTBL_SNR_RX3_MASK, WF_LWTBL_SNR_RX3_SHIFT, true},
4169+ {NULL,}
4170+};
4171+
4172+static void parse_fmac_lwtbl_dw35(struct seq_file *s, u8 *lwtbl)
4173+{
4174+ u32 *addr = 0;
4175+ u32 dw_value = 0;
4176+ u16 i = 0;
4177+
4178+ /* LMAC WTBL DW 35 */
4179+ seq_printf(s, "\t\n");
4180+ seq_printf(s, "LWTBL DW 35\n");
4181+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_3*4]);
4182+ dw_value = *addr;
4183+
4184+
4185+ while (WTBL_LMAC_DW35[i].name) {
4186+ if (WTBL_LMAC_DW35[i].shift == NO_SHIFT_DEFINE)
4187+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW35[i].name,
4188+ (dw_value & WTBL_LMAC_DW35[i].mask) ? 1 : 0);
4189+ else
4190+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW35[i].name,
4191+ (dw_value & WTBL_LMAC_DW35[i].mask) >>
4192+ WTBL_LMAC_DW35[i].shift);
4193+ i++;
4194+ }
4195+}
4196+
4197+static void parse_fmac_lwtbl_rx_stats(struct seq_file *s, u8 *lwtbl)
4198+{
4199+ parse_fmac_lwtbl_dw33(s, lwtbl);
4200+ parse_fmac_lwtbl_dw34(s, lwtbl);
4201+ parse_fmac_lwtbl_dw35(s, lwtbl);
4202+}
4203+
4204+static void parse_fmac_lwtbl_mlo_info(struct seq_file *s, u8 *lwtbl)
4205+{
4206+ parse_fmac_lwtbl_dw28(s, lwtbl);
4207+ parse_fmac_lwtbl_dw29(s, lwtbl);
4208+ parse_fmac_lwtbl_dw30(s, lwtbl);
4209+}
4210+
4211+static const struct berse_wtbl_parse WTBL_UMAC_DW9[] = {
4212+ {"RELATED_IDX0", WF_UWTBL_RELATED_IDX0_MASK, WF_UWTBL_RELATED_IDX0_SHIFT, false},
4213+ {"RELATED_BAND0", WF_UWTBL_RELATED_BAND0_MASK, WF_UWTBL_RELATED_BAND0_SHIFT, false},
4214+ {"PRI_MLD_BAND", WF_UWTBL_PRIMARY_MLD_BAND_MASK, WF_UWTBL_PRIMARY_MLD_BAND_SHIFT, true},
4215+ {"RELATED_IDX0", WF_UWTBL_RELATED_IDX1_MASK, WF_UWTBL_RELATED_IDX1_SHIFT, false},
4216+ {"RELATED_BAND1", WF_UWTBL_RELATED_BAND1_MASK, WF_UWTBL_RELATED_BAND1_SHIFT, false},
4217+ {"SEC_MLD_BAND", WF_UWTBL_SECONDARY_MLD_BAND_MASK, WF_UWTBL_SECONDARY_MLD_BAND_SHIFT, true},
4218+ {NULL,}
4219+};
4220+
4221+static void parse_fmac_uwtbl_mlo_info(struct seq_file *s, u8 *uwtbl)
4222+{
4223+ u32 *addr = 0;
4224+ u32 dw_value = 0;
4225+ u16 i = 0;
4226+
4227+ seq_printf(s, "\t\n");
4228+ seq_printf(s, "MldAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
4229+ uwtbl[4], uwtbl[5], uwtbl[6], uwtbl[7], uwtbl[0], uwtbl[1]);
4230+
4231+ /* UMAC WTBL DW 0 */
4232+ seq_printf(s, "\t\n");
4233+ seq_printf(s, "UWTBL DW 0\n");
4234+ addr = (u32 *)&(uwtbl[WF_UWTBL_OWN_MLD_ID_DW*4]);
4235+ dw_value = *addr;
4236+
4237+ seq_printf(s, "\t%s:%u\n", "OMLD_ID",
4238+ (dw_value & WF_UWTBL_OWN_MLD_ID_MASK) >> WF_UWTBL_OWN_MLD_ID_SHIFT);
4239+
4240+ /* UMAC WTBL DW 9 */
4241+ seq_printf(s, "\t\n");
4242+ seq_printf(s, "UWTBL DW 9\n");
4243+ addr = (u32 *)&(uwtbl[WF_UWTBL_RELATED_IDX0_DW*4]);
4244+ dw_value = *addr;
4245+
4246+ while (WTBL_UMAC_DW9[i].name) {
4247+
4248+ if (WTBL_UMAC_DW9[i].shift == NO_SHIFT_DEFINE)
4249+ seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW9[i].name,
4250+ (dw_value & WTBL_UMAC_DW9[i].mask) ? 1 : 0);
4251+ else
4252+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW9[i].name,
4253+ (dw_value & WTBL_UMAC_DW9[i].mask) >>
4254+ WTBL_UMAC_DW9[i].shift);
4255+ i++;
4256+ }
4257+}
4258+
4259+static bool
4260+is_wtbl_bigtk_exist(u8 *lwtbl)
4261+{
4262+ u32 *addr = 0;
4263+ u32 dw_value = 0;
4264+
4265+ addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]);
4266+ dw_value = *addr;
4267+ if (((dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT) ==
4268+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC) {
4269+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_BIGTK_DW*4]);
4270+ dw_value = *addr;
4271+ if (((dw_value & WF_LWTBL_CIPHER_SUIT_BIGTK_MASK) >>
4272+ WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT) != IGTK_CIPHER_SUIT_NONE)
4273+ return true;
4274+ }
4275+
4276+ return false;
4277+}
4278+
4279+static const struct berse_wtbl_parse WTBL_UMAC_DW2[] = {
4280+ {"PN0", WTBL_PN0_MASK, WTBL_PN0_OFFSET, false},
4281+ {"PN1", WTBL_PN1_MASK, WTBL_PN1_OFFSET, false},
4282+ {"PN2", WTBL_PN2_MASK, WTBL_PN2_OFFSET, true},
4283+ {"PN3", WTBL_PN3_MASK, WTBL_PN3_OFFSET, false},
4284+ {NULL,}
4285+};
4286+
4287+static const struct berse_wtbl_parse WTBL_UMAC_DW3[] = {
4288+ {"PN4", WTBL_PN4_MASK, WTBL_PN4_OFFSET, false},
4289+ {"PN5", WTBL_PN5_MASK, WTBL_PN5_OFFSET, true},
4290+ {NULL,}
4291+};
4292+
4293+static const struct berse_wtbl_parse WTBL_UMAC_DW4_BIPN[] = {
4294+ {"BIPN0", WTBL_BIPN0_MASK, WTBL_BIPN0_OFFSET, false},
4295+ {"BIPN1", WTBL_BIPN1_MASK, WTBL_BIPN1_OFFSET, false},
4296+ {"BIPN2", WTBL_BIPN2_MASK, WTBL_BIPN2_OFFSET, true},
4297+ {"BIPN3", WTBL_BIPN3_MASK, WTBL_BIPN3_OFFSET, false},
4298+ {NULL,}
4299+};
4300+
4301+static const struct berse_wtbl_parse WTBL_UMAC_DW5_BIPN[] = {
4302+ {"BIPN4", WTBL_BIPN0_MASK, WTBL_BIPN0_OFFSET, false},
4303+ {"BIPN5", WTBL_BIPN1_MASK, WTBL_BIPN1_OFFSET, true},
4304+ {NULL,}
4305+};
4306+
4307+static void parse_fmac_uwtbl_pn(struct seq_file *s, u8 *uwtbl, u8 *lwtbl)
4308+{
4309+ u32 *addr = 0;
4310+ u32 dw_value = 0;
4311+ u16 i = 0;
4312+
4313+ seq_printf(s, "\t\n");
4314+ seq_printf(s, "UWTBL PN\n");
4315+
4316+ /* UMAC WTBL DW 2/3 */
4317+ addr = (u32 *)&(uwtbl[WF_UWTBL_PN_31_0__DW*4]);
4318+ dw_value = *addr;
4319+
4320+ while (WTBL_UMAC_DW2[i].name) {
4321+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW2[i].name,
4322+ (dw_value & WTBL_UMAC_DW2[i].mask) >>
4323+ WTBL_UMAC_DW2[i].shift);
4324+ i++;
4325+ }
4326+
4327+ i = 0;
4328+ addr = (u32 *)&(uwtbl[WF_UWTBL_PN_47_32__DW*4]);
4329+ dw_value = *addr;
4330+
4331+ while (WTBL_UMAC_DW3[i].name) {
4332+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW3[i].name,
4333+ (dw_value & WTBL_UMAC_DW3[i].mask) >>
4334+ WTBL_UMAC_DW3[i].shift);
4335+ i++;
4336+ }
4337+
4338+
4339+ /* UMAC WTBL DW 4/5 for BIGTK */
4340+ if (is_wtbl_bigtk_exist(lwtbl) == true) {
4341+ i = 0;
4342+ addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_31_0__DW*4]);
4343+ dw_value = *addr;
4344+
4345+ while (WTBL_UMAC_DW4_BIPN[i].name) {
4346+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW4_BIPN[i].name,
4347+ (dw_value & WTBL_UMAC_DW4_BIPN[i].mask) >>
4348+ WTBL_UMAC_DW4_BIPN[i].shift);
4349+ i++;
4350+ }
4351+
4352+ i = 0;
4353+ addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_47_32__DW*4]);
4354+ dw_value = *addr;
4355+
4356+ while (WTBL_UMAC_DW5_BIPN[i].name) {
4357+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW5_BIPN[i].name,
4358+ (dw_value & WTBL_UMAC_DW5_BIPN[i].mask) >>
4359+ WTBL_UMAC_DW5_BIPN[i].shift);
4360+ i++;
4361+ }
4362+ }
4363+}
4364+
4365+static void parse_fmac_uwtbl_sn(struct seq_file *s, u8 *uwtbl)
4366+{
4367+ u32 *addr = 0;
4368+ u32 u2SN = 0;
4369+
4370+ /* UMAC WTBL DW SN part */
4371+ seq_printf(s, "\t\n");
4372+ seq_printf(s, "UWTBL SN\n");
4373+
4374+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID0_SN_DW*4]);
4375+ u2SN = ((*addr) & WF_UWTBL_TID0_SN_MASK) >> WF_UWTBL_TID0_SN_SHIFT;
4376+ seq_printf(s, "\t%s:%u\n", "TID0_AC0_SN", u2SN);
4377+
4378+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID1_SN_DW*4]);
4379+ u2SN = ((*addr) & WF_UWTBL_TID1_SN_MASK) >> WF_UWTBL_TID1_SN_SHIFT;
4380+ seq_printf(s, "\t%s:%u\n", "TID1_AC1_SN", u2SN);
4381+
4382+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_7_0__DW*4]);
4383+ u2SN = ((*addr) & WF_UWTBL_TID2_SN_7_0__MASK) >>
4384+ WF_UWTBL_TID2_SN_7_0__SHIFT;
4385+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_11_8__DW*4]);
4386+ u2SN |= (((*addr) & WF_UWTBL_TID2_SN_11_8__MASK) >>
4387+ WF_UWTBL_TID2_SN_11_8__SHIFT) << 8;
4388+ seq_printf(s, "\t%s:%u\n", "TID2_AC2_SN", u2SN);
4389+
4390+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID3_SN_DW*4]);
4391+ u2SN = ((*addr) & WF_UWTBL_TID3_SN_MASK) >> WF_UWTBL_TID3_SN_SHIFT;
4392+ seq_printf(s, "\t%s:%u\n", "TID3_AC3_SN", u2SN);
4393+
4394+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID4_SN_DW*4]);
4395+ u2SN = ((*addr) & WF_UWTBL_TID4_SN_MASK) >> WF_UWTBL_TID4_SN_SHIFT;
4396+ seq_printf(s, "\t%s:%u\n", "TID4_SN", u2SN);
4397+
4398+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_3_0__DW*4]);
4399+ u2SN = ((*addr) & WF_UWTBL_TID5_SN_3_0__MASK) >>
4400+ WF_UWTBL_TID5_SN_3_0__SHIFT;
4401+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_11_4__DW*4]);
4402+ u2SN |= (((*addr) & WF_UWTBL_TID5_SN_11_4__MASK) >>
4403+ WF_UWTBL_TID5_SN_11_4__SHIFT) << 4;
4404+ seq_printf(s, "\t%s:%u\n", "TID5_SN", u2SN);
4405+
4406+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID6_SN_DW*4]);
4407+ u2SN = ((*addr) & WF_UWTBL_TID6_SN_MASK) >> WF_UWTBL_TID6_SN_SHIFT;
4408+ seq_printf(s, "\t%s:%u\n", "TID6_SN", u2SN);
4409+
4410+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID7_SN_DW*4]);
4411+ u2SN = ((*addr) & WF_UWTBL_TID7_SN_MASK) >> WF_UWTBL_TID7_SN_SHIFT;
4412+ seq_printf(s, "\t%s:%u\n", "TID7_SN", u2SN);
4413+
4414+ addr = (u32 *)&(uwtbl[WF_UWTBL_COM_SN_DW*4]);
4415+ u2SN = ((*addr) & WF_UWTBL_COM_SN_MASK) >> WF_UWTBL_COM_SN_SHIFT;
4416+ seq_printf(s, "\t%s:%u\n", "COM_SN", u2SN);
4417+}
4418+
4419+static void dump_key_table(
4420+ struct seq_file *s,
4421+ uint16_t keyloc0,
4422+ uint16_t keyloc1,
4423+ uint16_t keyloc2
4424+)
4425+{
4426+#define ONE_KEY_ENTRY_LEN_IN_DW 8
4427+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4428+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
4429+ uint16_t x;
4430+
4431+ seq_printf(s, "\t\n");
4432+ seq_printf(s, "\t%s:%d\n", "keyloc0", keyloc0);
4433+ if (keyloc0 != INVALID_KEY_ENTRY) {
4434+
4435+ /* Don't swap below two lines, halWtblReadRaw will
4436+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4437+ */
4438+ mt7996_wtbl_read_raw(dev, keyloc0,
4439+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4440+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4441+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4442+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4443+ KEYTBL_IDX2BASE(keyloc0, 0));
4444+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4445+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4446+ x,
4447+ keytbl[x * 4 + 3],
4448+ keytbl[x * 4 + 2],
4449+ keytbl[x * 4 + 1],
4450+ keytbl[x * 4]);
4451+ }
4452+ }
4453+
4454+ seq_printf(s, "\t%s:%d\n", "keyloc1", keyloc1);
4455+ if (keyloc1 != INVALID_KEY_ENTRY) {
4456+ /* Don't swap below two lines, halWtblReadRaw will
4457+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4458+ */
4459+ mt7996_wtbl_read_raw(dev, keyloc1,
4460+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4461+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4462+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4463+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4464+ KEYTBL_IDX2BASE(keyloc1, 0));
4465+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4466+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4467+ x,
4468+ keytbl[x * 4 + 3],
4469+ keytbl[x * 4 + 2],
4470+ keytbl[x * 4 + 1],
4471+ keytbl[x * 4]);
4472+ }
4473+ }
4474+
4475+ seq_printf(s, "\t%s:%d\n", "keyloc2", keyloc2);
4476+ if (keyloc2 != INVALID_KEY_ENTRY) {
4477+ /* Don't swap below two lines, halWtblReadRaw will
4478+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4479+ */
4480+ mt7996_wtbl_read_raw(dev, keyloc2,
4481+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4482+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4483+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4484+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4485+ KEYTBL_IDX2BASE(keyloc2, 0));
4486+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4487+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4488+ x,
4489+ keytbl[x * 4 + 3],
4490+ keytbl[x * 4 + 2],
4491+ keytbl[x * 4 + 1],
4492+ keytbl[x * 4]);
4493+ }
4494+ }
4495+}
4496+
4497+static void parse_fmac_uwtbl_key_info(struct seq_file *s, u8 *uwtbl, u8 *lwtbl)
4498+{
4499+ u32 *addr = 0;
4500+ u32 dw_value = 0;
4501+ uint16_t keyloc0 = INVALID_KEY_ENTRY;
4502+ uint16_t keyloc1 = INVALID_KEY_ENTRY;
4503+ uint16_t keyloc2 = INVALID_KEY_ENTRY;
4504+
4505+ /* UMAC WTBL DW 7 */
4506+ seq_printf(s, "\t\n");
4507+ seq_printf(s, "UWTBL key info\n");
4508+
4509+ addr = (u32 *)&(uwtbl[WF_UWTBL_KEY_LOC0_DW*4]);
4510+ dw_value = *addr;
4511+ keyloc0 = (dw_value & WF_UWTBL_KEY_LOC0_MASK) >> WF_UWTBL_KEY_LOC0_SHIFT;
4512+ keyloc1 = (dw_value & WF_UWTBL_KEY_LOC1_MASK) >> WF_UWTBL_KEY_LOC1_SHIFT;
4513+
4514+ seq_printf(s, "\t%s:%u/%u\n", "Key Loc 0/1", keyloc0, keyloc1);
4515+
4516+ /* UMAC WTBL DW 6 for BIGTK */
4517+ if (is_wtbl_bigtk_exist(lwtbl) == true) {
4518+ keyloc2 = (dw_value & WF_UWTBL_KEY_LOC2_MASK) >>
4519+ WF_UWTBL_KEY_LOC2_SHIFT;
4520+ seq_printf(s, "\t%s:%u\n", "Key Loc 2", keyloc2);
4521+ }
4522+
4523+ /* Parse KEY link */
4524+ dump_key_table(s, keyloc0, keyloc1, keyloc2);
4525+}
4526+
4527+static const struct berse_wtbl_parse WTBL_UMAC_DW8[] = {
4528+ {"UWTBL_WMM_Q", WF_UWTBL_WMM_Q_MASK, WF_UWTBL_WMM_Q_SHIFT, false},
4529+ {"UWTBL_QOS", WF_UWTBL_QOS_MASK, NO_SHIFT_DEFINE, false},
4530+ {"UWTBL_HT_VHT_HE", WF_UWTBL_HT_MASK, NO_SHIFT_DEFINE, false},
4531+ {"UWTBL_HDRT_MODE", WF_UWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, true},
4532+ {NULL,}
4533+};
4534+
4535+static void parse_fmac_uwtbl_msdu_info(struct seq_file *s, u8 *uwtbl)
4536+{
4537+ u32 *addr = 0;
4538+ u32 dw_value = 0;
4539+ u32 amsdu_len = 0;
4540+ u16 i = 0;
4541+
4542+ /* UMAC WTBL DW 8 */
4543+ seq_printf(s, "\t\n");
4544+ seq_printf(s, "UWTBL DW8\n");
4545+
4546+ addr = (u32 *)&(uwtbl[WF_UWTBL_AMSDU_CFG_DW*4]);
4547+ dw_value = *addr;
4548+
4549+ while (WTBL_UMAC_DW8[i].name) {
4550+
4551+ if (WTBL_UMAC_DW8[i].shift == NO_SHIFT_DEFINE)
4552+ seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW8[i].name,
4553+ (dw_value & WTBL_UMAC_DW8[i].mask) ? 1 : 0);
4554+ else
4555+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW8[i].name,
4556+ (dw_value & WTBL_UMAC_DW8[i].mask) >>
4557+ WTBL_UMAC_DW8[i].shift);
4558+ i++;
4559+ }
4560+
4561+ /* UMAC WTBL DW 8 - AMSDU_CFG */
4562+ seq_printf(s, "\t%s:%d\n", "HW AMSDU Enable",
4563+ (dw_value & WTBL_AMSDU_EN_MASK) ? 1 : 0);
4564+
4565+ amsdu_len = (dw_value & WTBL_AMSDU_LEN_MASK) >> WTBL_AMSDU_LEN_OFFSET;
4566+ if (amsdu_len == 0)
4567+ seq_printf(s, "\t%s:invalid (WTBL value=0x%x)\n", "HW AMSDU Len",
4568+ amsdu_len);
4569+ else if (amsdu_len == 1)
4570+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4571+ 1,
4572+ 255,
4573+ amsdu_len);
4574+ else if (amsdu_len == 2)
4575+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4576+ 256,
4577+ 511,
4578+ amsdu_len);
4579+ else if (amsdu_len == 3)
4580+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4581+ 512,
4582+ 767,
4583+ amsdu_len);
4584+ else
4585+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4586+ 256 * (amsdu_len - 1),
4587+ 256 * (amsdu_len - 1) + 255,
4588+ amsdu_len);
4589+
4590+ seq_printf(s, "\t%s:%lu (WTBL value=0x%lx)\n", "HW AMSDU Num",
4591+ ((dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET) + 1,
4592+ (dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET);
4593+}
4594+
4595+static int mt7996_wtbl_read(struct seq_file *s, void *data)
4596+{
4597+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4598+ u8 lwtbl[LWTBL_LEN_IN_DW * 4] = {0};
4599+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
4600+ int x;
4601+
4602+ mt7996_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
4603+ LWTBL_LEN_IN_DW, lwtbl);
4604+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
4605+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4606+ MT_DBG_WTBLON_TOP_WDUCR_ADDR,
4607+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR),
4608+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
4609+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
4610+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
4611+ x,
4612+ lwtbl[x * 4 + 3],
4613+ lwtbl[x * 4 + 2],
4614+ lwtbl[x * 4 + 1],
4615+ lwtbl[x * 4]);
4616+ }
4617+
4618+ /* Parse LWTBL */
4619+ parse_fmac_lwtbl_dw0_1(s, lwtbl);
4620+ parse_fmac_lwtbl_dw2(s, lwtbl);
4621+ parse_fmac_lwtbl_dw3(s, lwtbl);
4622+ parse_fmac_lwtbl_dw4(s, lwtbl);
4623+ parse_fmac_lwtbl_dw5(s, lwtbl);
4624+ parse_fmac_lwtbl_dw6(s, lwtbl);
4625+ parse_fmac_lwtbl_dw7(s, lwtbl);
4626+ parse_fmac_lwtbl_dw8(s, lwtbl);
4627+ parse_fmac_lwtbl_dw9(s, lwtbl);
4628+ parse_fmac_lwtbl_dw10(s, lwtbl);
4629+ parse_fmac_lwtbl_dw11(s, lwtbl);
4630+ parse_fmac_lwtbl_dw12(s, lwtbl);
4631+ parse_fmac_lwtbl_dw13(s, lwtbl);
4632+ parse_fmac_lwtbl_dw14(s, lwtbl);
4633+ parse_fmac_lwtbl_mlo_info(s, lwtbl);
4634+ parse_fmac_lwtbl_dw31(s, lwtbl);
4635+ parse_fmac_lwtbl_dw32(s, lwtbl);
4636+ parse_fmac_lwtbl_rx_stats(s, lwtbl);
4637+
4638+ mt7996_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
4639+ UWTBL_LEN_IN_DW, uwtbl);
4640+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
4641+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4642+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4643+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4644+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
4645+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
4646+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
4647+ x,
4648+ uwtbl[x * 4 + 3],
4649+ uwtbl[x * 4 + 2],
4650+ uwtbl[x * 4 + 1],
4651+ uwtbl[x * 4]);
4652+ }
4653+
4654+ /* Parse UWTBL */
4655+ parse_fmac_uwtbl_mlo_info(s, uwtbl);
4656+ parse_fmac_uwtbl_pn(s, uwtbl, lwtbl);
4657+ parse_fmac_uwtbl_sn(s, uwtbl);
4658+ parse_fmac_uwtbl_key_info(s, uwtbl, lwtbl);
4659+ parse_fmac_uwtbl_msdu_info(s, uwtbl);
4660+
4661+ return 0;
4662+}
4663+
4664+static int mt7996_sta_info(struct seq_file *s, void *data)
4665+{
4666+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4667+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
4668+ u16 i = 0;
4669+
4670+ for (i=0; i < mt7996_wtbl_size(dev); i++) {
4671+ mt7996_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
4672+ LWTBL_LEN_IN_DW, lwtbl);
4673+
4674+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1]) {
4675+ u32 *addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]);
4676+ u32 dw_value = *addr;
4677+
4678+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x",
4679+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
4680+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW2[0].name,
4681+ (dw_value & WTBL_LMAC_DW2[0].mask) >> WTBL_LMAC_DW2[0].shift);
4682+ }
4683+ }
4684+
4685+ return 0;
4686+}
4687+
4688+int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir)
4689+{
4690+ struct mt7996_dev *dev = phy->dev;
4691+
4692+ mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
4693+
4694+ /* agg */
4695+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
4696+ mt7996_agginfo_read_band0);
4697+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
4698+ mt7996_agginfo_read_band1);
4699+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info2", dir,
4700+ mt7996_agginfo_read_band2);
4701+ /* amsdu */
4702+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
4703+ mt7996_amsdu_result_read);
4704+
4705+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
4706+ &fops_fw_debug_module);
4707+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
4708+ &fops_fw_debug_level);
4709+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
4710+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
4711+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_version", dir,
4712+ mt7996_dump_version);
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]4713+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wa_info", dir,
4714+ mt7996_fw_wa_info_read);
4715+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wm_info", dir,
4716+ mt7996_fw_wm_info_read);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4717+
4718+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
4719+ mt7996_mibinfo_band0);
4720+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
4721+ mt7996_mibinfo_band1);
4722+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info2", dir,
4723+ mt7996_mibinfo_band2);
4724+
4725+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
4726+ mt7996_sta_info);
4727+
4728+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
4729+ mt7996_trinfo_read);
4730+
4731+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
4732+ mt7996_wtbl_read);
4733+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]4734+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
4735+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4736+ return 0;
4737+}
4738+
4739+#endif
4740diff --git a/mt7996/mtk_mcu.c b/mt7996/mtk_mcu.c
4741new file mode 100644
developerde9ecce2023-05-22 11:17:16 +0800[diff] [blame]4742index 00000000..e8870166
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4743--- /dev/null
4744+++ b/mt7996/mtk_mcu.c
4745@@ -0,0 +1,18 @@
4746+// SPDX-License-Identifier: ISC
4747+/*
4748+ * Copyright (C) 2023 MediaTek Inc.
4749+ */
4750+
4751+#include <linux/firmware.h>
4752+#include <linux/fs.h>
4753+#include "mt7996.h"
4754+#include "mcu.h"
4755+#include "mac.h"
4756+#include "mtk_mcu.h"
4757+
4758+#ifdef CONFIG_MTK_DEBUG
4759+
4760+
4761+
4762+
4763+#endif
4764diff --git a/mt7996/mtk_mcu.h b/mt7996/mtk_mcu.h
4765new file mode 100644
developerde9ecce2023-05-22 11:17:16 +0800[diff] [blame]4766index 00000000..e741aa27
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4767--- /dev/null
4768+++ b/mt7996/mtk_mcu.h
4769@@ -0,0 +1,16 @@
4770+/* SPDX-License-Identifier: ISC */
4771+/*
4772+ * Copyright (C) 2023 MediaTek Inc.
4773+ */
4774+
4775+#ifndef __MT7996_MTK_MCU_H
4776+#define __MT7996_MTK_MCU_H
4777+
4778+#include "../mt76_connac_mcu.h"
4779+
4780+#ifdef CONFIG_MTK_DEBUG
4781+
4782+
4783+#endif
4784+
4785+#endif
4786diff --git a/tools/fwlog.c b/tools/fwlog.c
developerde9ecce2023-05-22 11:17:16 +0800[diff] [blame]4787index e5d4a105..3c6a61d7 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4788--- a/tools/fwlog.c
4789+++ b/tools/fwlog.c
4790@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
4791 return path;
4792 }
4793
4794-static int mt76_set_fwlog_en(const char *phyname, bool en)
4795+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
4796 {
4797 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
4798
4799@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
4800 return 1;
4801 }
4802
4803- fprintf(f, "7");
4804+ if (en && val)
4805+ fprintf(f, "%s", val);
4806+ else if (en)
4807+ fprintf(f, "7");
4808+ else
4809+ fprintf(f, "0");
4810+
4811 fclose(f);
4812
4813 return 0;
4814@@ -76,6 +82,7 @@ static void handle_signal(int sig)
4815
4816 int mt76_fwlog(const char *phyname, int argc, char **argv)
4817 {
4818+#define BUF_SIZE 1504
4819 struct sockaddr_in local = {
4820 .sin_family = AF_INET,
4821 .sin_addr.s_addr = INADDR_ANY,
4822@@ -84,9 +91,9 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4823 .sin_family = AF_INET,
4824 .sin_port = htons(55688),
4825 };
4826- char buf[1504];
4827+ char *buf = calloc(BUF_SIZE, sizeof(char));
4828 int ret = 0;
4829- int yes = 1;
4830+ /* int yes = 1; */
4831 int s, fd;
4832
4833 if (argc < 1) {
4834@@ -105,13 +112,13 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4835 return 1;
4836 }
4837
4838- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
4839+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
4840 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
4841 perror("bind");
4842 return 1;
4843 }
4844
4845- if (mt76_set_fwlog_en(phyname, true))
4846+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
4847 return 1;
4848
4849 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
4850@@ -145,8 +152,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4851 if (!r)
4852 continue;
4853
4854- if (len > sizeof(buf)) {
4855- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
4856+ if (len > BUF_SIZE) {
4857+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
4858 ret = 1;
4859 break;
4860 }
4861@@ -171,7 +178,7 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4862 close(fd);
4863
4864 out:
4865- mt76_set_fwlog_en(phyname, false);
4866+ mt76_set_fwlog_en(phyname, false, NULL);
4867
4868 return ret;
4869 }
4870--
developerde9ecce2023-05-22 11:17:16 +0800[diff] [blame]48712.39.2
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4872