blob: 302f962de6be96739da8c697069e7159a9f5b007 [file] [log] [blame]
developer5f11e9e2022-03-10 15:03:47 +08001diff --git a/package/kernel/mt76/patches/1005-mt76-certification-patches.patch b/package/kernel/mt76/patches/1005-mt76-certification-patches.patch
developerbaa67712021-12-21 17:01:26 +08002new file mode 100644
developer5f11e9e2022-03-10 15:03:47 +08003index 00000000..e2034ac9
developerbaa67712021-12-21 17:01:26 +08004--- /dev/null
developer5f11e9e2022-03-10 15:03:47 +08005+++ b/package/kernel/mt76/patches/1005-mt76-certification-patches.patch
6@@ -0,0 +1,1161 @@
7+From c412ccd55171d3051fba026b5ec8bb84330e3735 Mon Sep 17 00:00:00 2001
8+From: MeiChia Chiu <meichia.chiu@mediatek.com>
9+Date: Fri, 21 Jan 2022 11:22:10 +0800
10+Subject: [PATCH 1005/1006] mt76: certification patches
11+
12+Signed-off-by: MeiChia Chiu <meichia.chiu@mediatek.com>
13+---
14+ .../wireless/mediatek/mt76/mt76_connac_mcu.h | 1 +
15+ .../net/wireless/mediatek/mt76/mt7915/init.c | 7 +-
16+ .../net/wireless/mediatek/mt76/mt7915/mac.c | 23 +
17+ .../net/wireless/mediatek/mt76/mt7915/main.c | 15 +-
18+ .../net/wireless/mediatek/mt76/mt7915/mcu.c | 463 ++++++++++++++++++
19+ .../net/wireless/mediatek/mt76/mt7915/mcu.h | 209 +++++++-
20+ .../wireless/mediatek/mt76/mt7915/mt7915.h | 13 +
21+ .../mediatek/mt76/mt7915/mtk_debugfs.c | 7 +-
22+ .../wireless/mediatek/mt76/mt7915/vendor.c | 187 +++++++
23+ .../wireless/mediatek/mt76/mt7915/vendor.h | 42 ++
24+ 10 files changed, 961 insertions(+), 6 deletions(-)
25+
26+diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
27+index 2173682..8903e08 100644
28+--- a/mt76_connac_mcu.h
29++++ b/mt76_connac_mcu.h
30+@@ -993,6 +993,7 @@ enum {
31+ MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
32+ /* for vendor csi and air monitor */
33+ MCU_EXT_CMD_SMESH_CTRL = 0xae,
34++ MCU_EXT_CMD_CERT_CFG = 0xb7,
35+ MCU_EXT_CMD_CSI_CTRL = 0xc2,
36+ };
37+
developerbaa67712021-12-21 17:01:26 +080038+diff --git a/mt7915/init.c b/mt7915/init.c
developer5f11e9e2022-03-10 15:03:47 +080039+index a12b701..aed4731 100644
developerbaa67712021-12-21 17:01:26 +080040+--- a/mt7915/init.c
41++++ b/mt7915/init.c
developer5f11e9e2022-03-10 15:03:47 +080042+@@ -366,12 +366,17 @@ mt7915_init_wiphy(struct ieee80211_hw *hw)
developerbaa67712021-12-21 17:01:26 +080043+ if (!phy->dev->dbdc_support)
44+ wiphy->txq_memory_limit = 32 << 20; /* 32 MiB */
45+
46+- if (phy->mt76->cap.has_2ghz)
47++ if (phy->mt76->cap.has_2ghz) {
48++ phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
49++ IEEE80211_HT_MPDU_DENSITY_4;
50+ phy->mt76->sband_2g.sband.ht_cap.cap |=
51+ IEEE80211_HT_CAP_LDPC_CODING |
52+ IEEE80211_HT_CAP_MAX_AMSDU;
53++ }
54+
55+ if (phy->mt76->cap.has_5ghz) {
56++ phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
57++ IEEE80211_HT_MPDU_DENSITY_4;
58+ phy->mt76->sband_5g.sband.ht_cap.cap |=
59+ IEEE80211_HT_CAP_LDPC_CODING |
60+ IEEE80211_HT_CAP_MAX_AMSDU;
61+diff --git a/mt7915/mac.c b/mt7915/mac.c
developer5f11e9e2022-03-10 15:03:47 +080062+index 9f595ca..efdc1b1 100644
developerbaa67712021-12-21 17:01:26 +080063+--- a/mt7915/mac.c
64++++ b/mt7915/mac.c
65+@@ -7,6 +7,7 @@
66+ #include "../dma.h"
67+ #include "mac.h"
68+ #include "mcu.h"
69++#include "vendor.h"
70+
71+ #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
72+
developer5f11e9e2022-03-10 15:03:47 +080073+@@ -2294,6 +2295,21 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
developerbaa67712021-12-21 17:01:26 +080074+ }
75+ }
developer5f11e9e2022-03-10 15:03:47 +080076+
developerbaa67712021-12-21 17:01:26 +080077++#ifdef CONFIG_MTK_VENDOR
78++void mt7915_capi_sta_rc_work(void *data, struct ieee80211_sta *sta)
79++{
80++ struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
81++ struct mt7915_dev *dev = msta->vif->phy->dev;
developerbaa67712021-12-21 17:01:26 +080082++ u32 *changed = data;
developer5f11e9e2022-03-10 15:03:47 +080083++
developerbaa67712021-12-21 17:01:26 +080084++ spin_lock_bh(&dev->sta_poll_lock);
85++ msta->changed |= *changed;
developer5f11e9e2022-03-10 15:03:47 +080086++ if (list_empty(&msta->rc_list))
developerbaa67712021-12-21 17:01:26 +080087++ list_add_tail(&msta->rc_list, &dev->sta_rc_list);
developerbaa67712021-12-21 17:01:26 +080088++ spin_unlock_bh(&dev->sta_poll_lock);
89++}
90++#endif
developer5f11e9e2022-03-10 15:03:47 +080091++
developerbaa67712021-12-21 17:01:26 +080092+ void mt7915_mac_sta_rc_work(struct work_struct *work)
93+ {
94+ struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work);
developer5f11e9e2022-03-10 15:03:47 +080095+@@ -2316,6 +2332,13 @@ void mt7915_mac_sta_rc_work(struct work_struct *work)
developerbaa67712021-12-21 17:01:26 +080096+ sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
97+ vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
developer5f11e9e2022-03-10 15:03:47 +080098+
developerbaa67712021-12-21 17:01:26 +080099++#ifdef CONFIG_MTK_VENDOR
100++ if (changed & CAPI_RFEATURE_CHANGED) {
101++ mt7915_mcu_set_rfeature_starec(&changed, dev, vif, sta);
102++ spin_lock_bh(&dev->sta_poll_lock);
103++ continue;
104++ }
105++#endif
106+ if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED |
107+ IEEE80211_RC_NSS_CHANGED |
108+ IEEE80211_RC_BW_CHANGED))
109+diff --git a/mt7915/main.c b/mt7915/main.c
developer5f11e9e2022-03-10 15:03:47 +0800110+index 1beadd8..a09cd74 100644
developerbaa67712021-12-21 17:01:26 +0800111+--- a/mt7915/main.c
112++++ b/mt7915/main.c
developer5f11e9e2022-03-10 15:03:47 +0800113+@@ -655,6 +655,9 @@ int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
developerbaa67712021-12-21 17:01:26 +0800114+ struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
115+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
developer5f11e9e2022-03-10 15:03:47 +0800116+ bool ext_phy = mvif->phy != &dev->phy;
developerbaa67712021-12-21 17:01:26 +0800117++#ifdef CONFIG_MTK_VENDOR
118++ struct mt7915_phy *phy;
119++#endif
120+ int ret, idx;
121+
122+ idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
developer5f11e9e2022-03-10 15:03:47 +0800123+@@ -680,7 +683,17 @@ int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
developerbaa67712021-12-21 17:01:26 +0800124+ #ifdef CONFIG_MTK_VENDOR
125+ mt7915_vendor_amnt_sta_remove(mvif->phy, sta);
126+ #endif
127+- return mt7915_mcu_add_rate_ctrl(dev, vif, sta, false);
128++ ret = mt7915_mcu_add_rate_ctrl(dev, vif, sta, false);
129++ if (ret)
130++ return ret;
131++
132++#ifdef CONFIG_MTK_VENDOR
133++ if (dev->dbg.muru_onoff & MUMIMO_DL_CERT) {
developer5f11e9e2022-03-10 15:03:47 +0800134++ phy = mvif->mt76.band_idx ? mt7915_ext_phy(dev) : &dev->phy;
developerbaa67712021-12-21 17:01:26 +0800135++ mt7915_mcu_set_mimo(phy, 0);
136++ }
137++#endif
138++ return 0;
139+ }
140+
141+ void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
142+diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer5f11e9e2022-03-10 15:03:47 +0800143+index f01a2f0..bb77edc 100644
developerbaa67712021-12-21 17:01:26 +0800144+--- a/mt7915/mcu.c
145++++ b/mt7915/mcu.c
developer5f11e9e2022-03-10 15:03:47 +0800146+@@ -3707,6 +3707,469 @@ mt7915_mcu_report_csi(struct mt7915_dev *dev, struct sk_buff *skb)
147+
148+ return 0;
developerbaa67712021-12-21 17:01:26 +0800149+ }
developerbaa67712021-12-21 17:01:26 +0800150++void mt7915_set_wireless_vif(void *data, u8 *mac, struct ieee80211_vif *vif)
151++{
152++ u8 mode, val;
153++ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
154++ struct mt7915_dev *dev = mvif->phy->dev;
155++
156++ mode = FIELD_GET(RATE_CFG_MODE, *((u32 *)data));
157++ val = FIELD_GET(RATE_CFG_VAL, *((u32 *)data));
158++
159++ switch (mode) {
160++ case RATE_PARAM_FIXED_OFDMA:
161++ dev->dbg.muru_onoff = val;
162++ break;
163++ case RATE_PARAM_FIXED_MIMO:
164++ if (val == 0)
165++ dev->dbg.muru_onoff = FIELD_PREP(MUMIMO_DL_CERT, 1);
166++ break;
167++ }
168++}
169++
170++void mt7915_mcu_set_rfeature_starec(void *data, struct mt7915_dev *dev,
171++ struct ieee80211_vif *vif, struct ieee80211_sta *sta)
172++{
173++ struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
174++ struct mt7915_vif *mvif = msta->vif;
175++ struct sta_rec_ra_fixed *ra;
176++ struct sk_buff *skb;
177++ struct tlv *tlv;
178++ u8 mode, val;
179++ int len = sizeof(struct sta_req_hdr) + sizeof(*ra);
180++
181++ mode = FIELD_GET(RATE_CFG_MODE, *((u32 *)data));
182++ val = FIELD_GET(RATE_CFG_VAL, *((u32 *)data));
183++
developer5f11e9e2022-03-10 15:03:47 +0800184++ skb = __mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, &msta->wcid, len);
developerbaa67712021-12-21 17:01:26 +0800185++ if (IS_ERR(skb))
developer5f11e9e2022-03-10 15:03:47 +0800186++ return;
developerbaa67712021-12-21 17:01:26 +0800187++
developer5f11e9e2022-03-10 15:03:47 +0800188++ tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_RA_UPDATE, sizeof(*ra));
developerbaa67712021-12-21 17:01:26 +0800189++ ra = (struct sta_rec_ra_fixed *)tlv;
190++
191++ switch (mode) {
192++ case RATE_PARAM_FIXED_GI:
193++ ra->field = cpu_to_le32(RATE_PARAM_FIXED_GI);
194++ ra->phy.sgi = val * 85;
195++ break;
196++ case RATE_PARAM_FIXED_HE_LTF:
197++ ra->field = cpu_to_le32(RATE_PARAM_FIXED_HE_LTF);
198++ ra->phy.he_ltf = val * 85;
199++ break;
200++ case RATE_PARAM_FIXED_MCS:
201++ ra->field = cpu_to_le32(RATE_PARAM_FIXED_MCS);
202++ ra->phy.mcs = val;
203++ break;
204++ }
205++
206++ mt76_mcu_skb_send_msg(&dev->mt76, skb,
207++ MCU_EXT_CMD(STA_REC_UPDATE), true);
208++}
209++
210++int mt7915_mcu_set_mu_prot_frame_th(struct mt7915_phy *phy, u32 val)
211++{
212++ struct mt7915_dev *dev = phy->dev;
213++ struct {
214++ __le32 cmd;
215++ __le32 threshold;
216++ } __packed req = {
217++ .cmd = cpu_to_le32(MURU_SET_PROT_FRAME_THR),
218++ .threshold = val,
219++ };
220++
221++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
222++ sizeof(req), false);
223++}
224++
225++int mt7915_mcu_set_mu_edca(struct mt7915_phy *phy, u8 val)
226++{
227++ struct mt7915_dev *dev = phy->dev;
228++ struct {
229++ __le32 cmd;
230++ u8 override;
231++ } __packed req = {
232++ .cmd = cpu_to_le32(MURU_SET_CERT_MU_EDCA_OVERRIDE),
233++ .override = val,
234++ };
235++
236++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
237++ sizeof(req), false);
238++}
239++
240++int mt7915_mcu_set_muru_cfg(struct mt7915_phy *phy, struct mt7915_muru *muru)
241++{
242++ struct mt7915_dev *dev = phy->dev;
243++ struct {
244++ __le32 cmd;
245++ struct mt7915_muru muru;
246++ } __packed req = {
247++ .cmd = cpu_to_le32(MURU_SET_MANUAL_CFG),
248++ };
249++
250++ memcpy(&req.muru, muru, sizeof(struct mt7915_muru));
251++
252++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
253++ sizeof(req), false);
254++}
255++
256++int mt7915_set_muru_cfg(struct mt7915_phy *phy, u8 action, u8 val)
257++{
258++ struct mt7915_muru muru;
259++ struct mt7915_muru_dl *dl = &muru.dl;
260++ struct mt7915_muru_ul *ul = &muru.ul;
261++ struct mt7915_muru_comm *comm = &muru.comm;
262++
263++ memset(&muru, 0, sizeof(muru));
264++
265++ switch (action) {
266++ case MURU_DL_USER_CNT:
267++ dl->user_num = val;
268++ comm->ppdu_format |= MURU_PPDU_HE_MU;
269++ comm->sch_type |= MURU_OFDMA_SCH_TYPE_DL;
270++ muru.cfg_comm = cpu_to_le32(MURU_COMM_SET);
271++ muru.cfg_dl = cpu_to_le32(MURU_USER_CNT);
272++ return mt7915_mcu_set_muru_cfg(phy, &muru);
273++ case MURU_UL_USER_CNT:
274++ ul->user_num = val;
275++ comm->ppdu_format |= MURU_PPDU_HE_TRIG;
276++ comm->sch_type |= MURU_OFDMA_SCH_TYPE_UL;
277++ muru.cfg_comm = cpu_to_le32(MURU_COMM_SET);
278++ muru.cfg_ul = cpu_to_le32(MURU_USER_CNT);
279++ return mt7915_mcu_set_muru_cfg(phy, &muru);
280++ default:
281++ return 0;
282++ }
283++}
284++
285++void mt7915_mcu_set_ppdu_tx_type(struct mt7915_phy *phy, u8 ppdu_type)
286++{
287++ struct mt7915_dev *dev = phy->dev;
288++ struct {
289++ __le32 cmd;
290++ u8 enable_su;
291++ } __packed ppdu_type_req = {
292++ .cmd = cpu_to_le32(MURU_SET_SUTX),
293++ };
294++
295++ switch(ppdu_type) {
296++ case CAPI_SU:
297++ ppdu_type_req.enable_su = 1;
298++ mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL),
299++ &ppdu_type_req, sizeof(ppdu_type_req), false);
300++ mt7915_set_muru_cfg(phy, MURU_DL_USER_CNT, 0);
301++ break;
302++ case CAPI_MU:
303++ ppdu_type_req.enable_su = 0;
304++ mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL),
305++ &ppdu_type_req, sizeof(ppdu_type_req), false);
306++ break;
307++ default:
308++ break;
309++ }
310++}
311++
312++void mt7915_mcu_set_nusers_ofdma(struct mt7915_phy *phy, u8 type, u8 ofdma_user_cnt)
313++{
314++ struct mt7915_dev *dev = phy->dev;
315++ struct {
316++ __le32 cmd;
317++ u8 enable_su;
318++ } __packed nusers_ofdma_req = {
319++ .cmd = cpu_to_le32(MURU_SET_SUTX),
320++ .enable_su = 0,
321++ };
322++
323++ mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL),
324++ &nusers_ofdma_req, sizeof(nusers_ofdma_req), false);
325++
326++ mt7915_mcu_set_mu_dl_ack_policy(phy, MU_DL_ACK_POLICY_SU_BAR);
327++ mt7915_mcu_set_mu_prot_frame_th(phy, 9999);
328++ switch(type) {
329++ case MURU_UL_USER_CNT:
330++ mt7915_set_muru_cfg(phy, MURU_UL_USER_CNT, ofdma_user_cnt);
331++ break;
332++ case MURU_DL_USER_CNT:
333++ default:
334++ mt7915_set_muru_cfg(phy, MURU_DL_USER_CNT, ofdma_user_cnt);
335++ break;
336++ }
337++}
338++
339++void mt7915_mcu_set_mimo(struct mt7915_phy *phy, u8 direction)
340++{
341++#define MUMIMO_SET_FIXED_RATE 10
342++#define MUMIMO_SET_FIXED_GRP_RATE 11
343++#define MUMIMO_SET_FORCE_MU 12
344++ struct mt7915_dev *dev = phy->dev;
345++ struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
346++ struct {
347++ __le32 cmd;
348++ __le16 sub_cmd;
349++ __le16 disable_ra;
350++ } __packed fixed_rate_req = {
351++ .cmd = cpu_to_le32(MURU_SET_MUMIMO_CTRL),
352++ .sub_cmd = cpu_to_le16(MUMIMO_SET_FIXED_RATE),
353++ .disable_ra = 1,
354++ };
355++ struct {
356++ __le32 cmd;
357++ __le32 sub_cmd;
358++ struct {
359++ u8 user_cnt:2;
360++ u8 rsv:2;
361++ u8 ns0:1;
362++ u8 ns1:1;
363++ u8 ns2:1;
364++ u8 ns3:1;
365++
366++ __le16 wlan_id_user0;
367++ __le16 wlan_id_user1;
368++ __le16 wlan_id_user2;
369++ __le16 wlan_id_user3;
370++
371++ u8 dl_mcs_user0:4;
372++ u8 dl_mcs_user1:4;
373++ u8 dl_mcs_user2:4;
374++ u8 dl_mcs_user3:4;
375++
376++ u8 ul_mcs_user0:4;
377++ u8 ul_mcs_user1:4;
378++ u8 ul_mcs_user2:4;
379++ u8 ul_mcs_user3:4;
380++
381++ u8 ru_alloc;
382++ u8 cap;
383++ u8 gi;
384++ u8 dl_ul;
385++ } grp_rate_conf;
386++ } fixed_grp_rate_req = {
387++ .cmd = cpu_to_le32(MURU_SET_MUMIMO_CTRL),
388++ .sub_cmd = cpu_to_le32(MUMIMO_SET_FIXED_GRP_RATE),
389++ .grp_rate_conf = {
390++ .user_cnt = 1,
391++ .ru_alloc = 134,
392++ .gi = 0,
393++ .cap = 1,
394++ .dl_ul = 0,
395++ .wlan_id_user0 = cpu_to_le16(1),
396++ .dl_mcs_user0 = 2,
397++ .wlan_id_user1 = cpu_to_le16(2),
398++ .dl_mcs_user1 = 2,
399++ },
400++ };
401++ struct {
402++ __le32 cmd;
403++ __le16 sub_cmd;
404++ bool force_mu;
405++ } __packed force_mu_req = {
406++ .cmd = cpu_to_le32(MURU_SET_MUMIMO_CTRL),
407++ .sub_cmd = cpu_to_le16(MUMIMO_SET_FORCE_MU),
408++ .force_mu = true,
409++ };
410++
411++ switch (chandef->width) {
412++ case NL80211_CHAN_WIDTH_20_NOHT:
413++ case NL80211_CHAN_WIDTH_20:
414++ fixed_grp_rate_req.grp_rate_conf.ru_alloc = 122;
415++ break;
416++ case NL80211_CHAN_WIDTH_80:
417++ default:
418++ break;
419++ }
420++
421++ mt7915_mcu_set_mu_dl_ack_policy(phy, MU_DL_ACK_POLICY_SU_BAR);
422++
423++ mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL),
424++ &fixed_rate_req, sizeof(fixed_rate_req), false);
425++ mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL),
426++ &fixed_grp_rate_req, sizeof(fixed_grp_rate_req), false);
427++ mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL),
428++ &force_mu_req, sizeof(force_mu_req), false);
429++}
430++
431++void mt7915_mcu_set_dynalgo(struct mt7915_phy *phy, u8 enable)
432++{
433++ struct mt7915_dev *dev = phy->dev;
434++ struct {
435++ __le32 cmd;
436++ u8 enable;
437++ } __packed req = {
438++ .cmd = cpu_to_le32(MURU_SET_20M_DYN_ALGO),
439++ .enable = enable,
440++ };
441++
442++ mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL),
443++ &req, sizeof(req), false);
444++}
445++
446++void mt7915_mcu_set_cert(struct mt7915_phy *phy, u8 type)
447++{
448++#define CFGINFO_CERT_CFG 4
449++ struct mt7915_dev *dev = phy->dev;
450++ struct {
451++ struct basic_info{
452++ u8 dbdc_idx;
453++ u8 rsv[3];
454++ __le32 tlv_num;
455++ u8 tlv_buf[0];
456++ } hdr;
457++ struct cert_cfg{
458++ __le16 tag;
459++ __le16 length;
460++ u8 cert_program;
461++ u8 rsv[3];
462++ } tlv;
463++ } req = {
464++ .hdr = {
465++ .dbdc_idx = phy != &dev->phy,
466++ .tlv_num = cpu_to_le32(1),
467++ },
468++ .tlv = {
469++ .tag = cpu_to_le16(CFGINFO_CERT_CFG),
470++ .length = cpu_to_le16(sizeof(struct cert_cfg)),
471++ .cert_program = type, /* 1: CAPI Enable */
472++ }
473++ };
474++
475++ mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(CERT_CFG),
476++ &req, sizeof(req), false);
477++}
478++
479++void mt7915_mcu_set_bypass_smthint(struct mt7915_phy *phy, u8 val)
480++{
481++#define BF_CMD_CFG_PHY 36
482++#define BF_PHY_SMTH_INTL_BYPASS 0
483++ struct mt7915_dev *dev = phy->dev;
484++ struct {
485++ u8 cmd_category_id;
486++ u8 action;
487++ u8 band_idx;
488++ u8 smthintbypass;
489++ u8 rsv[12];
490++ } req = {
491++ .cmd_category_id = BF_CMD_CFG_PHY,
492++ .action = BF_PHY_SMTH_INTL_BYPASS,
493++ .band_idx = phy != &dev->phy,
494++ .smthintbypass = val,
495++ };
496++
497++ mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION),
498++ &req, sizeof(req), false);
499++}
500++
developerbaa67712021-12-21 17:01:26 +0800501++int mt7915_mcu_set_bsrp_ctrl(struct mt7915_phy *phy, u16 interval,
502++ u16 ru_alloc, u32 ppdu_dur, u8 trig_flow, u8 ext_cmd)
503++{
504++ struct mt7915_dev *dev = phy->dev;
505++ struct {
506++ __le32 cmd;
507++ __le16 bsrp_interval;
508++ __le16 bsrp_ru_alloc;
509++ __le32 ppdu_duration;
510++ u8 trigger_flow;
511++ u8 ext_cmd_bsrp;
512++ } __packed req = {
513++ .cmd = cpu_to_le32(MURU_SET_BSRP_CTRL),
514++ .bsrp_interval = cpu_to_le16(interval),
515++ .bsrp_ru_alloc = cpu_to_le16(ru_alloc),
516++ .ppdu_duration = cpu_to_le32(ppdu_dur),
517++ .trigger_flow = trig_flow,
518++ .ext_cmd_bsrp = ext_cmd,
519++ };
520++
521++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
522++ sizeof(req), false);
523++}
524++
525++int mt7915_mcu_set_mu_dl_ack_policy(struct mt7915_phy *phy, u8 policy_num)
526++{
527++ struct mt7915_dev *dev = phy->dev;
528++ struct {
529++ __le32 cmd;
530++ u8 ack_policy;
531++ } __packed req = {
532++ .cmd = cpu_to_le32(MURU_SET_MU_DL_ACK_POLICY),
533++ .ack_policy = policy_num,
534++ };
535++
536++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
537++ sizeof(req), false);
538++}
539++
540++int mt7915_mcu_set_txbf_sound_info(struct mt7915_phy *phy, u8 action,
541++ u8 v1, u8 v2, u8 v3)
542++{
543++ struct mt7915_dev *dev = phy->dev;
544++ struct {
545++ u8 cmd_category_id;
546++ u8 action;
547++ u8 read_clear;
548++ u8 vht_opt;
549++ u8 he_opt;
550++ u8 glo_opt;
551++ __le16 wlan_idx;
552++ u8 sound_interval;
553++ u8 sound_stop;
554++ u8 max_sound_sta;
555++ u8 tx_time;
556++ u8 mcs;
557++ bool ldpc;
558++ u8 inf;
559++ u8 rsv;
560++ } __packed req = {
561++ .cmd_category_id = BF_CMD_TXSND_INFO,
562++ .action = action,
563++ };
564++
565++ switch (action) {
566++ case BF_SND_CFG_OPT:
567++ req.vht_opt = v1;
568++ req.he_opt = v2;
569++ req.glo_opt = v3;
570++ break;
571++ default:
572++ return -EINVAL;
573++ }
574++
575++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
576++ sizeof(req), false);
577++}
578++
579++int mt7915_mcu_set_rfeature_trig_type(struct mt7915_phy *phy, u8 enable, u8 trig_type)
580++{
581++ struct mt7915_dev *dev = phy->dev;
582++ int ret = 0;
583++ struct {
584++ __le32 cmd;
585++ u8 trig_type;
586++ } __packed req = {
587++ .cmd = cpu_to_le32(MURU_SET_TRIG_TYPE),
588++ .trig_type = trig_type,
589++ };
590++
591++ if (enable) {
592++ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
593++ sizeof(req), false);
594++ if (ret)
595++ return ret;
596++ }
597++
598++ switch (trig_type) {
599++ case CAPI_BASIC:
600++ return mt7915_mcu_set_bsrp_ctrl(phy, 5, 67, 0, 0, enable);
601++ case CAPI_BRP:
602++ return mt7915_mcu_set_txbf_sound_info(phy, BF_SND_CFG_OPT,
603++ 0x0, 0x0, 0x1b);
604++ case CAPI_MU_BAR:
605++ return mt7915_mcu_set_mu_dl_ack_policy(phy,
606++ MU_DL_ACK_POLICY_MU_BAR);
607++ case CAPI_BSRP:
608++ return mt7915_mcu_set_bsrp_ctrl(phy, 5, 67, 4, 0, enable);
609++ default:
610++ return 0;
611++ }
612++}
613+ #endif
developer5f11e9e2022-03-10 15:03:47 +0800614+
615+ #ifdef MTK_DEBUG
developerbaa67712021-12-21 17:01:26 +0800616+diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer5f11e9e2022-03-10 15:03:47 +0800617+index 2a88bee..30211cb 100644
developerbaa67712021-12-21 17:01:26 +0800618+--- a/mt7915/mcu.h
619++++ b/mt7915/mcu.h
developer5f11e9e2022-03-10 15:03:47 +0800620+@@ -430,9 +430,13 @@ enum {
developerbaa67712021-12-21 17:01:26 +0800621+ RATE_PARAM_FIXED = 3,
622+ RATE_PARAM_MMPS_UPDATE = 5,
623+ RATE_PARAM_FIXED_HE_LTF = 7,
624+- RATE_PARAM_FIXED_MCS,
625++ RATE_PARAM_FIXED_MCS = 8,
626+ RATE_PARAM_FIXED_GI = 11,
627+ RATE_PARAM_AUTO = 20,
628++#ifdef CONFIG_MTK_VENDOR
629++ RATE_PARAM_FIXED_MIMO = 30,
630++ RATE_PARAM_FIXED_OFDMA = 31,
631++#endif
632+ };
633+
634+ #define RATE_CFG_MCS GENMASK(3, 0)
developer5f11e9e2022-03-10 15:03:47 +0800635+@@ -444,6 +448,9 @@ enum {
636+ #define RATE_CFG_PHY_TYPE GENMASK(27, 24)
637+ #define RATE_CFG_HE_LTF GENMASK(31, 28)
developerbaa67712021-12-21 17:01:26 +0800638+
639++#define RATE_CFG_MODE GENMASK(15, 8)
640++#define RATE_CFG_VAL GENMASK(7, 0)
641++
642+ enum {
developer5f11e9e2022-03-10 15:03:47 +0800643+ THERMAL_PROTECT_PARAMETER_CTRL,
644+ THERMAL_PROTECT_BASIC_INFO,
645+@@ -573,5 +580,205 @@ struct csi_data {
developerbaa67712021-12-21 17:01:26 +0800646+ #define OFDMA_UL BIT(1)
647+ #define MUMIMO_DL BIT(2)
648+ #define MUMIMO_UL BIT(3)
649++#define MUMIMO_DL_CERT BIT(4)
650++
developer5f11e9e2022-03-10 15:03:47 +0800651++
652++#ifdef CONFIG_MTK_VENDOR
developerbaa67712021-12-21 17:01:26 +0800653++struct mt7915_muru_comm {
654++ u8 ppdu_format;
655++ u8 sch_type;
656++ u8 band;
657++ u8 wmm_idx;
658++ u8 spe_idx;
659++ u8 proc_type;
660++};
661++
662++struct mt7915_muru_dl {
663++ u8 user_num;
664++ u8 tx_mode;
665++ u8 bw;
666++ u8 gi;
667++ u8 ltf;
668++ /* sigB */
669++ u8 mcs;
670++ u8 dcm;
671++ u8 cmprs;
672++
673++ u8 ru[8];
674++ u8 c26[2];
675++ u8 ack_policy;
676++
677++ struct {
678++ __le16 wlan_idx;
679++ u8 ru_alloc_seg;
680++ u8 ru_idx;
681++ u8 ldpc;
682++ u8 nss;
683++ u8 mcs;
684++ u8 mu_group_idx;
685++ u8 vht_groud_id;
686++ u8 vht_up;
687++ u8 he_start_stream;
688++ u8 he_mu_spatial;
689++ u8 ack_policy;
690++ __le16 tx_power_alpha;
691++ } usr[16];
692++};
693++
694++struct mt7915_muru_ul {
695++ u8 user_num;
696++
697++ /* UL TX */
698++ u8 trig_type;
699++ __le16 trig_cnt;
700++ __le16 trig_intv;
701++ u8 bw;
702++ u8 gi_ltf;
703++ __le16 ul_len;
704++ u8 pad;
705++ u8 trig_ta[ETH_ALEN];
706++ u8 ru[8];
707++ u8 c26[2];
708++
709++ struct {
710++ __le16 wlan_idx;
711++ u8 ru_alloc;
712++ u8 ru_idx;
713++ u8 ldpc;
714++ u8 nss;
715++ u8 mcs;
716++ u8 target_rssi;
717++ __le32 trig_pkt_size;
718++ } usr[16];
719++
720++ /* HE TB RX Debug */
721++ __le32 rx_hetb_nonsf_en_bitmap;
722++ __le32 rx_hetb_cfg[2];
723++
724++ /* DL TX */
725++ u8 ba_type;
726++};
727++
728++struct mt7915_muru {
729++ __le32 cfg_comm;
730++ __le32 cfg_dl;
731++ __le32 cfg_ul;
732++
733++ struct mt7915_muru_comm comm;
734++ struct mt7915_muru_dl dl;
735++ struct mt7915_muru_ul ul;
736++};
737++
738++#define MURU_PPDU_HE_TRIG BIT(2)
739++#define MURU_PPDU_HE_MU BIT(3)
740++
741++#define MURU_OFDMA_SCH_TYPE_DL BIT(0)
742++#define MURU_OFDMA_SCH_TYPE_UL BIT(1)
743++
744++/* Common Config */
745++#define MURU_COMM_PPDU_FMT BIT(0)
746++#define MURU_COMM_SCH_TYPE BIT(1)
747++#define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_SCH_TYPE)
748++
749++/* DL&UL User config*/
750++#define MURU_USER_CNT BIT(4)
751++
752++enum {
753++ CAPI_SU,
754++ CAPI_MU,
755++ CAPI_ER_SU,
756++ CAPI_TB,
757++ CAPI_LEGACY
758++};
759++
760++enum {
761++ CAPI_BASIC,
762++ CAPI_BRP,
763++ CAPI_MU_BAR,
764++ CAPI_MU_RTS,
765++ CAPI_BSRP,
766++ CAPI_GCR_MU_BAR,
767++ CAPI_BQRP,
768++ CAPI_NDP_FRP
769++};
770++
771++enum {
772++ MURU_SET_BSRP_CTRL = 1,
773++ MURU_SET_SUTX = 16,
774++ MURU_SET_MUMIMO_CTRL = 17,
775++ MURU_SET_MANUAL_CFG = 100,
776++ MURU_SET_MU_DL_ACK_POLICY = 200,
777++ MURU_SET_TRIG_TYPE = 201,
778++ MURU_SET_20M_DYN_ALGO = 202,
779++ MURU_SET_PROT_FRAME_THR = 204,
780++ MURU_SET_CERT_MU_EDCA_OVERRIDE = 205,
781++};
782++
783++enum {
784++ MU_DL_ACK_POLICY_MU_BAR = 3,
785++ MU_DL_ACK_POLICY_TF_FOR_ACK = 4,
786++ MU_DL_ACK_POLICY_SU_BAR = 5,
787++};
788++
789++enum {
790++ BF_SOUNDING_OFF = 0,
791++ BF_SOUNDING_ON,
792++ BF_DATA_PACKET_APPLY,
793++ BF_PFMU_MEM_ALLOCATE,
794++ BF_PFMU_MEM_RELEASE,
795++ BF_PFMU_TAG_READ,
796++ BF_PFMU_TAG_WRITE,
797++ BF_PROFILE_READ,
798++ BF_PROFILE_WRITE,
799++ BF_PN_READ,
800++ BF_PN_WRITE,
801++ BF_PFMU_MEM_ALLOC_MAP_READ,
802++ BF_AID_SET,
803++ BF_STA_REC_READ,
804++ BF_PHASE_CALIBRATION,
805++ BF_IBF_PHASE_COMP,
806++ BF_LNA_GAIN_CONFIG,
807++ BF_PROFILE_WRITE_20M_ALL,
808++ BF_APCLIENT_CLUSTER,
809++ BF_AWARE_CTRL,
810++ BF_HW_ENABLE_STATUS_UPDATE,
811++ BF_REPT_CLONED_STA_TO_NORMAL_STA,
812++ BF_GET_QD,
813++ BF_BFEE_HW_CTRL,
814++ BF_PFMU_SW_TAG_WRITE,
815++ BF_MOD_EN_CTRL,
816++ BF_DYNSND_EN_INTR,
817++ BF_DYNSND_CFG_DMCS_TH,
818++ BF_DYNSND_EN_PFID_INTR,
819++ BF_CONFIG,
820++ BF_PFMU_DATA_WRITE,
821++ BF_FBRPT_DBG_INFO_READ,
822++ BF_CMD_TXSND_INFO,
823++ BF_CMD_PLY_INFO,
824++ BF_CMD_MU_METRIC,
825++ BF_CMD_TXCMD,
826++ BF_CMD_CFG_PHY,
827++ BF_CMD_SND_CNT,
828++ BF_CMD_MAX
829++};
830++
831++enum {
832++ BF_SND_READ_INFO = 0,
833++ BF_SND_CFG_OPT,
834++ BF_SND_CFG_INTV,
835++ BF_SND_STA_STOP,
836++ BF_SND_CFG_MAX_STA,
837++ BF_SND_CFG_BFRP,
838++ BF_SND_CFG_INF
839++};
840++
841++enum {
842++ MURU_UPDATE = 0,
843++ MURU_DL_USER_CNT,
844++ MURU_UL_USER_CNT,
845++ MURU_DL_INIT,
846++ MURU_UL_INIT,
847++};
developer5f11e9e2022-03-10 15:03:47 +0800848++#endif
developerbaa67712021-12-21 17:01:26 +0800849+
850+ #endif
851+diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer5f11e9e2022-03-10 15:03:47 +0800852+index eddcc6d..b3abe77 100644
developerbaa67712021-12-21 17:01:26 +0800853+--- a/mt7915/mt7915.h
854++++ b/mt7915/mt7915.h
developer5f11e9e2022-03-10 15:03:47 +0800855+@@ -655,6 +655,19 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerbaa67712021-12-21 17:01:26 +0800856+ #endif
developer5f11e9e2022-03-10 15:03:47 +0800857+
developerbaa67712021-12-21 17:01:26 +0800858+ #ifdef CONFIG_MTK_VENDOR
859++void mt7915_capi_sta_rc_work(void *data, struct ieee80211_sta *sta);
860++void mt7915_set_wireless_vif(void *data, u8 *mac, struct ieee80211_vif *vif);
861++void mt7915_mcu_set_rfeature_starec(void *data, struct mt7915_dev *dev,
862++ struct ieee80211_vif *vif, struct ieee80211_sta *sta);
863++int mt7915_mcu_set_rfeature_trig_type(struct mt7915_phy *phy, u8 enable, u8 trig_type);
864++int mt7915_mcu_set_mu_dl_ack_policy(struct mt7915_phy *phy, u8 policy_num);
865++void mt7915_mcu_set_ppdu_tx_type(struct mt7915_phy *phy, u8 ppdu_type);
866++void mt7915_mcu_set_nusers_ofdma(struct mt7915_phy *phy, u8 type, u8 ofdma_user_cnt);
867++void mt7915_mcu_set_mimo(struct mt7915_phy *phy, u8 direction);
868++void mt7915_mcu_set_dynalgo(struct mt7915_phy *phy, u8 enable);
869++int mt7915_mcu_set_mu_edca(struct mt7915_phy *phy, u8 val);
870++void mt7915_mcu_set_cert(struct mt7915_phy *phy, u8 type);
871++void mt7915_mcu_set_bypass_smthint(struct mt7915_phy *phy, u8 val);
872+ void mt7915_vendor_register(struct mt7915_phy *phy);
873+ int mt7915_mcu_set_csi(struct mt7915_phy *phy, u8 mode,
874+ u8 cfg, u8 v1, u32 v2, u8 *mac_addr);
875+diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
developer5f11e9e2022-03-10 15:03:47 +0800876+index 4ebeeb2..63853f7 100644
developerbaa67712021-12-21 17:01:26 +0800877+--- a/mt7915/mtk_debugfs.c
878++++ b/mt7915/mtk_debugfs.c
developer5f11e9e2022-03-10 15:03:47 +0800879+@@ -2436,7 +2436,8 @@ static int mt7915_muru_onoff_get(void *data, u64 *val)
developerbaa67712021-12-21 17:01:26 +0800880+
881+ *val = dev->dbg.muru_onoff;
882+
883+- printk("mumimo ul:%d, mumimo dl:%d, ofdma ul:%d, ofdma dl:%d\n",
884++ printk("cert mumimo dl:%d, mumimo ul:%d, mumimo dl:%d, ofdma ul:%d, ofdma dl:%d\n",
885++ !!(dev->dbg.muru_onoff & MUMIMO_DL_CERT),
886+ !!(dev->dbg.muru_onoff & MUMIMO_UL),
887+ !!(dev->dbg.muru_onoff & MUMIMO_DL),
888+ !!(dev->dbg.muru_onoff & OFDMA_UL),
developer5f11e9e2022-03-10 15:03:47 +0800889+@@ -2449,8 +2450,8 @@ static int mt7915_muru_onoff_set(void *data, u64 val)
developerbaa67712021-12-21 17:01:26 +0800890+ {
891+ struct mt7915_dev *dev = data;
892+
893+- if (val > 15) {
894+- printk("Wrong value! The value is between 0 ~ 15.\n");
895++ if (val > 31) {
896++ printk("Wrong value! The value is between 0 ~ 31.\n");
897+ goto exit;
898+ }
899+
900+diff --git a/mt7915/vendor.c b/mt7915/vendor.c
developer5f11e9e2022-03-10 15:03:47 +0800901+index b94d787..7456c57 100644
developerbaa67712021-12-21 17:01:26 +0800902+--- a/mt7915/vendor.c
903++++ b/mt7915/vendor.c
904+@@ -22,6 +22,29 @@ csi_ctrl_policy[NUM_MTK_VENDOR_ATTRS_CSI_CTRL] = {
905+ [MTK_VENDOR_ATTR_CSI_CTRL_DATA] = { .type = NLA_NESTED },
906+ };
907+
908++static const struct nla_policy
909++wireless_ctrl_policy[NUM_MTK_VENDOR_ATTRS_WIRELESS_CTRL] = {
910++ [MTK_VENDOR_ATTR_WIRELESS_CTRL_FIXED_MCS] = {.type = NLA_U8 },
911++ [MTK_VENDOR_ATTR_WIRELESS_CTRL_OFDMA] = {.type = NLA_U8 },
912++ [MTK_VENDOR_ATTR_WIRELESS_CTRL_PPDU_TX_TYPE] = {.type = NLA_U8 },
913++ [MTK_VENDOR_ATTR_WIRELESS_CTRL_NUSERS_OFDMA] = {.type = NLA_U8 },
914++ [MTK_VENDOR_ATTR_WIRELESS_CTRL_MIMO] = {.type = NLA_U8 },
915++ [MTK_VENDOR_ATTR_WIRELESS_CTRL_BA_BUFFER_SIZE] = {.type = NLA_U16 },
916++ [MTK_VENDOR_ATTR_WIRELESS_CTRL_MU_EDCA] = {.type = NLA_U8 },
917++ [MTK_VENDOR_ATTR_WIRELESS_CTRL_CERT] = {.type = NLA_U8 },
918++};
919++
920++static const struct nla_policy
921++rfeature_ctrl_policy[NUM_MTK_VENDOR_ATTRS_RFEATURE_CTRL] = {
922++ [MTK_VENDOR_ATTR_RFEATURE_CTRL_HE_GI] = {.type = NLA_U8 },
923++ [MTK_VENDOR_ATTR_RFEATURE_CTRL_HE_LTF] = { .type = NLA_U8 },
924++ [MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE_CFG] = { .type = NLA_NESTED },
925++ [MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE_EN] = { .type = NLA_U8 },
926++ [MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE] = { .type = NLA_U8 },
927++ [MTK_VENDOR_ATTR_RFEATURE_CTRL_ACK_PLCY] = { .type = NLA_U8 },
928++ [MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TXBF] = { .type = NLA_U8 },
929++};
930++
931+ struct csi_null_tone {
932+ u8 start;
933+ u8 end;
developer5f11e9e2022-03-10 15:03:47 +0800934+@@ -777,6 +800,148 @@ mt7915_vendor_amnt_ctrl_dump(struct wiphy *wiphy, struct wireless_dev *wdev,
developerbaa67712021-12-21 17:01:26 +0800935+ return len + 1;
936+ }
937+
938++static int mt7915_vendor_rfeature_ctrl(struct wiphy *wiphy,
939++ struct wireless_dev *wdev,
940++ const void *data,
941++ int data_len)
942++{
943++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
944++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
945++ struct mt7915_dev *dev = phy->dev;
946++ struct nlattr *tb[NUM_MTK_VENDOR_ATTRS_RFEATURE_CTRL];
947++ int err;
948++ u32 val;
949++
950++ err = nla_parse(tb, MTK_VENDOR_ATTR_RFEATURE_CTRL_MAX, data, data_len,
951++ rfeature_ctrl_policy, NULL);
952++ if (err)
953++ return err;
954++
955++ val = CAPI_RFEATURE_CHANGED;
956++
957++ if (tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_HE_GI]) {
958++ val |= FIELD_PREP(RATE_CFG_MODE, RATE_PARAM_FIXED_GI)|
959++ FIELD_PREP(RATE_CFG_VAL, nla_get_u8(tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_HE_GI]));
960++ ieee80211_iterate_stations_atomic(hw, mt7915_capi_sta_rc_work, &val);
961++ ieee80211_queue_work(hw, &dev->rc_work);
962++ }
963++ else if (tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_HE_LTF]) {
964++ val |= FIELD_PREP(RATE_CFG_MODE, RATE_PARAM_FIXED_HE_LTF)|
965++ FIELD_PREP(RATE_CFG_VAL, nla_get_u8(tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_HE_LTF]));
966++ ieee80211_iterate_stations_atomic(hw, mt7915_capi_sta_rc_work, &val);
967++ ieee80211_queue_work(hw, &dev->rc_work);
968++ }
969++ else if (tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE_CFG]) {
970++ u8 enable, trig_type;
971++ int rem;
972++ struct nlattr *cur;
973++
974++ nla_for_each_nested(cur, tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE_CFG], rem) {
975++ switch(nla_type(cur)) {
976++ case MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE_EN:
977++ enable = nla_get_u8(cur);
978++ break;
979++ case MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE:
980++ trig_type = nla_get_u8(cur);
981++ break;
982++ default:
983++ return -EINVAL;
984++ };
985++ }
986++
987++ err = mt7915_mcu_set_rfeature_trig_type(phy, enable, trig_type);
988++ if (err)
989++ return err;
990++ }
991++ else if (tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_ACK_PLCY]) {
992++ u8 ack_policy;
993++
994++ ack_policy = nla_get_u8(tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_ACK_PLCY]);
995++#define HE_TB_PPDU_ACK 4
996++ switch (ack_policy) {
997++ case HE_TB_PPDU_ACK:
998++ return mt7915_mcu_set_mu_dl_ack_policy(phy, ack_policy);
999++ default:
1000++ return 0;
1001++ }
1002++ }
1003++ else if (tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TXBF]) {
1004++ u8 trig_txbf;
1005++
1006++ trig_txbf = nla_get_u8(tb[MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TXBF]);
1007++ /* CAPI only issues trig_txbf=disable */
1008++ }
1009++
1010++ return 0;
1011++}
1012++
1013++static int mt7915_vendor_wireless_ctrl(struct wiphy *wiphy,
1014++ struct wireless_dev *wdev,
1015++ const void *data,
1016++ int data_len)
1017++{
1018++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1019++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
1020++ struct mt7915_dev *dev = phy->dev;
1021++ struct nlattr *tb[NUM_MTK_VENDOR_ATTRS_WIRELESS_CTRL];
1022++ int err;
1023++ u8 val8;
1024++ u16 val16;
1025++ u32 val32;
1026++
1027++ err = nla_parse(tb, MTK_VENDOR_ATTR_WIRELESS_CTRL_MAX, data, data_len,
1028++ wireless_ctrl_policy, NULL);
1029++ if (err)
1030++ return err;
1031++
1032++ val32 = CAPI_WIRELESS_CHANGED;
1033++
1034++ if (tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_FIXED_MCS]) {
1035++ val32 &= ~CAPI_WIRELESS_CHANGED;
1036++ val32 |= CAPI_RFEATURE_CHANGED |
1037++ FIELD_PREP(RATE_CFG_MODE, RATE_PARAM_FIXED_MCS) |
1038++ FIELD_PREP(RATE_CFG_VAL, nla_get_u8(tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_FIXED_MCS]));
1039++ ieee80211_iterate_stations_atomic(hw, mt7915_capi_sta_rc_work, &val32);
1040++ ieee80211_queue_work(hw, &dev->rc_work);
1041++ } else if (tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_OFDMA]) {
1042++ val8 = nla_get_u8(tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_OFDMA]);
1043++ val32 |= FIELD_PREP(RATE_CFG_MODE, RATE_PARAM_FIXED_OFDMA) |
1044++ FIELD_PREP(RATE_CFG_VAL, val8);
1045++ ieee80211_iterate_active_interfaces_atomic(hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1046++ mt7915_set_wireless_vif, &val32);
1047++ if (val8 == 3) /* DL20and80 */
1048++ mt7915_mcu_set_dynalgo(phy, 1); /* Enable dynamic algo */
1049++ } else if (tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_BA_BUFFER_SIZE]) {
1050++ val16 = nla_get_u16(tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_BA_BUFFER_SIZE]);
1051++ hw->max_tx_aggregation_subframes = val16;
1052++ hw->max_rx_aggregation_subframes = val16;
1053++ } else if (tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_MU_EDCA]) {
1054++ val8 = nla_get_u8(tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_MU_EDCA]);
1055++ mt7915_mcu_set_mu_edca(phy, val8);
1056++ } else if (tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_PPDU_TX_TYPE]) {
1057++ val8 = nla_get_u8(tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_PPDU_TX_TYPE]);
1058++ mt7915_mcu_set_ppdu_tx_type(phy, val8);
1059++ } else if (tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_NUSERS_OFDMA]) {
1060++ val8 = nla_get_u8(tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_NUSERS_OFDMA]);
1061++ if (FIELD_GET(OFDMA_UL, dev->dbg.muru_onoff) == 1)
1062++ mt7915_mcu_set_nusers_ofdma(phy, MURU_UL_USER_CNT, val8);
1063++ else
1064++ mt7915_mcu_set_nusers_ofdma(phy, MURU_DL_USER_CNT, val8);
1065++ } else if (tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_MIMO]) {
1066++ val8 = nla_get_u8(tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_MIMO]);
1067++ val32 |= FIELD_PREP(RATE_CFG_MODE, RATE_PARAM_FIXED_MIMO) |
1068++ FIELD_PREP(RATE_CFG_VAL, val8);
1069++ ieee80211_iterate_active_interfaces_atomic(hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1070++ mt7915_set_wireless_vif, &val32);
1071++ } else if (tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_CERT]) {
1072++ val8 = nla_get_u8(tb[MTK_VENDOR_ATTR_WIRELESS_CTRL_CERT]);
1073++ mt7915_mcu_set_cert(phy, val8); /* Cert Enable for OMI */
1074++ mt7915_mcu_set_bypass_smthint(phy, val8); /* Cert bypass smooth interpolation */
1075++ }
1076++
1077++ return 0;
1078++}
1079++
developerbaa67712021-12-21 17:01:26 +08001080+ static const struct wiphy_vendor_command mt7915_vendor_commands[] = {
1081+ {
1082+ .info = {
developer5f11e9e2022-03-10 15:03:47 +08001083+@@ -801,6 +966,28 @@ static const struct wiphy_vendor_command mt7915_vendor_commands[] = {
developerbaa67712021-12-21 17:01:26 +08001084+ .dumpit = mt7915_vendor_amnt_ctrl_dump,
1085+ .policy = amnt_ctrl_policy,
1086+ .maxattr = MTK_VENDOR_ATTR_AMNT_CTRL_MAX,
developerbaa67712021-12-21 17:01:26 +08001087++ },
1088++ {
1089++ .info = {
1090++ .vendor_id = MTK_NL80211_VENDOR_ID,
1091++ .subcmd = MTK_NL80211_VENDOR_SUBCMD_RFEATURE_CTRL,
1092++ },
1093++ .flags = WIPHY_VENDOR_CMD_NEED_NETDEV |
1094++ WIPHY_VENDOR_CMD_NEED_RUNNING,
1095++ .doit = mt7915_vendor_rfeature_ctrl,
1096++ .policy = rfeature_ctrl_policy,
1097++ .maxattr = MTK_VENDOR_ATTR_RFEATURE_CTRL_MAX,
1098++ },
1099++ {
1100++ .info = {
1101++ .vendor_id = MTK_NL80211_VENDOR_ID,
1102++ .subcmd = MTK_NL80211_VENDOR_SUBCMD_WIRELESS_CTRL,
1103++ },
1104++ .flags = WIPHY_VENDOR_CMD_NEED_NETDEV |
1105++ WIPHY_VENDOR_CMD_NEED_RUNNING,
1106++ .doit = mt7915_vendor_wireless_ctrl,
1107++ .policy = wireless_ctrl_policy,
1108++ .maxattr = MTK_VENDOR_ATTR_WIRELESS_CTRL_MAX,
developer5f11e9e2022-03-10 15:03:47 +08001109+ }
developerbaa67712021-12-21 17:01:26 +08001110+ };
1111+
developerbaa67712021-12-21 17:01:26 +08001112+diff --git a/mt7915/vendor.h b/mt7915/vendor.h
developer5f11e9e2022-03-10 15:03:47 +08001113+index 976817f..1b08321 100644
developerbaa67712021-12-21 17:01:26 +08001114+--- a/mt7915/vendor.h
1115++++ b/mt7915/vendor.h
1116+@@ -6,6 +6,48 @@
1117+ enum mtk_nl80211_vendor_subcmds {
1118+ MTK_NL80211_VENDOR_SUBCMD_AMNT_CTRL = 0xae,
1119+ MTK_NL80211_VENDOR_SUBCMD_CSI_CTRL = 0xc2,
1120++ MTK_NL80211_VENDOR_SUBCMD_RFEATURE_CTRL = 0xc3,
1121++ MTK_NL80211_VENDOR_SUBCMD_WIRELESS_CTRL = 0xc4,
1122++};
1123++
1124++enum mtk_capi_control_changed {
1125++ CAPI_RFEATURE_CHANGED = BIT(16),
1126++ CAPI_WIRELESS_CHANGED = BIT(17),
1127++};
1128++
1129++enum mtk_vendor_attr_wireless_ctrl {
1130++ MTK_VENDOR_ATTR_WIRELESS_CTRL_UNSPEC,
1131++
1132++ MTK_VENDOR_ATTR_WIRELESS_CTRL_FIXED_MCS,
1133++ MTK_VENDOR_ATTR_WIRELESS_CTRL_OFDMA,
1134++ MTK_VENDOR_ATTR_WIRELESS_CTRL_PPDU_TX_TYPE,
1135++ MTK_VENDOR_ATTR_WIRELESS_CTRL_NUSERS_OFDMA,
1136++ MTK_VENDOR_ATTR_WIRELESS_CTRL_BA_BUFFER_SIZE,
1137++ MTK_VENDOR_ATTR_WIRELESS_CTRL_MIMO,
1138++ MTK_VENDOR_ATTR_WIRELESS_CTRL_CERT = 9,
1139++
1140++ MTK_VENDOR_ATTR_WIRELESS_CTRL_MU_EDCA, /* reserve */
1141++ /* keep last */
1142++ NUM_MTK_VENDOR_ATTRS_WIRELESS_CTRL,
1143++ MTK_VENDOR_ATTR_WIRELESS_CTRL_MAX =
1144++ NUM_MTK_VENDOR_ATTRS_WIRELESS_CTRL - 1
1145++};
1146++
1147++enum mtk_vendor_attr_rfeature_ctrl {
1148++ MTK_VENDOR_ATTR_RFEATURE_CTRL_UNSPEC,
1149++
1150++ MTK_VENDOR_ATTR_RFEATURE_CTRL_HE_GI,
1151++ MTK_VENDOR_ATTR_RFEATURE_CTRL_HE_LTF,
1152++ MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE_CFG,
1153++ MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE_EN,
1154++ MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TYPE,
1155++ MTK_VENDOR_ATTR_RFEATURE_CTRL_ACK_PLCY,
1156++ MTK_VENDOR_ATTR_RFEATURE_CTRL_TRIG_TXBF,
1157++
1158++ /* keep last */
1159++ NUM_MTK_VENDOR_ATTRS_RFEATURE_CTRL,
1160++ MTK_VENDOR_ATTR_RFEATURE_CTRL_MAX =
1161++ NUM_MTK_VENDOR_ATTRS_RFEATURE_CTRL - 1
1162+ };
1163+
1164+ enum mtk_vendor_attr_csi_ctrl {
1165+--
developer5f11e9e2022-03-10 15:03:47 +08001166+2.25.1
developerbaa67712021-12-21 17:01:26 +08001167+