blob: 7853f411fdb6d64a5a3b4825035cbd14f7f2edcf [file] [log] [blame]
developer5d148cb2023-06-02 13:08:11 +08001From e640a8767e5ab047b8a4c89041ee3872132ce38a Mon Sep 17 00:00:00 2001
2From: Sam Shih <sam.shih@mediatek.com>
3Date: Fri, 2 Jun 2023 13:06:03 +0800
4Subject: [PATCH] [basic-part][999-2013-clk-mtk-add-chg-shift-control.patch]
5
6---
7 drivers/clk/mediatek/clk-mtk.h | 1 +
8 drivers/clk/mediatek/clk-pll.c | 5 ++++-
9 2 files changed, 5 insertions(+), 1 deletion(-)
10
developer2cdaeb12022-10-04 20:25:05 +080011diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
developer5d148cb2023-06-02 13:08:11 +080012index c3d6756b0..d84c45d75 100644
developer2cdaeb12022-10-04 20:25:05 +080013--- a/drivers/clk/mediatek/clk-mtk.h
14+++ b/drivers/clk/mediatek/clk-mtk.h
15@@ -231,6 +231,7 @@ struct mtk_pll_data {
16 uint32_t pcw_reg;
17 int pcw_shift;
18 uint32_t pcw_chg_reg;
19+ int pcw_chg_shift;
20 const struct mtk_pll_div_table *div_table;
21 const char *parent_name;
22 };
23diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
developer5d148cb2023-06-02 13:08:11 +080024index f440f2cd0..db318fe1c 100644
developer2cdaeb12022-10-04 20:25:05 +080025--- a/drivers/clk/mediatek/clk-pll.c
26+++ b/drivers/clk/mediatek/clk-pll.c
27@@ -136,7 +136,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
28 pll->data->pcw_shift);
29 val |= pcw << pll->data->pcw_shift;
30 writel(val, pll->pcw_addr);
31- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
32+ if (pll->data->pcw_chg_shift)
33+ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
34+ else
35+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
36 writel(chg, pll->pcw_chg_addr);
37 if (pll->tuner_addr)
38 writel(val + 1, pll->tuner_addr);
developer5d148cb2023-06-02 13:08:11 +080039--
402.34.1
41