developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022 MediaTek Inc. |
| 3 | * Author: Xiufeng Li <Xiufeng.Li@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #ifndef _DT_BINDINGS_CLK_MT7988_H |
| 16 | #define _DT_BINDINGS_CLK_MT7988_H |
| 17 | |
| 18 | /* INFRACFG */ |
| 19 | |
| 20 | #define CK_INFRA_CK_F26M 0 |
| 21 | #define CK_INFRA_PWM_O 1 |
| 22 | #define CK_INFRA_PCIE_OCC_P0 2 |
| 23 | #define CK_INFRA_PCIE_OCC_P1 3 |
| 24 | #define CK_INFRA_PCIE_OCC_P2 4 |
| 25 | #define CK_INFRA_PCIE_OCC_P3 5 |
| 26 | #define CK_INFRA_133M_HCK 6 |
| 27 | #define CK_INFRA_133M_PHCK 7 |
| 28 | #define CK_INFRA_66M_PHCK 8 |
| 29 | #define CK_INFRA_FAUD_L_O 9 |
| 30 | #define CK_INFRA_FAUD_AUD_O 10 |
| 31 | #define CK_INFRA_FAUD_EG2_O 11 |
| 32 | #define CK_INFRA_I2C_O 12 |
| 33 | #define CK_INFRA_UART_O0 13 |
| 34 | #define CK_INFRA_UART_O1 14 |
| 35 | #define CK_INFRA_UART_O2 15 |
| 36 | #define CK_INFRA_NFI_O 16 |
| 37 | #define CK_INFRA_SPINFI_O 17 |
| 38 | #define CK_INFRA_SPI0_O 18 |
| 39 | #define CK_INFRA_SPI1_O 19 |
| 40 | #define CK_INFRA_LB_MUX_FRTC 20 |
| 41 | #define CK_INFRA_FRTC 21 |
| 42 | #define CK_INFRA_FMSDC400_O 22 |
| 43 | #define CK_INFRA_FMSDC2_HCK_OCC 23 |
| 44 | #define CK_INFRA_PERI_133M 24 |
| 45 | #define CK_INFRA_USB_O 25 |
| 46 | #define CK_INFRA_USB_O_P1 26 |
| 47 | #define CK_INFRA_USB_FRMCNT_O 27 |
| 48 | #define CK_INFRA_USB_FRMCNT_O_P1 28 |
| 49 | #define CK_INFRA_USB_XHCI_O 29 |
| 50 | #define CK_INFRA_USB_XHCI_O_P1 30 |
| 51 | #define CK_INFRA_USB_PIPE_O 31 |
| 52 | #define CK_INFRA_USB_PIPE_O_P1 32 |
| 53 | #define CK_INFRA_USB_UTMI_O 33 |
| 54 | #define CK_INFRA_USB_UTMI_O_P1 34 |
| 55 | #define CK_INFRA_PCIE_PIPE_OCC_P0 35 |
| 56 | #define CK_INFRA_PCIE_PIPE_OCC_P1 36 |
| 57 | #define CK_INFRA_PCIE_PIPE_OCC_P2 37 |
| 58 | #define CK_INFRA_PCIE_PIPE_OCC_P3 38 |
| 59 | #define CK_INFRA_F26M_O0 39 |
| 60 | #define CK_INFRA_F26M_O1 40 |
| 61 | #define CK_INFRA_133M_MCK 41 |
| 62 | #define CK_INFRA_66M_MCK 42 |
| 63 | #define CK_INFRA_PERI_66M_O 43 |
| 64 | #define CK_INFRA_USB_SYS_O 44 |
| 65 | #define CK_INFRA_USB_SYS_O_P1 45 |
| 66 | #define CLK_INFRA_NR_CLK 46 |
| 67 | |
| 68 | |
| 69 | /* INFRACFG_AO */ |
| 70 | |
| 71 | #define CK_INFRA_MUX_UART0_SEL 0 |
| 72 | #define CK_INFRA_MUX_UART1_SEL 1 |
| 73 | #define CK_INFRA_MUX_UART2_SEL 2 |
| 74 | #define CK_INFRA_MUX_SPI0_SEL 3 |
| 75 | #define CK_INFRA_MUX_SPI1_SEL 4 |
| 76 | #define CK_INFRA_MUX_SPI2_SEL 5 |
| 77 | #define CK_INFRA_PWM_SEL 6 |
| 78 | #define CK_INFRA_PWM_CK1_SEL 7 |
| 79 | #define CK_INFRA_PWM_CK2_SEL 8 |
| 80 | #define CK_INFRA_PWM_CK3_SEL 9 |
| 81 | #define CK_INFRA_PWM_CK4_SEL 10 |
| 82 | #define CK_INFRA_PWM_CK5_SEL 11 |
| 83 | #define CK_INFRA_PWM_CK6_SEL 12 |
| 84 | #define CK_INFRA_PWM_CK7_SEL 13 |
| 85 | #define CK_INFRA_PWM_CK8_SEL 14 |
| 86 | #define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 |
| 87 | #define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 |
| 88 | #define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 |
| 89 | #define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 |
| 90 | #define CK_INFRA_66M_GPT_BCK 19 |
| 91 | #define CK_INFRA_66M_PWM_HCK 20 |
| 92 | #define CK_INFRA_66M_PWM_BCK 21 |
| 93 | #define CK_INFRA_66M_PWM_CK1 22 |
| 94 | #define CK_INFRA_66M_PWM_CK2 23 |
| 95 | #define CK_INFRA_66M_PWM_CK3 24 |
| 96 | #define CK_INFRA_66M_PWM_CK4 25 |
| 97 | #define CK_INFRA_66M_PWM_CK5 26 |
| 98 | #define CK_INFRA_66M_PWM_CK6 27 |
| 99 | #define CK_INFRA_66M_PWM_CK7 28 |
| 100 | #define CK_INFRA_66M_PWM_CK8 29 |
| 101 | #define CK_INFRA_133M_CQDMA_BCK 30 |
| 102 | #define CK_INFRA_66M_AUD_SLV_BCK 31 |
| 103 | #define CK_INFRA_AUD_26M 32 |
| 104 | #define CK_INFRA_AUD_L 33 |
| 105 | #define CK_INFRA_AUD_AUD 34 |
| 106 | #define CK_INFRA_AUD_EG2 35 |
| 107 | #define CK_INFRA_DRAMC_F26M 36 |
| 108 | #define CK_INFRA_133M_DBG_ACKM 37 |
| 109 | #define CK_INFRA_66M_AP_DMA_BCK 38 |
| 110 | #define CK_INFRA_66M_SEJ_BCK 39 |
| 111 | #define CK_INFRA_PRE_CK_SEJ_F13M 40 |
developer | b620682 | 2022-11-25 14:16:44 +0800 | [diff] [blame] | 112 | #define CK_INFRA_26M_THERM_SYSTEM 41 |
| 113 | #define CK_INFRA_I2C_BCK 42 |
| 114 | #define CK_INFRA_52M_UART0_CK 43 |
| 115 | #define CK_INFRA_52M_UART1_CK 44 |
| 116 | #define CK_INFRA_52M_UART2_CK 45 |
| 117 | #define CK_INFRA_NFI 46 |
| 118 | #define CK_INFRA_SPINFI 47 |
| 119 | #define CK_INFRA_66M_NFI_HCK 48 |
| 120 | #define CK_INFRA_104M_SPI0 49 |
| 121 | #define CK_INFRA_104M_SPI1 50 |
| 122 | #define CK_INFRA_104M_SPI2_BCK 51 |
| 123 | #define CK_INFRA_66M_SPI0_HCK 52 |
| 124 | #define CK_INFRA_66M_SPI1_HCK 53 |
| 125 | #define CK_INFRA_66M_SPI2_HCK 54 |
| 126 | #define CK_INFRA_66M_FLASHIF_AXI 55 |
| 127 | #define CK_INFRA_RTC 56 |
| 128 | #define CK_INFRA_26M_ADC_BCK 57 |
| 129 | #define CK_INFRA_RC_ADC 58 |
| 130 | #define CK_INFRA_MSDC400 59 |
| 131 | #define CK_INFRA_MSDC2_HCK 60 |
| 132 | #define CK_INFRA_133M_MSDC_0_HCK 61 |
| 133 | #define CK_INFRA_66M_MSDC_0_HCK 62 |
| 134 | #define CK_INFRA_133M_CPUM_BCK 63 |
| 135 | #define CK_INFRA_BIST2FPC 64 |
| 136 | #define CK_INFRA_I2C_X16W_MCK_CK_P1 65 |
| 137 | #define CK_INFRA_I2C_X16W_PCK_CK_P1 66 |
| 138 | #define CK_INFRA_133M_USB_HCK 67 |
| 139 | #define CK_INFRA_133M_USB_HCK_CK_P1 68 |
| 140 | #define CK_INFRA_66M_USB_HCK 69 |
| 141 | #define CK_INFRA_66M_USB_HCK_CK_P1 70 |
| 142 | #define CK_INFRA_USB_SYS 71 |
| 143 | #define CK_INFRA_USB_SYS_CK_P1 72 |
| 144 | #define CK_INFRA_USB_REF 73 |
| 145 | #define CK_INFRA_USB_CK_P1 74 |
| 146 | #define CK_INFRA_USB_FRMCNT 75 |
| 147 | #define CK_INFRA_USB_FRMCNT_CK_P1 76 |
| 148 | #define CK_INFRA_USB_PIPE 77 |
| 149 | #define CK_INFRA_USB_PIPE_CK_P1 78 |
| 150 | #define CK_INFRA_USB_UTMI 79 |
| 151 | #define CK_INFRA_USB_UTMI_CK_P1 80 |
| 152 | #define CK_INFRA_USB_XHCI 81 |
| 153 | #define CK_INFRA_USB_XHCI_CK_P1 82 |
| 154 | #define CK_INFRA_PCIE_GFMUX_TL_P0 83 |
| 155 | #define CK_INFRA_PCIE_GFMUX_TL_P1 84 |
| 156 | #define CK_INFRA_PCIE_GFMUX_TL_P2 85 |
| 157 | #define CK_INFRA_PCIE_GFMUX_TL_P3 86 |
| 158 | #define CK_INFRA_PCIE_PIPE_P0 87 |
| 159 | #define CK_INFRA_PCIE_PIPE_P1 88 |
| 160 | #define CK_INFRA_PCIE_PIPE_P2 89 |
| 161 | #define CK_INFRA_PCIE_PIPE_P3 90 |
| 162 | #define CK_INFRA_133M_PCIE_CK_P0 91 |
| 163 | #define CK_INFRA_133M_PCIE_CK_P1 92 |
| 164 | #define CK_INFRA_133M_PCIE_CK_P2 93 |
| 165 | #define CK_INFRA_133M_PCIE_CK_P3 94 |
| 166 | #define CK_INFRA_PCIE_PERI_26M_CK_P0 95 |
| 167 | #define CK_INFRA_PCIE_PERI_26M_CK_P1 96 |
| 168 | #define CK_INFRA_PCIE_PERI_26M_CK_P2 97 |
| 169 | #define CK_INFRA_PCIE_PERI_26M_CK_P3 98 |
| 170 | #define CLK_INFRA_AO_NR_CLK 99 |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 171 | |
| 172 | /* TOPCKGEN */ |
| 173 | |
| 174 | #define CK_TOP_NETSYS_SEL 0 |
| 175 | #define CK_TOP_NETSYS_500M_SEL 1 |
| 176 | #define CK_TOP_NETSYS_2X_SEL 2 |
| 177 | #define CK_TOP_NETSYS_GSW_SEL 3 |
| 178 | #define CK_TOP_ETH_GMII_SEL 4 |
| 179 | #define CK_TOP_NETSYS_MCU_SEL 5 |
| 180 | #define CK_TOP_NETSYS_PAO_2X_SEL 6 |
| 181 | #define CK_TOP_EIP197_SEL 7 |
| 182 | #define CK_TOP_AXI_INFRA_SEL 8 |
| 183 | #define CK_TOP_UART_SEL 9 |
| 184 | #define CK_TOP_EMMC_250M_SEL 10 |
| 185 | #define CK_TOP_EMMC_400M_SEL 11 |
| 186 | #define CK_TOP_SPI_SEL 12 |
| 187 | #define CK_TOP_SPIM_MST_SEL 13 |
| 188 | #define CK_TOP_NFI1X_SEL 14 |
| 189 | #define CK_TOP_SPINFI_SEL 15 |
| 190 | #define CK_TOP_PWM_SEL 16 |
| 191 | #define CK_TOP_I2C_SEL 17 |
| 192 | #define CK_TOP_PCIE_MBIST_250M_SEL 18 |
| 193 | #define CK_TOP_PEXTP_TL_SEL 19 |
| 194 | #define CK_TOP_PEXTP_TL_P1_SEL 20 |
| 195 | #define CK_TOP_PEXTP_TL_P2_SEL 21 |
| 196 | #define CK_TOP_PEXTP_TL_P3_SEL 22 |
| 197 | #define CK_TOP_USB_SYS_SEL 23 |
| 198 | #define CK_TOP_USB_SYS_P1_SEL 24 |
| 199 | #define CK_TOP_USB_XHCI_SEL 25 |
| 200 | #define CK_TOP_USB_XHCI_P1_SEL 26 |
| 201 | #define CK_TOP_USB_FRMCNT_SEL 27 |
| 202 | #define CK_TOP_USB_FRMCNT_P1_SEL 28 |
| 203 | #define CK_TOP_AUD_SEL 29 |
| 204 | #define CK_TOP_A1SYS_SEL 30 |
| 205 | #define CK_TOP_AUD_L_SEL 31 |
| 206 | #define CK_TOP_A_TUNER_SEL 32 |
| 207 | #define CK_TOP_SSPXTP_SEL 33 |
| 208 | #define CK_TOP_USB_PHY_SEL 34 |
| 209 | #define CK_TOP_USXGMII_SBUS_0_SEL 35 |
| 210 | #define CK_TOP_USXGMII_SBUS_1_SEL 36 |
| 211 | #define CK_TOP_SGM_0_SEL 37 |
| 212 | #define CK_TOP_SGM_SBUS_0_SEL 38 |
| 213 | #define CK_TOP_SGM_1_SEL 39 |
| 214 | #define CK_TOP_SGM_SBUS_1_SEL 40 |
| 215 | #define CK_TOP_XFI_PHY_0_XTAL_SEL 41 |
| 216 | #define CK_TOP_XFI_PHY_1_XTAL_SEL 42 |
| 217 | #define CK_TOP_SYSAXI_SEL 43 |
| 218 | #define CK_TOP_SYSAPB_SEL 44 |
| 219 | #define CK_TOP_ETH_REFCK_50M_SEL 45 |
| 220 | #define CK_TOP_ETH_SYS_200M_SEL 46 |
| 221 | #define CK_TOP_ETH_SYS_SEL 47 |
| 222 | #define CK_TOP_ETH_XGMII_SEL 48 |
| 223 | #define CK_TOP_BUS_TOPS_SEL 49 |
| 224 | #define CK_TOP_NPU_TOPS_SEL 50 |
| 225 | #define CK_TOP_DRAMC_SEL 51 |
| 226 | #define CK_TOP_DRAMC_MD32_SEL 52 |
| 227 | #define CK_TOP_INFRA_F26M_SEL 53 |
| 228 | #define CK_TOP_PEXTP_P0_SEL 54 |
| 229 | #define CK_TOP_PEXTP_P1_SEL 55 |
| 230 | #define CK_TOP_PEXTP_P2_SEL 56 |
| 231 | #define CK_TOP_PEXTP_P3_SEL 57 |
| 232 | #define CK_TOP_DA_XTP_GLB_P0_SEL 58 |
| 233 | #define CK_TOP_DA_XTP_GLB_P1_SEL 59 |
| 234 | #define CK_TOP_DA_XTP_GLB_P2_SEL 60 |
| 235 | #define CK_TOP_DA_XTP_GLB_P3_SEL 61 |
| 236 | #define CK_TOP_CKM_SEL 62 |
| 237 | #define CK_TOP_DA_SELM_XTAL_SEL 63 |
| 238 | #define CK_TOP_PEXTP_SEL 64 |
| 239 | #define CK_TOP_TOPS_P2_26M_SEL 65 |
| 240 | #define CK_TOP_MCUSYS_BACKUP_625M_SEL 66 |
| 241 | #define CK_TOP_NETSYS_SYNC_250M_SEL 67 |
| 242 | #define CK_TOP_MACSEC_SEL 68 |
| 243 | #define CK_TOP_NETSYS_TOPS_400M_SEL 69 |
| 244 | #define CK_TOP_NETSYS_PPEFB_250M_SEL 70 |
| 245 | #define CK_TOP_NETSYS_WARP_SEL 71 |
| 246 | #define CK_TOP_ETH_MII_SEL 72 |
| 247 | #define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 73 |
| 248 | #define CK_TOP_CB_CKSQ_40M 74 |
| 249 | #define CK_TOP_CB_M_416M 75 |
| 250 | #define CK_TOP_CB_M_D2 76 |
| 251 | #define CK_TOP_M_D3_D2 77 |
| 252 | #define CK_TOP_CB_M_D4 78 |
| 253 | #define CK_TOP_CB_M_D8 79 |
| 254 | #define CK_TOP_M_D8_D2 80 |
| 255 | #define CK_TOP_CB_MM_720M 81 |
| 256 | #define CK_TOP_CB_MM_D2 82 |
| 257 | #define CK_TOP_CB_MM_D3_D5 83 |
| 258 | #define CK_TOP_CB_MM_D4 84 |
| 259 | #define CK_TOP_MM_D6_D2 85 |
| 260 | #define CK_TOP_CB_MM_D8 86 |
| 261 | #define CK_TOP_CB_APLL2_196M 87 |
| 262 | #define CK_TOP_CB_APLL2_D4 88 |
| 263 | #define CK_TOP_CB_NET1_D4 89 |
| 264 | #define CK_TOP_CB_NET1_D5 90 |
| 265 | #define CK_TOP_NET1_D5_D2 91 |
| 266 | #define CK_TOP_NET1_D5_D4 92 |
| 267 | #define CK_TOP_CB_NET1_D8 93 |
| 268 | #define CK_TOP_NET1_D8_D2 94 |
| 269 | #define CK_TOP_NET1_D8_D4 95 |
| 270 | #define CK_TOP_NET1_D8_D8 96 |
| 271 | #define CK_TOP_NET1_D8_D16 97 |
| 272 | #define CK_TOP_CB_NET2_800M 98 |
| 273 | #define CK_TOP_CB_NET2_D2 99 |
| 274 | #define CK_TOP_CB_NET2_D4 100 |
| 275 | #define CK_TOP_NET2_D4_D4 101 |
| 276 | #define CK_TOP_NET2_D4_D8 102 |
| 277 | #define CK_TOP_CB_NET2_D6 103 |
| 278 | #define CK_TOP_CB_NET2_D8 104 |
| 279 | #define CK_TOP_CB_WEDMCU_208M 105 |
| 280 | #define CK_TOP_CB_SGM_325M 106 |
| 281 | #define CK_TOP_CB_NETSYS_850M 107 |
| 282 | #define CK_TOP_CB_MSDC_400M 108 |
| 283 | #define CK_TOP_CKSQ_40M_D2 109 |
| 284 | #define CK_TOP_CB_RTC_32K 110 |
| 285 | #define CK_TOP_CB_RTC_32P7K 111 |
| 286 | #define CK_TOP_INFRA_F32K 112 |
| 287 | #define CK_TOP_CKSQ_SRC 113 |
| 288 | #define CK_TOP_NETSYS_2X 114 |
| 289 | #define CK_TOP_NETSYS_GSW 115 |
| 290 | #define CK_TOP_NETSYS_WED_MCU 116 |
| 291 | #define CK_TOP_EIP197 117 |
| 292 | #define CK_TOP_EMMC_250M 118 |
| 293 | #define CK_TOP_EMMC_400M 119 |
| 294 | #define CK_TOP_SPI 120 |
| 295 | #define CK_TOP_SPIM_MST 121 |
| 296 | #define CK_TOP_NFI1X 122 |
| 297 | #define CK_TOP_SPINFI_BCK 123 |
| 298 | #define CK_TOP_I2C_BCK 124 |
| 299 | #define CK_TOP_USB_SYS 125 |
| 300 | #define CK_TOP_USB_SYS_P1 126 |
| 301 | #define CK_TOP_USB_XHCI 127 |
| 302 | #define CK_TOP_USB_XHCI_P1 128 |
| 303 | #define CK_TOP_USB_FRMCNT 129 |
| 304 | #define CK_TOP_USB_FRMCNT_P1 130 |
| 305 | #define CK_TOP_AUD 131 |
| 306 | #define CK_TOP_A1SYS 132 |
| 307 | #define CK_TOP_AUD_L 133 |
| 308 | #define CK_TOP_A_TUNER 134 |
| 309 | #define CK_TOP_SYSAXI 135 |
| 310 | #define CK_TOP_INFRA_F26M 136 |
| 311 | #define CK_TOP_USB_REF 137 |
| 312 | #define CK_TOP_USB_CK_P1 138 |
| 313 | #define CK_TOP_AUD_I2S_M 139 |
| 314 | #define CLK_TOP_NR_CLK 140 |
| 315 | |
| 316 | /* APMIXEDSYS */ |
| 317 | |
| 318 | #define CK_APMIXED_NETSYSPLL 0 |
| 319 | #define CK_APMIXED_MPLL 1 |
| 320 | #define CK_APMIXED_MMPLL 2 |
| 321 | #define CK_APMIXED_APLL2 3 |
| 322 | #define CK_APMIXED_NET1PLL 4 |
| 323 | #define CK_APMIXED_NET2PLL 5 |
| 324 | #define CK_APMIXED_WEDMCUPLL 6 |
| 325 | #define CK_APMIXED_SGMPLL 7 |
| 326 | #define CK_APMIXED_ARM_B 8 |
| 327 | #define CK_APMIXED_CCIPLL2_B 9 |
| 328 | #define CK_APMIXED_USXGMIIPLL 10 |
| 329 | #define CK_APMIXED_MSDCPLL 11 |
| 330 | #define CLK_APMIXED_NR_CLK 12 |
| 331 | |
| 332 | /* MCUSYS */ |
| 333 | |
| 334 | #define CK_MCU_BUS_DIV_SEL 0 |
| 335 | #define CK_MCU_ARM_DIV_SEL 1 |
| 336 | #define CLK_MCU_NR_CLK 2 |
| 337 | |
| 338 | /* ETHDMA */ |
| 339 | |
| 340 | #define CK_ETHDMA_XGP1_EN 0 |
| 341 | #define CK_ETHDMA_XGP2_EN 1 |
| 342 | #define CK_ETHDMA_XGP3_EN 2 |
| 343 | #define CK_ETHDMA_FE_EN 3 |
| 344 | #define CK_ETHDMA_GP2_EN 4 |
| 345 | #define CK_ETHDMA_GP1_EN 5 |
| 346 | #define CK_ETHDMA_GP3_EN 6 |
| 347 | #define CK_ETHDMA_ESW_EN 7 |
| 348 | #define CK_ETHDMA_CRYPT0_EN 8 |
| 349 | #define CLK_ETHDMA_NR_CLK 9 |
| 350 | /* SGMIISYS_0 */ |
| 351 | |
| 352 | #define CK_SGM0_TX_EN 0 |
| 353 | #define CK_SGM0_RX_EN 1 |
| 354 | #define CLK_SGMII0_NR_CLK 2 |
| 355 | |
| 356 | /* SGMIISYS_1 */ |
| 357 | |
| 358 | #define CK_SGM1_TX_EN 0 |
| 359 | #define CK_SGM1_RX_EN 1 |
| 360 | #define CLK_SGMII1_NR_CLK 2 |
| 361 | |
| 362 | /* ETHWARP */ |
| 363 | |
| 364 | #define CK_ETHWARP_WOCPU2_EN 0 |
| 365 | #define CK_ETHWARP_WOCPU1_EN 1 |
| 366 | #define CK_ETHWARP_WOCPU0_EN 2 |
| 367 | #define CLK_ETHWARP_NR_CLK 3 |
| 368 | |
| 369 | #endif /* _DT_BINDINGS_CLK_MT7988_H */ |
| 370 | |