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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / f6302352f5439c041e900af466926053412b0aa5 / . / autobuild_mac80211_release / mt7988_mt7996_mac80211 / package / kernel / mt76 / patches / 2013-wifi-mt76-mt7996-support-TX-RX-for-Kite-without-WED-.patch
blob: 8dd2d61fe8e1b9a8f6774f32c1b281198cdfeb46 [file] [log] [blame]
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]1From bd93ad7026e316307453438f4b7bce59e30bf03e Mon Sep 17 00:00:00 2001
2From: Benjamin Lin <benjamin-jw.lin@mediatek.com>
3Date: Wed, 7 Jun 2023 14:11:28 +0800
4Subject: [PATCH 77/98] wifi: mt76: mt7996: support TX/RX for Kite without WED
5 and RRO
6
7Signed-off-by: Benjamin Lin <benjamin-jw.lin@mediatek.com>
8Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
9---
10 mt76_connac3_mac.h | 3 ++-
11 mt7996/dma.c | 61 +++++++++++++++++++++++++++++++++++++---------
12 mt7996/init.c | 10 ++++++--
13 mt7996/mac.c | 7 ++++--
14 mt7996/mt7996.h | 4 +--
15 mt7996/regs.h | 4 +--
16 6 files changed, 68 insertions(+), 21 deletions(-)
17
18diff --git a/mt76_connac3_mac.h b/mt76_connac3_mac.h
19index 7402de2..3fd46ae 100644
20--- a/mt76_connac3_mac.h
21+++ b/mt76_connac3_mac.h
22@@ -244,7 +244,8 @@ enum tx_mgnt_type {
23 #define MT_TXD6_TX_RATE GENMASK(21, 16)
24 #define MT_TXD6_TIMESTAMP_OFS_EN BIT(15)
25 #define MT_TXD6_TIMESTAMP_OFS_IDX GENMASK(14, 10)
26-#define MT_TXD6_MSDU_CNT GENMASK(9, 4)
27+#define MT_TXD6_MSDU_CNT_MT7996 GENMASK(9, 4)
28+#define MT_TXD6_MSDU_CNT_MT7992 GENMASK(15, 10)
29 #define MT_TXD6_DIS_MAT BIT(3)
30 #define MT_TXD6_DAS BIT(2)
31 #define MT_TXD6_AMSDU_CAP BIT(1)
32diff --git a/mt7996/dma.c b/mt7996/dma.c
33index b2c7ae6..1163550 100644
34--- a/mt7996/dma.c
35+++ b/mt7996/dma.c
36@@ -57,13 +57,21 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
37 RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7996_RXQ_MCU_WM);
38 RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7996_RXQ_MCU_WA);
39
40- /* band0/band1 */
41+ /* MT7996 band0/band1
42+ * MT7992 band0
43+ */
44 RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7996_RXQ_BAND0);
45 RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN, MT7996_RXQ_MCU_WA_MAIN);
46
47- /* band2 */
48- RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2);
49- RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI);
50+ if (is_mt7996(&dev->mt76)) {
51+ /* MT7996 band2 */
52+ RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2);
53+ RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI);
54+ } else {
55+ /* MT7992 band1 */
56+ RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, MT7996_RXQ_BAND1);
57+ RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT, MT7996_RXQ_MCU_WA_EXT);
58+ }
59
60 if (dev->has_rro) {
61 /* band0 */
62@@ -90,8 +98,12 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
63
64 /* data tx queue */
65 TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
66- TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
67- TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);
68+ if (is_mt7996(&dev->mt76)) {
69+ TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
70+ TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);
71+ } else {
72+ TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);
73+ }
74
75 /* mcu tx queue */
76 MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7996_TXQ_MCU_WM);
77@@ -123,10 +135,15 @@ static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs)
78 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x2));
79 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x2));
80 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x2));
81- mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x2));
82+ if (is_mt7996(&dev->mt76))
83+ mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x2));
84+ else
85+ mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1_WA) + ofs, PREFETCH(0x2));
86 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x10));
87- mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x10));
88-
89+ if (is_mt7996(&dev->mt76))
90+ mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x10));
91+ else
92+ mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1) + ofs, PREFETCH(0x10));
93 if (dev->has_rro) {
94 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_RRO_BAND0) + ofs,
95 PREFETCH(0x10));
96@@ -488,7 +505,7 @@ int mt7996_dma_init(struct mt7996_dev *dev)
97 if (ret)
98 return ret;
99
100- /* rx data queue for band0 and band1 */
101+ /* rx data queue for band0 and MT7996 band1 */
102 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
103 dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(0);
104 dev->mt76.q_rx[MT_RXQ_MAIN].wed = wed;
105@@ -517,7 +534,7 @@ int mt7996_dma_init(struct mt7996_dev *dev)
106 return ret;
107
108 if (mt7996_band_valid(dev, MT_BAND2)) {
109- /* rx data queue for band2 */
110+ /* rx data queue for MT7996 band2 */
111 rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs;
112 if (mtk_wed_device_active(wed_hif2) && mtk_wed_get_rx_capa(wed_hif2)) {
113 dev->mt76.q_rx[MT_RXQ_BAND2].flags = MT_WED_Q_RX(0);
114@@ -531,7 +548,7 @@ int mt7996_dma_init(struct mt7996_dev *dev)
115 if (ret)
116 return ret;
117
118- /* tx free notify event from WA for band2
119+ /* tx free notify event from WA for MT7996 band2
120 * use pcie0's rx ring3, but, redirect pcie0 rx ring3 interrupt to pcie1
121 */
122 if (mtk_wed_device_active(wed_hif2) && !dev->has_rro) {
123@@ -546,6 +563,26 @@ int mt7996_dma_init(struct mt7996_dev *dev)
124 MT_RXQ_RING_BASE(MT_RXQ_BAND2_WA));
125 if (ret)
126 return ret;
127+ } else if (mt7996_band_valid(dev, MT_BAND1)) {
128+ /* rx data queue for MT7992 band1 */
129+ rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs;
130+ ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1],
131+ MT_RXQ_ID(MT_RXQ_BAND1),
132+ MT7996_RX_RING_SIZE,
133+ MT_RX_BUF_SIZE,
134+ rx_base);
135+ if (ret)
136+ return ret;
137+
138+ /* tx free notify event from WA for MT7992 band1 */
139+ rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs;
140+ ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],
141+ MT_RXQ_ID(MT_RXQ_BAND1_WA),
142+ MT7996_RX_MCU_RING_SIZE,
143+ MT_RX_BUF_SIZE,
144+ rx_base);
145+ if (ret)
146+ return ret;
147 }
148
149 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed) &&
150diff --git a/mt7996/init.c b/mt7996/init.c
151index 20e14e7..d539af0 100644
152--- a/mt7996/init.c
153+++ b/mt7996/init.c
154@@ -505,7 +505,12 @@ void mt7996_mac_init(struct mt7996_dev *dev)
155 mt76_rmw_field(dev, MT_DMA_TCRF1(2), MT_DMA_TCRF1_QIDX, 0);
156
157 /* rro module init */
158- mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2);
159+ if (is_mt7996(&dev->mt76))
160+ mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2);
161+ else
162+ mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE,
163+ dev->hif2 ? 7 : 0);
164+
165 if (dev->has_rro) {
166 u16 timeout;
167
168@@ -562,7 +567,8 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy,
169 if (phy)
170 return 0;
171
172- if (band == MT_BAND2 && dev->hif2) {
173+ if ((is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) ||
174+ (is_mt7992(&dev->mt76) && band == MT_BAND1 && dev->hif2)) {
175 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
176 wed = &dev->mt76.mmio.wed_hif2;
177 }
178diff --git a/mt7996/mac.c b/mt7996/mac.c
179index 22cff71..a92298d 100644
180--- a/mt7996/mac.c
181+++ b/mt7996/mac.c
182@@ -878,8 +878,11 @@ void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
183 val |= MT_TXD5_TX_STATUS_HOST;
184 txwi[5] = cpu_to_le32(val);
185
186- val = MT_TXD6_DIS_MAT | MT_TXD6_DAS |
187- FIELD_PREP(MT_TXD6_MSDU_CNT, 1);
188+ val = MT_TXD6_DIS_MAT | MT_TXD6_DAS;
189+ if (is_mt7996(&dev->mt76))
190+ val |= FIELD_PREP(MT_TXD6_MSDU_CNT_MT7996, 1);
191+ else
192+ val |= FIELD_PREP(MT_TXD6_MSDU_CNT_MT7992, 1);
193 txwi[6] = cpu_to_le32(val);
194 txwi[7] = 0;
195
196diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
197index 06e00f4..4333d51 100644
198--- a/mt7996/mt7996.h
199+++ b/mt7996/mt7996.h
200@@ -152,10 +152,10 @@ enum mt7996_rxq_id {
201 MT7996_RXQ_MCU_WM = 0,
202 MT7996_RXQ_MCU_WA,
203 MT7996_RXQ_MCU_WA_MAIN = 2,
204- MT7996_RXQ_MCU_WA_EXT = 2,/* unused */
205+ MT7996_RXQ_MCU_WA_EXT = 3, /* Only used by MT7992. */
206 MT7996_RXQ_MCU_WA_TRI = 3,
207 MT7996_RXQ_BAND0 = 4,
208- MT7996_RXQ_BAND1 = 4,/* unused */
209+ MT7996_RXQ_BAND1 = 5, /* Only used by MT7992. */
210 MT7996_RXQ_BAND2 = 5,
211 MT7996_RXQ_RRO_BAND0 = 8,
212 MT7996_RXQ_RRO_BAND1 = 8,/* unused */
213diff --git a/mt7996/regs.h b/mt7996/regs.h
214index 77a2f9d..c9e90e3 100644
215--- a/mt7996/regs.h
216+++ b/mt7996/regs.h
217@@ -491,12 +491,12 @@ enum offs_rev {
218 #define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204)
219
220 #define MT_INT_RX_DONE_BAND0 BIT(12)
221-#define MT_INT_RX_DONE_BAND1 BIT(12)
222+#define MT_INT_RX_DONE_BAND1 BIT(13) /* Only used by MT7992. */
223 #define MT_INT_RX_DONE_BAND2 BIT(13)
224 #define MT_INT_RX_DONE_WM BIT(0)
225 #define MT_INT_RX_DONE_WA BIT(1)
226 #define MT_INT_RX_DONE_WA_MAIN BIT(2)
227-#define MT_INT_RX_DONE_WA_EXT BIT(2)
228+#define MT_INT_RX_DONE_WA_EXT BIT(3) /* Only used by MT7992. */
229 #define MT_INT_RX_DONE_WA_TRI BIT(3)
230 #define MT_INT_RX_TXFREE_MAIN BIT(17)
231 #define MT_INT_RX_TXFREE_TRI BIT(15)
232--
2332.18.0
234