developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020 MediaTek Inc. |
| 3 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 17 | #include <dt-bindings/phy/phy.h> |
| 18 | #include <dt-bindings/reset/ti-syscon.h> |
| 19 | / { |
| 20 | compatible = "mediatek,mt7986-fpga"; |
| 21 | interrupt-parent = <&gic>; |
| 22 | #address-cells = <2>; |
| 23 | #size-cells = <2>; |
| 24 | cpus { |
| 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; |
| 27 | cpu@0 { |
| 28 | device_type = "cpu"; |
| 29 | compatible = "arm,cortex-a53"; |
| 30 | enable-method = "psci"; |
| 31 | reg = <0x0>; |
| 32 | }; |
| 33 | |
| 34 | cpu@1 { |
| 35 | device_type = "cpu"; |
| 36 | compatible = "arm,cortex-a53"; |
| 37 | enable-method = "psci"; |
| 38 | reg = <0x1>; |
| 39 | }; |
| 40 | }; |
| 41 | |
| 42 | wed: wed@15010000 { |
| 43 | compatible = "mediatek,wed"; |
| 44 | wed_num = <2>; |
| 45 | /* add this property for wed get the pci slot number. */ |
| 46 | pci_slot_map = <0>, <1>; |
| 47 | reg = <0 0x15010000 0 0x1000>, |
| 48 | <0 0x15011000 0 0x1000>; |
| 49 | interrupt-parent = <&gic>; |
| 50 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 51 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 52 | }; |
| 53 | |
| 54 | wed2: wed2@15011000 { |
| 55 | compatible = "mediatek,wed2"; |
| 56 | wed_num = <2>; |
| 57 | reg = <0 0x15010000 0 0x1000>, |
| 58 | <0 0x15011000 0 0x1000>; |
| 59 | interrupt-parent = <&gic>; |
| 60 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 61 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 62 | }; |
| 63 | |
| 64 | wdma: wdma@15104800 { |
| 65 | compatible = "mediatek,wed-wdma"; |
| 66 | reg = <0 0x15104800 0 0x400>, |
| 67 | <0 0x15104c00 0 0x400>; |
| 68 | }; |
| 69 | |
| 70 | ap2woccif: ap2woccif@151A5000 { |
| 71 | compatible = "mediatek,ap2woccif"; |
| 72 | reg = <0 0x151A5000 0 0x1000>, |
| 73 | <0 0x151AD000 0 0x1000>; |
| 74 | interrupt-parent = <&gic>; |
| 75 | interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; |
| 77 | }; |
| 78 | |
| 79 | wocpu0_ilm: wocpu0_ilm@151E0000 { |
| 80 | compatible = "mediatek,wocpu0_ilm"; |
| 81 | reg = <0 0x151E0000 0 0x8000>; |
| 82 | }; |
| 83 | |
| 84 | wocpu1_ilm: wocpu1_ilm@151F0000 { |
| 85 | compatible = "mediatek,wocpu1_ilm"; |
| 86 | reg = <0 0x151F0000 0 0x8000>; |
| 87 | }; |
| 88 | |
| 89 | wocpu_dlm: wocpu_dlm@151E8000 { |
| 90 | compatible = "mediatek,wocpu_dlm"; |
| 91 | reg = <0 0x151E8000 0 0x2000>, |
| 92 | <0 0x151F8000 0 0x2000>; |
| 93 | |
| 94 | resets = <ðsysrst 0>; |
| 95 | reset-names = "wocpu_rst"; |
| 96 | }; |
| 97 | |
| 98 | cpu_boot: wocpu_boot@15194000 { |
| 99 | compatible = "mediatek,wocpu_boot"; |
| 100 | reg = <0 0x15194000 0 0x1000>; |
| 101 | }; |
| 102 | |
| 103 | reserved-memory { |
| 104 | #address-cells = <2>; |
| 105 | #size-cells = <2>; |
| 106 | ranges; |
| 107 | |
| 108 | /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
| 109 | secmon_reserved: secmon@43000000 { |
| 110 | reg = <0 0x43000000 0 0x30000>; |
| 111 | no-map; |
| 112 | }; |
| 113 | |
| 114 | wmcpu_emi: wmcpu-reserved@4FC00000 { |
| 115 | compatible = "mediatek,wmcpu-reserved"; |
| 116 | no-map; |
| 117 | reg = <0 0x4FC00000 0 0x00100000>; |
| 118 | }; |
| 119 | |
| 120 | wocpu0_emi: wocpu0_emi@4FD00000 { |
| 121 | compatible = "mediatek,wocpu0_emi"; |
| 122 | no-map; |
| 123 | reg = <0 0x4FD00000 0 0x40000>; |
| 124 | shared = <0>; |
| 125 | }; |
| 126 | |
| 127 | wocpu1_emi: wocpu1_emi@4FD80000 { |
| 128 | compatible = "mediatek,wocpu1_emi"; |
| 129 | no-map; |
| 130 | reg = <0 0x4FD40000 0 0x40000>; |
| 131 | shared = <0>; |
| 132 | }; |
| 133 | |
| 134 | wocpu_data: wocpu_data@4FE00000 { |
| 135 | compatible = "mediatek,wocpu_data"; |
| 136 | no-map; |
| 137 | reg = <0 0x4FD80000 0 0x200000>; |
| 138 | shared = <1>; |
| 139 | }; |
| 140 | }; |
| 141 | |
| 142 | psci { |
| 143 | compatible = "arm,psci-0.2"; |
| 144 | method = "smc"; |
| 145 | }; |
| 146 | |
| 147 | system_clk: dummy13m { |
| 148 | compatible = "fixed-clock"; |
| 149 | clock-frequency = <13000000>; |
| 150 | #clock-cells = <0>; |
| 151 | }; |
| 152 | |
| 153 | rtc_clk: dummy32k { |
| 154 | compatible = "fixed-clock"; |
| 155 | clock-frequency = <32000>; |
| 156 | #clock-cells = <0>; |
| 157 | }; |
| 158 | |
| 159 | uart_clk: dummy12m { |
| 160 | compatible = "fixed-clock"; |
| 161 | clock-frequency = <12000000>; |
| 162 | #clock-cells = <0>; |
| 163 | }; |
| 164 | |
| 165 | gpt_clk: dummy6m { |
| 166 | compatible = "fixed-clock"; |
| 167 | clock-frequency = <6000000>; |
| 168 | #clock-cells = <0>; |
| 169 | }; |
| 170 | |
| 171 | timer { |
| 172 | compatible = "arm,armv8-timer"; |
| 173 | interrupt-parent = <&gic>; |
| 174 | clock-frequency = <12000000>; |
| 175 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 176 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 177 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 178 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| 179 | |
| 180 | }; |
| 181 | |
| 182 | watchdog: watchdog@1001c000 { |
| 183 | compatible = "mediatek,mt7622-wdt", |
| 184 | "mediatek,mt6589-wdt"; |
| 185 | reg = <0 0x1001c000 0 0x1000>; |
| 186 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 187 | #reset-cells = <1>; |
| 188 | }; |
| 189 | |
| 190 | gic: interrupt-controller@c000000 { |
| 191 | compatible = "arm,gic-v3"; |
| 192 | #interrupt-cells = <3>; |
| 193 | interrupt-parent = <&gic>; |
| 194 | interrupt-controller; |
| 195 | reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| 196 | <0 0x0c080000 0 0x200000>; /* GICR */ |
| 197 | |
| 198 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 199 | }; |
| 200 | |
| 201 | uart0: serial@11002000 { |
| 202 | compatible = "mediatek,mt7986-uart", |
| 203 | "mediatek,mt6577-uart"; |
| 204 | reg = <0 0x11002000 0 0x400>; |
| 205 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| 206 | clocks = <&uart_clk>; |
| 207 | status = "disabled"; |
| 208 | }; |
| 209 | |
| 210 | uart1: serial@11003000 { |
| 211 | compatible = "mediatek,mt7986-uart", |
| 212 | "mediatek,mt6577-uart"; |
| 213 | reg = <0 0x11003000 0 0x400>; |
| 214 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| 215 | clocks = <&uart_clk>; |
| 216 | status = "disabled"; |
| 217 | }; |
| 218 | |
| 219 | uart2: serial@11004000 { |
| 220 | compatible = "mediatek,mt7986-uart", |
| 221 | "mediatek,mt6577-uart"; |
| 222 | reg = <0 0x11004000 0 0x400>; |
| 223 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| 224 | clocks = <&uart_clk>; |
| 225 | status = "disabled"; |
| 226 | }; |
| 227 | |
| 228 | pcie: pcie@11280000 { |
| 229 | compatible = "mediatek,mt7986-pcie"; |
| 230 | device_type = "pci"; |
| 231 | reg = <0 0x11280000 0 0x5000>; |
| 232 | reg-names = "port0"; |
| 233 | #address-cells = <3>; |
| 234 | #size-cells = <2>; |
| 235 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| 236 | bus-range = <0x00 0xff>; |
| 237 | ranges = <0x82000000 0 0x20000000 |
| 238 | 0x0 0x20000000 0 0x10000000>; |
| 239 | |
| 240 | pcie0: pcie@0,0 { |
| 241 | device_type = "pci"; |
| 242 | reg = <0x0000 0 0 0 0>; |
| 243 | #address-cells = <3>; |
| 244 | #size-cells = <2>; |
| 245 | ranges; |
| 246 | #interrupt-cells = <1>; |
| 247 | interrupt-map-mask = <0 0 0 7>; |
| 248 | interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| 249 | <0 0 0 2 &pcie_intc0 1>, |
| 250 | <0 0 0 3 &pcie_intc0 2>, |
| 251 | <0 0 0 4 &pcie_intc0 3>; |
| 252 | pcie_intc0: interrupt-controller { |
| 253 | interrupt-controller; |
| 254 | #address-cells = <0>; |
| 255 | #interrupt-cells = <1>; |
| 256 | }; |
| 257 | }; |
| 258 | }; |
| 259 | |
| 260 | pio: pinctrl@1001f000 { |
| 261 | compatible = "mediatek,mt7986-pinctrl"; |
| 262 | reg = <0 0x1001f000 0 0x1000>, |
| 263 | <0 0x11c30000 0 0x1000>, |
| 264 | <0 0x11c40000 0 0x1000>, |
| 265 | <0 0x11e20000 0 0x1000>, |
| 266 | <0 0x11e30000 0 0x1000>, |
| 267 | <0 0x11f00000 0 0x1000>, |
| 268 | <0 0x11f10000 0 0x1000>, |
| 269 | <0 0x1000b000 0 0x1000>; |
| 270 | reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", |
| 271 | "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", |
| 272 | "iocfg_tl_base", "eint"; |
| 273 | gpio-controller; |
| 274 | #gpio-cells = <2>; |
| 275 | gpio-ranges = <&pio 0 0 100>; |
| 276 | interrupt-controller; |
developer | a7f8fa4 | 2021-06-07 16:46:34 +0800 | [diff] [blame] | 277 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 278 | interrupt-parent = <&gic>; |
| 279 | #interrupt-cells = <2>; |
| 280 | }; |
| 281 | |
| 282 | ethsys: syscon@15000000 { |
| 283 | #address-cells = <1>; |
| 284 | #size-cells = <1>; |
| 285 | compatible = "mediatek,mt7986-ethsys", |
| 286 | "syscon"; |
| 287 | reg = <0 0x15000000 0 0x1000>; |
| 288 | #clock-cells = <1>; |
| 289 | #reset-cells = <1>; |
| 290 | |
| 291 | ethsysrst: reset-controller { |
| 292 | compatible = "ti,syscon-reset"; |
| 293 | #reset-cells = <1>; |
| 294 | ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; |
| 295 | }; |
| 296 | }; |
| 297 | |
| 298 | eth: ethernet@15100000 { |
| 299 | compatible = "mediatek,mt7986-eth"; |
| 300 | reg = <0 0x15100000 0 0x80000>; |
| 301 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| 302 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| 303 | <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 304 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
| 305 | mediatek,ethsys = <ðsys>; |
| 306 | #reset-cells = <1>; |
| 307 | #address-cells = <1>; |
| 308 | #size-cells = <0>; |
| 309 | status = "disabled"; |
| 310 | }; |
| 311 | |
| 312 | snand: snfi@11005000 { |
| 313 | compatible = "mediatek,mt7986-snand"; |
| 314 | reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; |
| 315 | reg-names = "nfi", "ecc"; |
| 316 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| 317 | clocks = <&system_clk>, |
| 318 | <&system_clk>, |
| 319 | <&system_clk>; |
| 320 | clock-names = "nfi_clk", "pad_clk", "ecc_clk"; |
| 321 | #address-cells = <1>; |
| 322 | #size-cells = <0>; |
| 323 | status = "disabled"; |
| 324 | }; |
| 325 | |
| 326 | wed_pcie: wed_pcie@10003000 { |
| 327 | compatible = "mediatek,wed_pcie"; |
| 328 | reg = <0 0x10003000 0 0x10>; |
| 329 | }; |
| 330 | |
| 331 | wbsys: wbsys@18000000 { |
| 332 | compatible = "mediatek,wbsys"; |
| 333 | reg = <0 0x18000000 0 0x1000000>; |
| 334 | interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| 335 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| 336 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| 337 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| 338 | chip_id = <0x7986>; |
| 339 | }; |
| 340 | |
| 341 | spi0: spi@1100a000 { |
| 342 | compatible = "mediatek,ipm-spi"; |
| 343 | reg = <0 0x1100a000 0 0x100>; |
| 344 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| 345 | status = "disabled"; |
| 346 | }; |
| 347 | |
| 348 | spi1: spi@1100b000 { |
| 349 | compatible = "mediatek,ipm-spi"; |
| 350 | reg = <0 0x1100b000 0 0x100>; |
| 351 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| 352 | status = "disabled"; |
| 353 | }; |
| 354 | |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 355 | auxadc: adc@1100d000 { |
| 356 | compatible = "mediatek,mt7986-auxadc", |
| 357 | "mediatek,mt7622-auxadc"; |
| 358 | reg = <0 0x1100d000 0 0x1000>; |
| 359 | clocks = <&system_clk>; |
| 360 | clock-names = "main"; |
| 361 | #io-channel-cells = <1>; |
| 362 | }; |
| 363 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 364 | consys: consys@10000000 { |
| 365 | compatible = "mediatek,mt7986-consys"; |
| 366 | reg = <0 0x10000000 0 0x8600000>; |
| 367 | memory-region = <&wmcpu_emi>; |
| 368 | }; |
| 369 | |
| 370 | xhci: xhci@11200000 { |
| 371 | compatible = "mediatek,mt7986-xhci", |
| 372 | "mediatek,mtk-xhci"; |
| 373 | reg = <0 0x11200000 0 0x2e00>, |
| 374 | <0 0x11203e00 0 0x0100>; |
| 375 | reg-names = "mac", "ippc"; |
| 376 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 377 | phys = <&u2port0 PHY_TYPE_USB2>; |
| 378 | clocks = <&system_clk>, |
| 379 | <&system_clk>, |
| 380 | <&system_clk>, |
| 381 | <&system_clk>, |
| 382 | <&system_clk>; |
| 383 | clock-names = "sys_ck", |
| 384 | "xhci_ck", |
| 385 | "ref_ck", |
| 386 | "mcu_ck", |
| 387 | "dma_ck"; |
| 388 | #address-cells = <2>; |
| 389 | #size-cells = <2>; |
| 390 | mediatek,u3p-dis-msk=<0x01>; |
| 391 | status = "okay"; |
| 392 | }; |
| 393 | |
| 394 | usbtphy: usb-phy@11203e00 { |
| 395 | compatible = "mediatek,a60810-u2phy", |
| 396 | "mediatek,a60931-u3phy", |
| 397 | "mediatek,a60xxx-usbphy"; |
| 398 | #address-cells = <2>; |
| 399 | #size-cells = <2>; |
| 400 | ranges; |
| 401 | status = "okay"; |
| 402 | |
| 403 | u2port0: usb-phy@11203ed0 { |
| 404 | reg = <0 0x11203ed0 0 0x008>; |
| 405 | clocks = <&system_clk>; |
| 406 | clock-names = "ref"; |
| 407 | #phy-cells = <1>; |
| 408 | status = "okay"; |
| 409 | }; |
| 410 | |
| 411 | u3port0: usb-phy@11203ed8 { |
| 412 | reg = <0 0x11203ed8 0 0x008>; |
| 413 | clocks = <&system_clk>; |
| 414 | clock-names = "ref"; |
| 415 | #phy-cells = <1>; |
| 416 | status = "disabled"; |
| 417 | }; |
| 418 | |
| 419 | u2port1: usb-phy@11203ee0 { |
| 420 | reg = <0 0x11203ee0 0 0x008>; |
| 421 | clocks = <&system_clk>; |
| 422 | clock-names = "ref"; |
| 423 | #phy-cells = <1>; |
| 424 | status = "disabled"; |
| 425 | }; |
| 426 | }; |
| 427 | }; |