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developerb11a5392022-03-31 00:34:47 +08001// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#include <linux/etherdevice.h>
5#include <linux/hwmon.h>
6#include <linux/hwmon-sysfs.h>
7#include <linux/thermal.h>
8#include "mt7915.h"
9#include "mac.h"
10#include "mcu.h"
11#include "eeprom.h"
12
13static const struct ieee80211_iface_limit if_limits[] = {
14 {
15 .max = 1,
16 .types = BIT(NL80211_IFTYPE_ADHOC)
17 }, {
18 .max = 16,
19 .types = BIT(NL80211_IFTYPE_AP)
20#ifdef CONFIG_MAC80211_MESH
21 | BIT(NL80211_IFTYPE_MESH_POINT)
22#endif
23 }, {
24 .max = MT7915_MAX_INTERFACES,
25 .types = BIT(NL80211_IFTYPE_STATION)
26 }
27};
28
29static const struct ieee80211_iface_combination if_comb[] = {
30 {
31 .limits = if_limits,
32 .n_limits = ARRAY_SIZE(if_limits),
33 .max_interfaces = MT7915_MAX_INTERFACES,
34 .num_different_channels = 1,
35 .beacon_int_infra_match = true,
36 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
37 BIT(NL80211_CHAN_WIDTH_20) |
38 BIT(NL80211_CHAN_WIDTH_40) |
39 BIT(NL80211_CHAN_WIDTH_80) |
40 BIT(NL80211_CHAN_WIDTH_160) |
41 BIT(NL80211_CHAN_WIDTH_80P80),
42 }
43};
44
45static ssize_t mt7915_thermal_temp_show(struct device *dev,
46 struct device_attribute *attr,
47 char *buf)
48{
49 struct mt7915_phy *phy = dev_get_drvdata(dev);
50 int i = to_sensor_dev_attr(attr)->index;
51 int temperature;
52
53 switch (i) {
54 case 0:
55 temperature = mt7915_mcu_get_temperature(phy);
56 if (temperature < 0)
57 return temperature;
58 /* display in millidegree celcius */
59 return sprintf(buf, "%u\n", temperature * 1000);
60 case 1:
61 case 2:
62 return sprintf(buf, "%u\n",
63 phy->throttle_temp[i - 1] * 1000);
64 case 3:
65 return sprintf(buf, "%hhu\n", phy->throttle_state);
66 default:
67 return -EINVAL;
68 }
69}
70
71static ssize_t mt7915_thermal_temp_store(struct device *dev,
72 struct device_attribute *attr,
73 const char *buf, size_t count)
74{
75 struct mt7915_phy *phy = dev_get_drvdata(dev);
76 int ret, i = to_sensor_dev_attr(attr)->index;
77 long val;
78
79 ret = kstrtol(buf, 10, &val);
80 if (ret < 0)
81 return ret;
82
83 mutex_lock(&phy->dev->mt76.mutex);
84 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130);
85 phy->throttle_temp[i - 1] = val;
86 mutex_unlock(&phy->dev->mt76.mutex);
87
88 return count;
89}
90
91static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0);
92static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1);
93static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2);
94static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3);
95
96static struct attribute *mt7915_hwmon_attrs[] = {
97 &sensor_dev_attr_temp1_input.dev_attr.attr,
98 &sensor_dev_attr_temp1_crit.dev_attr.attr,
99 &sensor_dev_attr_temp1_max.dev_attr.attr,
100 &sensor_dev_attr_throttle1.dev_attr.attr,
101 NULL,
102};
103ATTRIBUTE_GROUPS(mt7915_hwmon);
104
105static int
106mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
107 unsigned long *state)
108{
109 *state = MT7915_CDEV_THROTTLE_MAX;
110
111 return 0;
112}
113
114static int
115mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
116 unsigned long *state)
117{
118 struct mt7915_phy *phy = cdev->devdata;
119
120 *state = phy->cdev_state;
121
122 return 0;
123}
124
125static int
126mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
127 unsigned long state)
128{
129 struct mt7915_phy *phy = cdev->devdata;
130 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state;
131 int ret;
132
133 if (state > MT7915_CDEV_THROTTLE_MAX)
134 return -EINVAL;
135
136 if (phy->throttle_temp[0] > phy->throttle_temp[1])
137 return 0;
138
139 if (state == phy->cdev_state)
140 return 0;
141
142 /*
143 * cooling_device convention: 0 = no cooling, more = more cooling
144 * mcu convention: 1 = max cooling, more = less cooling
145 */
146 ret = mt7915_mcu_set_thermal_throttling(phy, throttling);
147 if (ret)
148 return ret;
149
150 phy->cdev_state = state;
151
152 return 0;
153}
154
155static const struct thermal_cooling_device_ops mt7915_thermal_ops = {
156 .get_max_state = mt7915_thermal_get_max_throttle_state,
157 .get_cur_state = mt7915_thermal_get_cur_throttle_state,
158 .set_cur_state = mt7915_thermal_set_cur_throttle_state,
159};
160
161static void mt7915_unregister_thermal(struct mt7915_phy *phy)
162{
163 struct wiphy *wiphy = phy->mt76->hw->wiphy;
164
165 if (!phy->cdev)
166 return;
167
168 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device");
169 thermal_cooling_device_unregister(phy->cdev);
170}
171
172static int mt7915_thermal_init(struct mt7915_phy *phy)
173{
174 struct wiphy *wiphy = phy->mt76->hw->wiphy;
175 struct thermal_cooling_device *cdev;
176 struct device *hwmon;
177 const char *name;
178
179 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s",
180 wiphy_name(wiphy));
181
182 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops);
183 if (!IS_ERR(cdev)) {
184 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
185 "cooling_device") < 0)
186 thermal_cooling_device_unregister(cdev);
187 else
188 phy->cdev = cdev;
189 }
190
191 if (!IS_REACHABLE(CONFIG_HWMON))
192 return 0;
193
194 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
195 mt7915_hwmon_groups);
196 if (IS_ERR(hwmon))
197 return PTR_ERR(hwmon);
198
199 /* initialize critical/maximum high temperature */
200 phy->throttle_temp[0] = 110;
201 phy->throttle_temp[1] = 120;
202
203 return mt7915_mcu_set_thermal_throttling(phy,
204 MT7915_THERMAL_THROTTLE_MAX);
205}
206
207static void mt7915_led_set_config(struct led_classdev *led_cdev,
208 u8 delay_on, u8 delay_off)
209{
210 struct mt7915_dev *dev;
211 struct mt76_dev *mt76;
212 u32 val;
213
214 mt76 = container_of(led_cdev, struct mt76_dev, led_cdev);
215 dev = container_of(mt76, struct mt7915_dev, mt76);
216
217 /* select TX blink mode, 2: only data frames */
218 mt76_rmw_field(dev, MT_TMAC_TCR0(0), MT_TMAC_TCR0_TX_BLINK, 2);
219
220 /* enable LED */
221 mt76_wr(dev, MT_LED_EN(0), 1);
222
223 /* set LED Tx blink on/off time */
224 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) |
225 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off);
226 mt76_wr(dev, MT_LED_TX_BLINK(0), val);
227
228 /* control LED */
229 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK;
230 if (dev->mt76.led_al)
231 val |= MT_LED_CTRL_POLARITY;
232
233 mt76_wr(dev, MT_LED_CTRL(0), val);
234 mt76_clear(dev, MT_LED_CTRL(0), MT_LED_CTRL_KICK);
235}
236
237static int mt7915_led_set_blink(struct led_classdev *led_cdev,
238 unsigned long *delay_on,
239 unsigned long *delay_off)
240{
241 u16 delta_on = 0, delta_off = 0;
242
243#define HW_TICK 10
244#define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
245
246 if (*delay_on)
247 delta_on = TO_HW_TICK(*delay_on);
248 if (*delay_off)
249 delta_off = TO_HW_TICK(*delay_off);
250
251 mt7915_led_set_config(led_cdev, delta_on, delta_off);
252
253 return 0;
254}
255
256static void mt7915_led_set_brightness(struct led_classdev *led_cdev,
257 enum led_brightness brightness)
258{
259 if (!brightness)
260 mt7915_led_set_config(led_cdev, 0, 0xff);
261 else
262 mt7915_led_set_config(led_cdev, 0xff, 0);
263}
264
265static void
266mt7915_init_txpower(struct mt7915_dev *dev,
267 struct ieee80211_supported_band *sband)
268{
269 int i, n_chains = hweight8(dev->mphy.antenna_mask);
270 int nss_delta = mt76_tx_power_nss_delta(n_chains);
271 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band);
272 struct mt76_power_limits limits;
273
274 for (i = 0; i < sband->n_channels; i++) {
275 struct ieee80211_channel *chan = &sband->channels[i];
276 u32 target_power = 0;
277 int j;
278
279 for (j = 0; j < n_chains; j++) {
280 u32 val;
281
282 val = mt7915_eeprom_get_target_power(dev, chan, j);
283 target_power = max(target_power, val);
284 }
285
286 target_power += pwr_delta;
287 target_power = mt76_get_rate_power_limits(&dev->mphy, chan,
288 &limits,
289 target_power);
290 target_power += nss_delta;
291 target_power = DIV_ROUND_UP(target_power, 2);
292 chan->max_power = min_t(int, chan->max_reg_power,
293 target_power);
294 chan->orig_mpwr = target_power;
295 }
296}
297
298static void
299mt7915_regd_notifier(struct wiphy *wiphy,
300 struct regulatory_request *request)
301{
302 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
303 struct mt7915_dev *dev = mt7915_hw_dev(hw);
304 struct mt76_phy *mphy = hw->priv;
305 struct mt7915_phy *phy = mphy->priv;
306
307 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
308 dev->mt76.region = request->dfs_region;
309
310 if (dev->mt76.region == NL80211_DFS_UNSET)
311 mt7915_mcu_rdd_background_enable(phy, NULL);
312
313 mt7915_init_txpower(dev, &mphy->sband_2g.sband);
314 mt7915_init_txpower(dev, &mphy->sband_5g.sband);
315 mt7915_init_txpower(dev, &mphy->sband_6g.sband);
316
317 mphy->dfs_state = MT_DFS_STATE_UNKNOWN;
318 mt7915_dfs_init_radar_detector(phy);
319}
320
321static void
322mt7915_init_wiphy(struct ieee80211_hw *hw)
323{
324 struct mt7915_phy *phy = mt7915_hw_phy(hw);
325 struct mt76_dev *mdev = &phy->dev->mt76;
326 struct wiphy *wiphy = hw->wiphy;
327 struct mt7915_dev *dev = phy->dev;
328
329 hw->queues = 4;
330 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF;
331 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF;
332 hw->netdev_features = NETIF_F_RXCSUM;
333
334 hw->radiotap_timestamp.units_pos =
335 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
336
337 phy->slottime = 9;
338
339 hw->sta_data_size = sizeof(struct mt7915_sta);
340 hw->vif_data_size = sizeof(struct mt7915_vif);
341
342 wiphy->iface_combinations = if_comb;
343 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
344 wiphy->reg_notifier = mt7915_regd_notifier;
345 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
346 wiphy->mbssid_max_interfaces = 16;
347
348 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
349 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
350 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
351 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
352 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
353 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
354
355 if (!mdev->dev->of_node ||
356 !of_property_read_bool(mdev->dev->of_node,
357 "mediatek,disable-radar-background"))
358 wiphy_ext_feature_set(wiphy,
359 NL80211_EXT_FEATURE_RADAR_BACKGROUND);
360
361 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
362 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
363 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
364 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
365 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
366
367 hw->max_tx_fragments = 4;
368
369 if (!phy->dev->dbdc_support)
370 wiphy->txq_memory_limit = 32 << 20; /* 32 MiB */
371
372 if (phy->mt76->cap.has_2ghz)
373 phy->mt76->sband_2g.sband.ht_cap.cap |=
374 IEEE80211_HT_CAP_LDPC_CODING |
375 IEEE80211_HT_CAP_MAX_AMSDU;
376
377 if (phy->mt76->cap.has_5ghz) {
378 phy->mt76->sband_5g.sband.ht_cap.cap |=
379 IEEE80211_HT_CAP_LDPC_CODING |
380 IEEE80211_HT_CAP_MAX_AMSDU;
381
382 if (is_mt7915(&dev->mt76)) {
383 phy->mt76->sband_5g.sband.vht_cap.cap |=
384 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 |
385 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
386
387 if (!dev->dbdc_support)
388 phy->mt76->sband_5g.sband.vht_cap.cap |=
389 IEEE80211_VHT_CAP_SHORT_GI_160 |
390 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ;
391 } else {
392 phy->mt76->sband_5g.sband.vht_cap.cap |=
393 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
394 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
395
396 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */
397 phy->mt76->sband_5g.sband.vht_cap.cap |=
398 IEEE80211_VHT_CAP_SHORT_GI_160 |
399 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
400 }
401 }
402
403 mt76_set_stream_caps(phy->mt76, true);
404 mt7915_set_stream_vht_txbf_caps(phy);
405 mt7915_set_stream_he_caps(phy);
406
407 wiphy->available_antennas_rx = phy->mt76->antenna_mask;
408 wiphy->available_antennas_tx = phy->mt76->antenna_mask;
409}
410
411static void
412mt7915_mac_init_band(struct mt7915_dev *dev, u8 band)
413{
414 u32 mask, set;
415
416 mt76_rmw_field(dev, MT_TMAC_CTCR0(band),
417 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);
418 mt76_set(dev, MT_TMAC_CTCR0(band),
419 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |
420 MT_TMAC_CTCR0_INS_DDLMT_EN);
421
422 mask = MT_MDP_RCFR0_MCU_RX_MGMT |
423 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR |
424 MT_MDP_RCFR0_MCU_RX_CTL_BAR;
425 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) |
426 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) |
427 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF);
428 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set);
429
430 mask = MT_MDP_RCFR1_MCU_RX_BYPASS |
431 MT_MDP_RCFR1_RX_DROPPED_UCAST |
432 MT_MDP_RCFR1_RX_DROPPED_MCAST;
433 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) |
434 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) |
435 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF);
436 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set);
437
438 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680);
439
440 /* mt7915: disable rx rate report by default due to hw issues */
441 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
442}
443
444static void mt7915_mac_init(struct mt7915_dev *dev)
445{
446 int i;
447 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680;
448
449 /* config pse qid6 wfdma port selection */
450 if (!is_mt7915(&dev->mt76) && dev->hif2)
451 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0,
452 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK);
453
454 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len);
455
developer66cd2092022-05-10 15:43:01 +0800456 if (!is_mt7915(&dev->mt76))
457 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
458
developerb11a5392022-03-31 00:34:47 +0800459 /* enable hardware de-agg */
460 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN);
461
462 for (i = 0; i < mt7915_wtbl_size(dev); i++)
463 mt7915_mac_wtbl_update(dev, i,
464 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
465 for (i = 0; i < 2; i++)
466 mt7915_mac_init_band(dev, i);
467
468 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
469 i = dev->mt76.led_pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2;
470 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4);
471 }
472}
473
474static int mt7915_txbf_init(struct mt7915_dev *dev)
475{
476 int ret;
477
478 if (dev->dbdc_support) {
479 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE);
480 if (ret)
481 return ret;
482 }
483
484 /* trigger sounding packets */
485 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON);
486 if (ret)
487 return ret;
488
489 /* enable eBF */
490 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
491}
492
493static struct mt7915_phy *
494mt7915_alloc_ext_phy(struct mt7915_dev *dev)
495{
496 struct mt7915_phy *phy;
497 struct mt76_phy *mphy;
498
499 if (!dev->dbdc_support)
500 return NULL;
501
502 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1);
503 if (!mphy)
504 return ERR_PTR(-ENOMEM);
505
506 phy = mphy->priv;
507 phy->dev = dev;
508 phy->mt76 = mphy;
509
510 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */
511 phy->band_idx = 1;
512
513 return phy;
514}
515
516static int
517mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy)
518{
519 struct mt76_phy *mphy = phy->mt76;
520 int ret;
521
522 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work);
523
524 mt7915_eeprom_parse_hw_cap(dev, phy);
525
526 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2,
527 ETH_ALEN);
528 /* Make the secondary PHY MAC address local without overlapping with
529 * the usual MAC address allocation scheme on multiple virtual interfaces
530 */
531 if (!is_valid_ether_addr(mphy->macaddr)) {
532 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
533 ETH_ALEN);
534 mphy->macaddr[0] |= 2;
535 mphy->macaddr[0] ^= BIT(7);
536 }
537 mt76_eeprom_override(mphy);
538
539 /* init wiphy according to mphy and phy */
540 mt7915_init_wiphy(mphy->hw);
541
542 ret = mt76_register_phy(mphy, true, mt76_rates,
543 ARRAY_SIZE(mt76_rates));
544 if (ret)
545 return ret;
546
547 ret = mt7915_thermal_init(phy);
548 if (ret)
549 goto unreg;
550
551 mt7915_init_debugfs(phy);
552
553 return 0;
554
555unreg:
556 mt76_unregister_phy(mphy);
557 return ret;
558}
559
560static void mt7915_init_work(struct work_struct *work)
561{
562 struct mt7915_dev *dev = container_of(work, struct mt7915_dev,
563 init_work);
564
565 mt7915_mcu_set_eeprom(dev);
566 mt7915_mac_init(dev);
567 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband);
568 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband);
569 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband);
570 mt7915_txbf_init(dev);
571}
572
573void mt7915_wfsys_reset(struct mt7915_dev *dev)
574{
575#define MT_MCU_DUMMY_RANDOM GENMASK(15, 0)
576#define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16)
577
578 if (is_mt7915(&dev->mt76)) {
579 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON;
580
581 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM);
582
583 /* change to software control */
584 val |= MT_TOP_PWR_SW_RST;
585 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
586
587 /* reset wfsys */
588 val &= ~MT_TOP_PWR_SW_RST;
589 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
590
591 /* release wfsys then mcu re-executes romcode */
592 val |= MT_TOP_PWR_SW_RST;
593 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
594
595 /* switch to hw control */
596 val &= ~MT_TOP_PWR_SW_RST;
597 val |= MT_TOP_PWR_HW_CTRL;
598 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
599
600 /* check whether mcu resets to default */
601 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR,
602 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT,
603 1000)) {
604 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n");
605 return;
606 }
607
608 /* wfsys reset won't clear host registers */
609 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE);
610
611 msleep(100);
612 } else if (is_mt7986(&dev->mt76)) {
613 mt7986_wmac_disable(dev);
614 msleep(20);
615
616 mt7986_wmac_enable(dev);
617 msleep(20);
618 } else {
619 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
620 msleep(20);
621
622 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
623 msleep(20);
624 }
625}
626
627static bool mt7915_band_config(struct mt7915_dev *dev)
628{
629 bool ret = true;
630
631 dev->phy.band_idx = 0;
632
633 if (is_mt7986(&dev->mt76)) {
634 u32 sku = mt7915_check_adie(dev, true);
635
636 /*
637 * for mt7986, dbdc support is determined by the number
638 * of adie chips and the main phy is bound to band1 when
639 * dbdc is disabled.
640 */
641 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) {
642 dev->phy.band_idx = 1;
643 ret = false;
644 }
645 } else {
646 ret = is_mt7915(&dev->mt76) ?
647 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true;
648 }
649
650 return ret;
651}
652
653static int
654mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2)
655{
656 int ret, idx;
657
658 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
659
660 INIT_WORK(&dev->init_work, mt7915_init_work);
661
662 ret = mt7915_dma_init(dev, phy2);
663 if (ret)
664 return ret;
665
666 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
667
668 ret = mt7915_mcu_init(dev);
669 if (ret)
670 return ret;
671
672 ret = mt7915_eeprom_init(dev);
673 if (ret < 0)
674 return ret;
675
676 if (dev->flash_mode) {
677 ret = mt7915_mcu_apply_group_cal(dev);
678 if (ret)
679 return ret;
680 }
681
682 /* Beacon and mgmt frames should occupy wcid 0 */
683 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
684 if (idx)
685 return -ENOSPC;
686
687 dev->mt76.global_wcid.idx = idx;
688 dev->mt76.global_wcid.hw_key_idx = -1;
689 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
690 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
691
692 return 0;
693}
694
695void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy)
696{
697 int nss;
698 u32 *cap;
699
700 if (!phy->mt76->cap.has_5ghz)
701 return;
702
703 nss = hweight8(phy->mt76->chainmask);
704 cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
705
706 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
707 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
708 (3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
709
710 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
711 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
712 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
713
714 if (nss < 2)
715 return;
716
717 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
718 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
719 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
720 nss - 1);
721}
722
723static void
724mt7915_set_stream_he_txbf_caps(struct mt7915_dev *dev,
725 struct ieee80211_sta_he_cap *he_cap,
726 int vif, int nss)
727{
728 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
729 u8 c, nss_160;
730
731 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */
732 if (is_mt7915(&dev->mt76) && !dev->dbdc_support)
733 nss_160 = nss / 2;
734 else
735 nss_160 = nss;
736
737#ifdef CONFIG_MAC80211_MESH
738 if (vif == NL80211_IFTYPE_MESH_POINT)
739 return;
740#endif
741
742 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
743 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
744
745 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK |
746 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
747 elem->phy_cap_info[5] &= ~c;
748
749 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
750 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
751 elem->phy_cap_info[6] &= ~c;
752
753 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
754
755 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
756 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO |
757 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO;
758 elem->phy_cap_info[2] |= c;
759
760 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
761 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 |
762 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
763 elem->phy_cap_info[4] |= c;
764
765 /* do not support NG16 due to spec D4.0 changes subcarrier idx */
766 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
767 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
768
769 if (vif == NL80211_IFTYPE_STATION)
770 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
771
772 elem->phy_cap_info[6] |= c;
773
774 if (nss < 2)
775 return;
776
777 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
778 elem->phy_cap_info[7] |= min_t(int, nss - 1, 2) << 3;
779
780 if (vif != NL80211_IFTYPE_AP)
781 return;
782
783 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
784 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
785
786 /* num_snd_dim
787 * for mt7915, max supported nss is 2 for bw > 80MHz
788 */
789 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
790 nss - 1) |
791 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
792 nss_160 - 1);
793 elem->phy_cap_info[5] |= c;
794
795 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
796 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
797 elem->phy_cap_info[6] |= c;
798
799 if (!is_mt7915(&dev->mt76)) {
800 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
801 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
802 elem->phy_cap_info[7] |= c;
803 }
804}
805
806static void
807mt7915_gen_ppe_thresh(u8 *he_ppet, int nss)
808{
809 u8 i, ppet_bits, ppet_size, ru_bit_mask = 0x7; /* HE80 */
developer66cd2092022-05-10 15:43:01 +0800810 static const u8 ppet16_ppet8_ru3_ru0[] = {0x1c, 0xc7, 0x71};
developerb11a5392022-03-31 00:34:47 +0800811
812 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) |
813 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK,
814 ru_bit_mask);
815
816 ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE *
817 nss * hweight8(ru_bit_mask) * 2;
818 ppet_size = DIV_ROUND_UP(ppet_bits, 8);
819
820 for (i = 0; i < ppet_size - 1; i++)
821 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3];
822
823 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] &
824 (0xff >> (8 - (ppet_bits - 1) % 8));
825}
826
827static int
828mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band,
829 struct ieee80211_sband_iftype_data *data)
830{
831 struct mt7915_dev *dev = phy->dev;
832 int i, idx = 0, nss = hweight8(phy->mt76->chainmask);
833 u16 mcs_map = 0;
834 u16 mcs_map_160 = 0;
835 u8 nss_160;
836
837 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */
838 if (is_mt7915(&dev->mt76) && !dev->dbdc_support)
839 nss_160 = nss / 2;
840 else
841 nss_160 = nss;
842
843 for (i = 0; i < 8; i++) {
844 if (i < nss)
845 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
846 else
847 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
848
849 if (i < nss_160)
850 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
851 else
852 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
853 }
854
855 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
856 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap;
857 struct ieee80211_he_cap_elem *he_cap_elem =
858 &he_cap->he_cap_elem;
859 struct ieee80211_he_mcs_nss_supp *he_mcs =
860 &he_cap->he_mcs_nss_supp;
861
862 switch (i) {
863 case NL80211_IFTYPE_STATION:
864 case NL80211_IFTYPE_AP:
865#ifdef CONFIG_MAC80211_MESH
866 case NL80211_IFTYPE_MESH_POINT:
867#endif
868 break;
869 default:
870 continue;
871 }
872
873 data[idx].types_mask = BIT(i);
874 he_cap->has_he = true;
875
876 he_cap_elem->mac_cap_info[0] =
877 IEEE80211_HE_MAC_CAP0_HTC_HE;
878 he_cap_elem->mac_cap_info[3] =
879 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
880 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
881 he_cap_elem->mac_cap_info[4] =
882 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
883
884 if (band == NL80211_BAND_2GHZ)
885 he_cap_elem->phy_cap_info[0] =
886 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
887 else
888 he_cap_elem->phy_cap_info[0] =
889 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
890 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G |
891 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G;
892
893 he_cap_elem->phy_cap_info[1] =
894 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
895 he_cap_elem->phy_cap_info[2] =
896 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
897 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
898
899 switch (i) {
900 case NL80211_IFTYPE_AP:
901 he_cap_elem->mac_cap_info[0] |=
902 IEEE80211_HE_MAC_CAP0_TWT_RES;
903 he_cap_elem->mac_cap_info[2] |=
904 IEEE80211_HE_MAC_CAP2_BSR;
905 he_cap_elem->mac_cap_info[4] |=
906 IEEE80211_HE_MAC_CAP4_BQR;
907 he_cap_elem->mac_cap_info[5] |=
908 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
909 he_cap_elem->phy_cap_info[3] |=
910 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
911 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
912 he_cap_elem->phy_cap_info[6] |=
913 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
914 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
915 he_cap_elem->phy_cap_info[9] |=
916 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
917 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
918 break;
919 case NL80211_IFTYPE_STATION:
920 he_cap_elem->mac_cap_info[1] |=
921 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
922
923 if (band == NL80211_BAND_2GHZ)
924 he_cap_elem->phy_cap_info[0] |=
925 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
926 else
927 he_cap_elem->phy_cap_info[0] |=
928 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
929
930 he_cap_elem->phy_cap_info[1] |=
931 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
932 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
933 he_cap_elem->phy_cap_info[3] |=
934 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
935 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
936 he_cap_elem->phy_cap_info[6] |=
937 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
938 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
939 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
940 he_cap_elem->phy_cap_info[7] |=
941 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
942 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
943 he_cap_elem->phy_cap_info[8] |=
944 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
945 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
946 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
947 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
948 he_cap_elem->phy_cap_info[9] |=
949 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
950 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
951 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
952 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
953 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
954 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
955 break;
956 }
957
958 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
959 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
960 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160);
961 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160);
962 he_mcs->rx_mcs_80p80 = cpu_to_le16(mcs_map_160);
963 he_mcs->tx_mcs_80p80 = cpu_to_le16(mcs_map_160);
964
965 mt7915_set_stream_he_txbf_caps(dev, he_cap, i, nss);
966
967 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
968 if (he_cap_elem->phy_cap_info[6] &
969 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
970 mt7915_gen_ppe_thresh(he_cap->ppe_thres, nss);
971 } else {
972 he_cap_elem->phy_cap_info[9] |=
973 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US;
974 }
975
976 if (band == NL80211_BAND_6GHZ) {
977 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
978 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
979
980 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_8,
981 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
982 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
983 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
984 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
985 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
986
987 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap);
988 }
989
990 idx++;
991 }
992
993 return idx;
994}
995
996void mt7915_set_stream_he_caps(struct mt7915_phy *phy)
997{
998 struct ieee80211_sband_iftype_data *data;
999 struct ieee80211_supported_band *band;
1000 int n;
1001
1002 if (phy->mt76->cap.has_2ghz) {
1003 data = phy->iftype[NL80211_BAND_2GHZ];
1004 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data);
1005
1006 band = &phy->mt76->sband_2g.sband;
1007 band->iftype_data = data;
1008 band->n_iftype_data = n;
1009 }
1010
1011 if (phy->mt76->cap.has_5ghz) {
1012 data = phy->iftype[NL80211_BAND_5GHZ];
1013 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data);
1014
1015 band = &phy->mt76->sband_5g.sband;
1016 band->iftype_data = data;
1017 band->n_iftype_data = n;
1018 }
1019
1020 if (phy->mt76->cap.has_6ghz) {
1021 data = phy->iftype[NL80211_BAND_6GHZ];
1022 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data);
1023
1024 band = &phy->mt76->sband_6g.sband;
1025 band->iftype_data = data;
1026 band->n_iftype_data = n;
1027 }
1028}
1029
1030static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
1031{
1032 struct mt7915_phy *phy = mt7915_ext_phy(dev);
1033 struct mt76_phy *mphy = dev->mt76.phy2;
1034
1035 if (!phy)
1036 return;
1037
1038 mt7915_unregister_thermal(phy);
1039 mt76_unregister_phy(mphy);
1040 ieee80211_free_hw(mphy->hw);
1041}
1042
1043static void mt7915_stop_hardware(struct mt7915_dev *dev)
1044{
1045 mt7915_mcu_exit(dev);
1046 mt7915_tx_token_put(dev);
1047 mt7915_dma_cleanup(dev);
1048 tasklet_disable(&dev->irq_tasklet);
1049
1050 if (is_mt7986(&dev->mt76))
1051 mt7986_wmac_disable(dev);
1052}
1053
1054
1055int mt7915_register_device(struct mt7915_dev *dev)
1056{
1057 struct ieee80211_hw *hw = mt76_hw(dev);
1058 struct mt7915_phy *phy2;
1059 int ret;
1060
1061 dev->phy.dev = dev;
1062 dev->phy.mt76 = &dev->mt76.phy;
1063 dev->mt76.phy.priv = &dev->phy;
1064 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work);
1065 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work);
1066 INIT_LIST_HEAD(&dev->sta_rc_list);
1067 INIT_LIST_HEAD(&dev->sta_poll_list);
1068 INIT_LIST_HEAD(&dev->twt_list);
1069 spin_lock_init(&dev->sta_poll_lock);
1070
1071 init_waitqueue_head(&dev->reset_wait);
1072 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work);
1073
1074 dev->dbdc_support = mt7915_band_config(dev);
1075
1076 phy2 = mt7915_alloc_ext_phy(dev);
1077 if (IS_ERR(phy2))
1078 return PTR_ERR(phy2);
1079
1080 ret = mt7915_init_hardware(dev, phy2);
1081 if (ret)
1082 goto free_phy2;
1083
1084 mt7915_init_wiphy(hw);
1085
1086#ifdef CONFIG_NL80211_TESTMODE
1087 dev->mt76.test_ops = &mt7915_testmode_ops;
1088#endif
1089
1090 /* init led callbacks */
1091 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
1092 dev->mt76.led_cdev.brightness_set = mt7915_led_set_brightness;
1093 dev->mt76.led_cdev.blink_set = mt7915_led_set_blink;
1094 }
1095
1096 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1097 ARRAY_SIZE(mt76_rates));
1098 if (ret)
1099 goto stop_hw;
1100
1101 ret = mt7915_thermal_init(&dev->phy);
1102 if (ret)
1103 goto unreg_dev;
1104
1105 ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1106
1107 if (phy2) {
1108 ret = mt7915_register_ext_phy(dev, phy2);
1109 if (ret)
1110 goto unreg_thermal;
1111 }
1112
1113 mt7915_init_debugfs(&dev->phy);
1114
1115 return 0;
1116
1117unreg_thermal:
1118 mt7915_unregister_thermal(&dev->phy);
1119unreg_dev:
1120 mt76_unregister_device(&dev->mt76);
1121stop_hw:
1122 mt7915_stop_hardware(dev);
1123free_phy2:
1124 if (phy2)
1125 ieee80211_free_hw(phy2->mt76->hw);
1126 return ret;
1127}
1128
1129void mt7915_unregister_device(struct mt7915_dev *dev)
1130{
1131 mt7915_unregister_ext_phy(dev);
1132 mt7915_unregister_thermal(&dev->phy);
1133 mt76_unregister_device(&dev->mt76);
1134 mt7915_stop_hardware(dev);
1135
1136 mt76_free_device(&dev->mt76);
1137}