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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / f39022abe7aa758b063910387b3e88021bf924c1 / . / target / linux / mediatek / files-5.4 / drivers / net / ethernet / raeth / raether.h
blob: 5316905eea2a0636df735af6cf438e41fd0d3662 [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]1/* Copyright 2016 MediaTek Inc.
2 * Author: Nelson Chang <nelson.chang@mediatek.com>
3 * Author: Carlos Huang <carlos.huang@mediatek.com>
4 * Author: Harry Huang <harry.huang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef RA2882ETHEND_H
16#define RA2882ETHEND_H
17
18#include "raeth_config.h"
19#include "raeth_reg.h"
20#include "ra_dbg_proc.h"
21#include "ra_ioctl.h"
22
23#include <linux/module.h>
24#include <linux/version.h>
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/skbuff.h>
30#include <linux/if_vlan.h>
31#include <linux/if_ether.h>
32#include <linux/fs.h>
33#include <linux/mii.h>
34#include <linux/uaccess.h>
35#if defined(CONFIG_RAETH_TSO)
36#include <linux/tcp.h>
37#include <net/ipv6.h>
38#include <linux/ip.h>
39#include <net/ip.h>
40#include <net/tcp.h>
41#include <linux/in.h>
42#include <linux/ppp_defs.h>
43#include <linux/if_pppox.h>
44#endif
45#include <linux/netdevice.h>
46#include <linux/if_vlan.h>
47#include <linux/ppp_defs.h>
48
49#include <linux/delay.h>
50#include <linux/sched.h>
51
52#include <linux/of_device.h>
53#include <linux/of_address.h>
54#include <linux/of_net.h>
55#include <linux/of_irq.h>
56#include <linux/of_gpio.h>
57#include <linux/mfd/syscon.h>
58#include <linux/regmap.h>
59#include <linux/clk.h>
60#include <linux/regulator/consumer.h>
61
62#include <linux/dma-mapping.h>
63
64#if defined(CONFIG_MACH_MT7623)
65#include <linux/delay.h>
66#endif
67#include <linux/kthread.h>
68#include <linux/prefetch.h>
69
70#include <linux/platform_device.h>
71#include <linux/pm_runtime.h>
72
73#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
74#include <net/ra_nat.h>
75#endif
76
77#ifndef TRUE
78#define TRUE 1
79#endif
80#ifndef FALSE
81#define FALSE 0
82#endif
83
84#define ETH_GPIO_BASE 0x10005000
85
86#if defined(CONFIG_QDMA_MQ)
87#define GMAC1_TXQ_NUM 3
88#define GMAC1_TXQ_TXD_NUM 512
89#define GMAC1_TXD_NUM (GMAC1_TXQ_NUM * GMAC1_TXQ_TXD_NUM)
90#define GMAC2_TXQ_NUM 1
91#define GMAC2_TXQ_TXD_NUM 128
92#define GMAC2_TXD_NUM (GMAC2_TXQ_NUM * GMAC2_TXQ_TXD_NUM)
93#define NUM_TX_DESC (GMAC1_TXD_NUM + GMAC2_TXD_NUM)
94#define TOTAL_TXQ_NUM (GMAC1_TXQ_NUM + GMAC2_TXQ_NUM)
95#else
96#define TOTAL_TXQ_NUM 2
97#endif
98
99#if defined(CONFIG_MACH_MT7623)
100#define NUM_RX_DESC 2048
101#define NUM_QRX_DESC 16
102#define NUM_PQ_RESV 4
103#define FFA 2048
104#define QUEUE_OFFSET 0x10
105#else
106#define NUM_QRX_DESC 16
107#define NUM_PQ_RESV 4
108#define FFA 512
109#define QUEUE_OFFSET 0x10
110#endif
111
112#if defined(CONFIG_PINCTRL_MT7622)
113#define NUM_PQ 64
114#else
115#define NUM_PQ 16
116#endif
117/* #define NUM_TX_MAX_PROCESS NUM_TX_DESC */
118#define NUM_RX_MAX_PROCESS 16
119
120#define MAX_RX_RING_NUM 4
121#define NUM_LRO_RX_DESC 16
122
123#define MAX_RX_LENGTH 1536
124
125#if defined(CONFIG_SUPPORT_OPENWRT)
126#define DEV_NAME "eth0"
127#define DEV2_NAME "eth1"
128#else
129#define DEV_NAME "eth2"
130#define DEV2_NAME "eth3"
131#endif
132
133#if defined(CONFIG_MACH_MT7623)
134#define GMAC0_OFFSET 0xE000
135#define GMAC2_OFFSET 0xE006
136#else
137#define GMAC0_OFFSET 0x28
138#define GMAC2_OFFSET 0x22
139#endif
140
141#if defined(CONFIG_MACH_MT7623)
142#define IRQ_ENET0 232
143#define IRQ_ENET1 231
144#define IRQ_ENET2 230
145#else
146/* NOTE(Nelson): prom version started from 20150806 */
147#define IRQ_ENET0 255
148#define IRQ_ENET1 256
149#define IRQ_ENET2 257
150#endif
151#define MTK_NAPI_WEIGHT 64
152
153#define RAETH_VERSION "STD_v0.1"
154
155/* MT7623 PSE reset workaround */
156#define FE_RESET_POLLING_MS (5000)
157
158/*LEOPARD POLLING*/
159#define PHY_POLLING_MS (1000)
160#define FE_DEFAULT_LAN_IP "192.168.1.1"
161#define IP4_ADDR_LEN 16
162
163#if defined(CONFIG_SOC_MT7621)
164#define MT_TRIGGER_LOW 0
165#else
166#define MT_TRIGGER_LOW IRQF_TRIGGER_LOW
167#endif
168
169/* This enum allows us to identify how the clock is defined on the array of the
170 * clock in the order
171 */
172enum mtk_clks_map {
173 MTK_CLK_ETHIF,
174 MTK_CLK_ESW,
175 MTK_CLK_GP0,
176 MTK_CLK_GP1,
177 MTK_CLK_GP2,
178 MTK_CLK_SGMII_TX250M,
179 MTK_CLK_SGMII_RX250M,
180 MTK_CLK_SGMII_CDR_REF,
181 MTK_CLK_SGMII_CDR_FB,
182 MTK_CLK_SGMII1_TX250M,
183 MTK_CLK_SGMII1_RX250M,
184 MTK_CLK_SGMII1_CDR_REF,
185 MTK_CLK_SGMII1_CDR_FB,
186 MTK_CLK_TRGPLL,
187 MTK_CLK_SGMIPLL,
188 MTK_CLK_ETH1PLL,
189 MTK_CLK_ETH2PLL,
190 MTK_CLK_FE,
191 MTK_CLK_SGMII_TOP,
192 MTK_CLK_MAX
193};
194
195struct END_DEVICE {
196 struct device *dev;
197 unsigned int tx_cpu_owner_idx0;
198#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
199 unsigned int rx_calc_idx[MAX_RX_RING_NUM];
200#endif
201 unsigned int tx_ring_full;
202 unsigned int tx_full; /* NOTE(Nelso): unused, can remove */
203
204 /* PDMA TX PTR */
205 dma_addr_t phy_tx_ring0;
206
207 /* QDMA TX PTR */
208 struct platform_device *qdma_pdev;
209 /* struct sk_buff *free_skb[NUM_TX_DESC]; */
210 struct sk_buff **free_skb;
211 unsigned int tx_dma_ptr;
212 unsigned int tx_cpu_ptr;
213 unsigned int tx_cpu_idx;
214 unsigned int rls_cpu_idx;
215 /* atomic_t free_txd_num[TOTAL_TXQ_NUM]; */
216 atomic_t *free_txd_num;
217 /* unsigned int free_txd_head[TOTAL_TXQ_NUM]; */
218 /* unsigned int free_txd_tail[TOTAL_TXQ_NUM]; */
219 unsigned int *free_txd_head;
220 unsigned int *free_txd_tail;
221 struct QDMA_txdesc *txd_pool;
222 dma_addr_t phy_txd_pool;
223 /* unsigned int txd_pool_info[NUM_TX_DESC]; */
224 unsigned int *txd_pool_info;
225 struct QDMA_txdesc *free_head;
226 unsigned int phy_free_head;
227 unsigned int *free_page_head;
228 dma_addr_t phy_free_page_head;
229 struct PDMA_rxdesc *qrx_ring;
230 dma_addr_t phy_qrx_ring;
231
232 /* TSO */
233 unsigned int skb_txd_num;
234
235 /* MT7623 workaround */
236 struct work_struct reset_task;
237
238 /* workqueue_bh */
239 struct work_struct rx_wq;
240
241 /* tasklet_bh */
242 struct tasklet_struct rx_tasklet;
243
244 /* struct sk_buff *skb_free[NUM_TX_DESC]; */
245 struct sk_buff **skb_free;
246 unsigned int free_idx;
247
248 struct net_device_stats stat; /* The new statistics table. */
249 spinlock_t page_lock; /* spin_lock for cr access critial section */
250 spinlock_t irq_lock; /* spin_lock for isr critial section */
251 spinlock_t mdio_lock; /* spin_lock for mdio reg access */
252 struct PDMA_txdesc *tx_ring0;
253 struct PDMA_rxdesc *rx_ring[MAX_RX_RING_NUM];
254 dma_addr_t phy_rx_ring[MAX_RX_RING_NUM];
255
256 /* void *netrx_skb_data[MAX_RX_RING_NUM][NUM_RX_DESC]; */
257 void **netrx_skb_data[MAX_RX_RING_NUM];
258
259 /* struct sk_buff *netrx0_skbuf[NUM_RX_DESC]; */
260 /*struct sk_buff **netrx0_skbuf;*/
261 void **netrx0_skb_data;
262 /* napi */
263 struct napi_struct napi;
264 struct napi_struct napi_rx;
265 struct napi_struct napi_rx_rss0;
266 struct napi_struct napi_rx_rss1;
267 struct napi_struct napi_rx_rss2;
268 struct napi_struct napi_rx_rss3;
269 struct napi_struct napi_tx;
270 struct net_device dummy_dev;
271
272 /* clock control */
273 struct clk *clks[MTK_CLK_MAX];
274
275 /* gsw device node */
276 struct device_node *switch_np;
277
278 /* GE1 support */
279 struct net_device *netdev;
280 /* GE2 support */
281 struct net_device *pseudo_dev;
282 unsigned int is_pseudo;
283
284 struct mii_if_info mii_info;
285 struct lro_counters lro_counters;
286 struct vlan_group *vlgrp;
287
288 /* virtual base addr from device tree */
289 void __iomem *ethdma_sysctl_base;
290
291 unsigned int irq0;
292 unsigned int irq1;
293 unsigned int irq2;
294 unsigned int irq3;
295 unsigned int esw_irq;
296 void __iomem *fe_tx_int_status;
297 void __iomem *fe_tx_int_enable;
298 void __iomem *fe_rx_int_status;
299 void __iomem *fe_rx_int_enable;
300
301 unsigned int features;
302 unsigned int chip_name;
303 unsigned int architecture;
304
305 /* IP address */
306 char lan_ip4_addr[IP4_ADDR_LEN];
307
308 /* Function pointers */
309 int (*ei_start_xmit)(struct sk_buff *skb, struct net_device *netdev,
310 int gmac_no);
311 int (*ei_xmit_housekeeping)(struct net_device *netdev, int budget);
312 int (*ei_eth_recv)(struct net_device *dev,
313 struct napi_struct *napi,
314 int budget);
315 int (*ei_eth_recv_rss0)(struct net_device *dev,
316 struct napi_struct *napi,
317 int budget);
318 int (*ei_eth_recv_rss1)(struct net_device *dev,
319 struct napi_struct *napi,
320 int budget);
321 int (*ei_eth_recv_rss2)(struct net_device *dev,
322 struct napi_struct *napi,
323 int budget);
324 int (*ei_eth_recv_rss3)(struct net_device *dev,
325 struct napi_struct *napi,
326 int budget);
327 int (*ei_fill_tx_desc)(struct net_device *dev,
328 unsigned long *tx_cpu_owner_idx,
329 struct sk_buff *skb, int gmac_no);
330
331 /* MT7623 PSE reset workaround */
332 struct task_struct *kreset_task;
333 struct task_struct *kphy_poll_task;
334 unsigned int fe_reset_times;
335 unsigned int tx_mask;
336 unsigned int rx_mask;
337 unsigned int *rls_cnt;
338};
339
340struct net_device_stats *ra_get_stats(struct net_device *dev);
341
342int ei_open(struct net_device *dev);
343int ei_close(struct net_device *dev);
344
345int ra2882eth_init(void);
346void ra2882eth_cleanup_module(void);
347
348u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
349u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
350u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr);
351u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr,
352 u32 *read_data);
353u32 mii_mgr_write_cl45(u32 port_num, u32 dev_addr, u32 reg_addr,
354 u32 write_data);
355
356/* HNAT functions */
357#if defined(CONFIG_RA_NAT_NONE)
358static int (*ppe_hook_rx_eth)(struct sk_buff *skb);
359static int (*ppe_hook_tx_eth)(struct sk_buff *skb, int gmac_no);
360#else
361extern int (*ppe_hook_rx_eth)(struct sk_buff *skb);
362extern int (*ppe_hook_tx_eth)(struct sk_buff *skb, int gmac_no);
363#endif
364
365/* PDMA functions */
366int fe_pdma_wait_dma_idle(void);
367int fe_pdma_rx_dma_init(struct net_device *dev);
368int fe_pdma_tx_dma_init(struct net_device *dev);
369void fe_pdma_rx_dma_deinit(struct net_device *dev);
370void fe_pdma_tx_dma_deinit(struct net_device *dev);
371void set_fe_pdma_glo_cfg(void);
372int ei_pdma_start_xmit(struct sk_buff *skb, struct net_device *dev,
373 int gmac_no);
374int ei_pdma_xmit_housekeeping(struct net_device *netdev,
375 int budget);
376int fe_fill_tx_desc(struct net_device *dev,
377 unsigned long *tx_cpu_owner_idx,
378 struct sk_buff *skb,
379 int gmac_no);
380int fe_fill_tx_desc_tso(struct net_device *dev,
381 unsigned long *tx_cpu_owner_idx,
382 struct sk_buff *skb,
383 int gmac_no);
384
385/* QDMA functions */
386int fe_qdma_wait_dma_idle(void);
387int fe_qdma_rx_dma_init(struct net_device *dev);
388int fe_qdma_tx_dma_init(struct net_device *dev);
389void fe_qdma_rx_dma_deinit(struct net_device *dev);
390void fe_qdma_tx_dma_deinit(struct net_device *dev);
391void set_fe_qdma_glo_cfg(void);
392int ei_qdma_start_xmit(struct sk_buff *skb, struct net_device *dev,
393 int gmac_no);
394int ei_qdma_xmit_housekeeping(struct net_device *netdev, int budget);
395int ei_qdma_ioctl(struct net_device *dev, struct ifreq *ifr,
396 struct qdma_ioctl_data *ioctl_data);
397int ephy_ioctl(struct net_device *dev, struct ifreq *ifr,
398 struct ephy_ioctl_data *ioctl_data);
399/* HW LRO functions */
400int fe_hw_lro_init(struct net_device *dev);
401void fe_hw_lro_deinit(struct net_device *dev);
402int fe_hw_lro_recv(struct net_device *dev,
403 struct napi_struct *napi,
404 int budget);
405void fe_set_hw_lro_my_ip(char *lan_ip_addr);
406
407int fe_rss_4ring_init(struct net_device *dev);
408void fe_rss_4ring_deinit(struct net_device *dev);
409int fe_rss_2ring_init(struct net_device *dev);
410void fe_rss_2ring_deinit(struct net_device *dev);
411int fe_rss0_recv(struct net_device *dev,
412 struct napi_struct *napi,
413 int budget);
414int fe_rss1_recv(struct net_device *dev,
415 struct napi_struct *napi,
416 int budget);
417int fe_rss2_recv(struct net_device *dev,
418 struct napi_struct *napi,
419 int budget);
420int fe_rss3_recv(struct net_device *dev,
421 struct napi_struct *napi,
422 int budget);
423static inline void *raeth_alloc_skb_data(size_t size, gfp_t flags)
424{
425#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
426 return kmalloc(size, flags);
427#else
428 return netdev_alloc_frag(size);
429#endif
430}
431
432static inline void raeth_free_skb_data(void *addr)
433{
434#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
435 kfree(addr);
436#else
437 skb_free_frag(addr);
438#endif
439}
440
441static inline struct sk_buff *raeth_build_skb(void *data,
442 unsigned int frag_size)
443{
444#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
445 return build_skb(data, 0);
446#else
447 return build_skb(data, frag_size);
448#endif
449}
450
451extern u32 gmac1_txq_num;
452extern u32 gmac1_txq_txd_num;
453extern u32 gmac1_txd_num;
454extern u32 gmac2_txq_num;
455extern u32 gmac2_txq_txd_num;
456extern u32 gmac2_txd_num;
457extern u32 num_rx_desc;
458extern u32 num_tx_max_process;
459extern u32 num_tx_desc;
460extern u32 total_txq_num;
461extern u32 mac_to_gigaphy_mode_addr;
462extern u32 mac_to_gigaphy_mode_addr2;
463#endif