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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / f39022abe7aa758b063910387b3e88021bf924c1 / . / target / linux / mediatek / files-5.4 / drivers / net / ethernet / raeth / ra_ioctl.h
blob: b94cb3369402b422a205570be79aa94b0cba9e2f [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]1/* Copyright 2016 MediaTek Inc.
2 * Author: Nelson Chang <nelson.chang@mediatek.com>
3 * Author: Carlos Huang <carlos.huang@mediatek.com>
4 * Author: Harry Huang <harry.huang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _RAETH_IOCTL_H
16#define _RAETH_IOCTL_H
17
18/* ioctl commands */
19#define RAETH_SW_IOCTL 0x89F0
20#define RAETH_ESW_REG_READ 0x89F1
21#define RAETH_ESW_REG_WRITE 0x89F2
22#define RAETH_MII_READ 0x89F3
23#define RAETH_MII_WRITE 0x89F4
24#define RAETH_ESW_INGRESS_RATE 0x89F5
25#define RAETH_ESW_EGRESS_RATE 0x89F6
26#define RAETH_ESW_PHY_DUMP 0x89F7
27#define RAETH_QDMA_IOCTL 0x89F8
28#define RAETH_EPHY_IOCTL 0x89F9
29#define RAETH_MII_READ_CL45 0x89FC
30#define RAETH_MII_WRITE_CL45 0x89FD
31#define RAETH_QDMA_SFQ_WEB_ENABLE 0x89FE
32#define RAETH_SET_LAN_IP 0x89FF
33
34/* switch ioctl commands */
35#define SW_IOCTL_SET_EGRESS_RATE 0x0000
36#define SW_IOCTL_SET_INGRESS_RATE 0x0001
37#define SW_IOCTL_SET_VLAN 0x0002
38#define SW_IOCTL_DUMP_VLAN 0x0003
39#define SW_IOCTL_DUMP_TABLE 0x0004
40#define SW_IOCTL_ADD_L2_ADDR 0x0005
41#define SW_IOCTL_DEL_L2_ADDR 0x0006
42#define SW_IOCTL_ADD_MCAST_ADDR 0x0007
43#define SW_IOCTL_DEL_MCAST_ADDR 0x0008
44#define SW_IOCTL_DUMP_MIB 0x0009
45#define SW_IOCTL_ENABLE_IGMPSNOOP 0x000A
46#define SW_IOCTL_DISABLE_IGMPSNOOP 0x000B
47#define SW_IOCTL_SET_PORT_TRUNK 0x000C
48#define SW_IOCTL_GET_PORT_TRUNK 0x000D
49#define SW_IOCTL_SET_PORT_MIRROR 0x000E
50#define SW_IOCTL_GET_PHY_STATUS 0x000F
51#define SW_IOCTL_READ_REG 0x0010
52#define SW_IOCTL_WRITE_REG 0x0011
53#define SW_IOCTL_QOS_EN 0x0012
54#define SW_IOCTL_QOS_SET_TABLE2TYPE 0x0013
55#define SW_IOCTL_QOS_GET_TABLE2TYPE 0x0014
56#define SW_IOCTL_QOS_SET_PORT2TABLE 0x0015
57#define SW_IOCTL_QOS_GET_PORT2TABLE 0x0016
58#define SW_IOCTL_QOS_SET_PORT2PRI 0x0017
59#define SW_IOCTL_QOS_GET_PORT2PRI 0x0018
60#define SW_IOCTL_QOS_SET_DSCP2PRI 0x0019
61#define SW_IOCTL_QOS_GET_DSCP2PRI 0x001a
62#define SW_IOCTL_QOS_SET_PRI2QUEUE 0x001b
63#define SW_IOCTL_QOS_GET_PRI2QUEUE 0x001c
64#define SW_IOCTL_QOS_SET_QUEUE_WEIGHT 0x001d
65#define SW_IOCTL_QOS_GET_QUEUE_WEIGHT 0x001e
66#define SW_IOCTL_SET_PHY_TEST_MODE 0x001f
67#define SW_IOCTL_GET_PHY_REG 0x0020
68#define SW_IOCTL_SET_PHY_REG 0x0021
69#define SW_IOCTL_VLAN_TAG 0x0022
70#define SW_IOCTL_CLEAR_TABLE 0x0023
71#define SW_IOCTL_CLEAR_VLAN 0x0024
72#define SW_IOCTL_SET_VLAN_MODE 0x0025
73
74/*****************QDMA IOCTL DATA*************/
75#define RAETH_QDMA_REG_READ 0x0000
76#define RAETH_QDMA_REG_WRITE 0x0001
77#define RAETH_QDMA_QUEUE_MAPPING 0x0002
78#define RAETH_QDMA_READ_CPU_CLK 0x0003
79/*********************************************/
80/******************EPHY IOCTL DATA************/
81/*MT7622 10/100 phy cal*/
82#define RAETH_VBG_IEXT_CALIBRATION 0x0000
83#define RAETH_TXG_R50_CALIBRATION 0x0001
84#define RAETH_TXG_OFFSET_CALIBRATION 0x0002
85#define RAETH_TXG_AMP_CALIBRATION 0x0003
86#define GE_TXG_R50_CALIBRATION 0x0004
87#define GE_TXG_OFFSET_CALIBRATION 0x0005
88#define GE_TXG_AMP_CALIBRATION 0x0006
89/*********************************************/
90#define REG_ESW_WT_MAC_MFC 0x10
91#define REG_ESW_ISC 0x18
92#define REG_ESW_WT_MAC_ATA1 0x74
93#define REG_ESW_WT_MAC_ATA2 0x78
94#define REG_ESW_WT_MAC_ATWD 0x7C
95#define REG_ESW_WT_MAC_ATC 0x80
96
97#define REG_ESW_TABLE_TSRA1 0x84
98#define REG_ESW_TABLE_TSRA2 0x88
99#define REG_ESW_TABLE_ATRD 0x8C
100
101#define REG_ESW_VLAN_VTCR 0x90
102#define REG_ESW_VLAN_VAWD1 0x94
103#define REG_ESW_VLAN_VAWD2 0x98
104
105#if defined(CONFIG_MACH_MT7623)
106#define REG_ESW_VLAN_ID_BASE 0x100
107#else
108#define REG_ESW_VLAN_ID_BASE 0x50
109#endif
110#define REG_ESW_VLAN_MEMB_BASE 0x70
111#define REG_ESW_TABLE_SEARCH 0x24
112#define REG_ESW_TABLE_STATUS0 0x28
113#define REG_ESW_TABLE_STATUS1 0x2C
114#define REG_ESW_TABLE_STATUS2 0x30
115#define REG_ESW_WT_MAC_AD0 0x34
116#define REG_ESW_WT_MAC_AD1 0x38
117#define REG_ESW_WT_MAC_AD2 0x3C
118
119#if defined(CONFIG_MACH_MT7623)
120#define REG_ESW_MAX 0xFC
121#else
122#define REG_ESW_MAX 0x16C
123#endif
124#define REG_HQOS_MAX 0x3FFF
125
126struct esw_reg {
127 unsigned int off;
128 unsigned int val;
129};
130
131struct ra_mii_ioctl_data {
132 __u32 phy_id;
133 __u32 reg_num;
134 __u32 val_in;
135 __u32 val_out;
136 __u32 port_num;
137 __u32 dev_addr;
138 __u32 reg_addr;
139};
140
141struct ra_switch_ioctl_data {
142 unsigned int cmd;
143 unsigned int on_off;
144 unsigned int port;
145 unsigned int bw;
146 unsigned int vid;
147 unsigned int fid;
148 unsigned int port_map;
149 unsigned int rx_port_map;
150 unsigned int tx_port_map;
151 unsigned int igmp_query_interval;
152 unsigned int reg_addr;
153 unsigned int reg_val;
154 unsigned int mode;
155 unsigned int qos_queue_num;
156 unsigned int qos_type;
157 unsigned int qos_pri;
158 unsigned int qos_dscp;
159 unsigned int qos_table_idx;
160 unsigned int qos_weight;
161 unsigned char mac[6];
162};
163
164struct qdma_ioctl_data {
165 unsigned int cmd;
166 unsigned int off;
167 unsigned int val;
168};
169
170struct ephy_ioctl_data {
171 unsigned int cmd;
172};
173
174struct esw_rate {
175 unsigned int on_off;
176 unsigned int port;
177 unsigned int bw; /*Mbps */
178};
179#endif /* _RAETH_IOCTL_H */