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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / f0de14bb448897c37bd86c8431654c168103bc42 / . / target / linux / mediatek / patches-5.4 / 753-net-mt753x-phy-coverity-scan.patch
blob: bc1bf039a97fb60f84623fd56a519ebcbc72c940 [file] [log] [blame]
developer6a33d162022-12-07 14:51:33 +0800[diff] [blame]1diff -Naur a/drivers/net/phy/mtk/mt753x/mt7531.c b/drivers/net/phy/mtk/mt753x/mt7531.c
2--- a/drivers/net/phy/mtk/mt753x/mt7531.c 2022-11-25 14:11:51.944272549 +0800
3+++ b/drivers/net/phy/mtk/mt753x/mt7531.c 2022-11-25 14:19:49.970820719 +0800
4@@ -1062,6 +1062,7 @@
5 u32 pmcr;
6 u32 speed;
7
8+ pdev = container_of(gsw->dev, struct platform_device, dev);
9 switch_node = of_find_node_by_name(NULL, "switch0");
10 if (switch_node == NULL) {
11 dev_err(&pdev->dev, "switch node invaild\n");
12@@ -1074,7 +1075,6 @@
13 return -EIO;
14 }
15
16- pdev = container_of(gsw->dev, struct platform_device, dev);
17 gsw->sysctrl_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
18 "mediatek,sysctrl");
19 if (IS_ERR(gsw->sysctrl_base)) {
20diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_common.c b/drivers/net/phy/mtk/mt753x/mt753x_common.c
21--- a/drivers/net/phy/mtk/mt753x/mt753x_common.c 2022-11-25 14:12:06.308223474 +0800
22+++ b/drivers/net/phy/mtk/mt753x/mt753x_common.c 2022-11-25 14:21:52.038450276 +0800
23@@ -49,6 +49,9 @@
24 case MAC_SPD_2500:
25 speed = "2.5Gbps";
26 break;
27+ default:
28+ dev_info(gsw->dev, "Invalid speed\n");
29+ return;
30 }
31
32 if (pmsr & MAC_LNK_STS) {
33diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_mdio.c b/drivers/net/phy/mtk/mt753x/mt753x_mdio.c
34--- a/drivers/net/phy/mtk/mt753x/mt753x_mdio.c 2022-11-25 14:12:29.064162894 +0800
35+++ b/drivers/net/phy/mtk/mt753x/mt753x_mdio.c 2022-11-25 17:04:01.973949052 +0800
36@@ -495,7 +495,7 @@
37 struct device_node *np = gsw->dev->of_node;
38 struct reset_control *rstc;
39 int mcm;
40- int ret = -EINVAL;
41+ int ret;
42
43 mcm = of_property_read_bool(np, "mediatek,mcm");
44 if (mcm) {
45diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_nl.c b/drivers/net/phy/mtk/mt753x/mt753x_nl.c
46--- a/drivers/net/phy/mtk/mt753x/mt753x_nl.c 2022-11-25 14:12:12.292202033 +0800
47+++ b/drivers/net/phy/mtk/mt753x/mt753x_nl.c 2022-11-25 17:01:26.881930912 +0800
48@@ -75,8 +75,10 @@
49 len = snprintf(buf, sizeof(buf),
50 "id: %d, model: %s, node: %s\n",
51 gsw->id, gsw->name, gsw->dev->of_node->name);
52- strncat(buff, buf, size - total);
53- total += len;
54+ if (len == strlen(buf)) {
55+ strncat(buff, buf, size - total);
56+ total += len;
57+ }
58 }
59
60 mt753x_put_gsw();
61diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_phy.c b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
62--- a/drivers/net/phy/mtk/mt753x/mt753x_phy.c 2022-11-25 14:12:34.160149995 +0800
63+++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c 2022-11-29 14:12:28.261884707 +0800
64@@ -141,7 +141,7 @@
65 u16 dev1e_17a_tmp, dev1e_e0_tmp;
66
67 /* *** Iext/Rext Cal start ************ */
68- all_ana_cal_status = ANACAL_INIT;
69+ //all_ana_cal_status = ANACAL_INIT;
70 /* analog calibration enable, Rext calibration enable */
71 /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
72 /* 1e_dc[0]:rg_txvos_calen */
73@@ -185,7 +185,7 @@
74 all_ana_cal_status = ANACAL_FINISH;
75 //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
76 } else {
77- dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
78+ //dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
79 dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
80 if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
81 all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
82@@ -580,33 +580,35 @@
83 } else if (phyaddr == 1) {
84 if (calibration_pair == ANACAL_PAIR_A)
85 tx_amp_temp = tx_amp_temp - 1;
86- else if(calibration_pair == ANACAL_PAIR_B)
87- tx_amp_temp = tx_amp_temp ;
88+ //else if(calibration_pair == ANACAL_PAIR_B)
89+ // tx_amp_temp = tx_amp_temp;
90 else if(calibration_pair == ANACAL_PAIR_C)
91 tx_amp_temp = tx_amp_temp - 1;
92 else if(calibration_pair == ANACAL_PAIR_D)
93 tx_amp_temp = tx_amp_temp - 1;
94 } else if (phyaddr == 2) {
95- if (calibration_pair == ANACAL_PAIR_A)
96- tx_amp_temp = tx_amp_temp;
97- else if(calibration_pair == ANACAL_PAIR_B)
98+ //if (calibration_pair == ANACAL_PAIR_A)
99+ // tx_amp_temp = tx_amp_temp;
100+ //else if(calibration_pair == ANACAL_PAIR_B)
101+ if(calibration_pair == ANACAL_PAIR_B)
102 tx_amp_temp = tx_amp_temp - 1;
103- else if(calibration_pair == ANACAL_PAIR_C)
104- tx_amp_temp = tx_amp_temp;
105+ //else if(calibration_pair == ANACAL_PAIR_C)
106+ // tx_amp_temp = tx_amp_temp;
107 else if(calibration_pair == ANACAL_PAIR_D)
108 tx_amp_temp = tx_amp_temp - 1;
109- } else if (phyaddr == 3) {
110- tx_amp_temp = tx_amp_temp;
111+ //} else if (phyaddr == 3) {
112+ // tx_amp_temp = tx_amp_temp;
113 } else if (phyaddr == 4) {
114- if (calibration_pair == ANACAL_PAIR_A)
115- tx_amp_temp = tx_amp_temp;
116- else if(calibration_pair == ANACAL_PAIR_B)
117+ //if (calibration_pair == ANACAL_PAIR_A)
118+ // tx_amp_temp = tx_amp_temp;
119+ //else if(calibration_pair == ANACAL_PAIR_B)
120+ if(calibration_pair == ANACAL_PAIR_B)
121 tx_amp_temp = tx_amp_temp - 1;
122- else if(calibration_pair == ANACAL_PAIR_C)
123- tx_amp_temp = tx_amp_temp;
124- else if(calibration_pair == ANACAL_PAIR_D)
125- tx_amp_temp = tx_amp_temp;
126- }
127+ //else if(calibration_pair == ANACAL_PAIR_C)
128+ // tx_amp_temp = tx_amp_temp;
129+ //else if(calibration_pair == ANACAL_PAIR_D)
130+ // tx_amp_temp = tx_amp_temp;
131+ }
132 reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
133 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
134 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
135@@ -704,7 +706,7 @@
136 reg_backup = 0x0000;
137 reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0));
138 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
139- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
140+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
141 //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
142 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
143 reg_tmp = ((reg_backup & 0x3f) >> 0);
144@@ -712,7 +714,7 @@
145 reg_backup = (reg_backup & (~0x3f));
146 reg_backup |= (reg_tmp << 0);
147 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
148- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
149+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
150 //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
151 }
152 else if(calibration_pair == ANACAL_PAIR_B){
153@@ -722,7 +724,7 @@
154 reg_backup = 0x0000;
155 reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0));
156 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
157- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
158+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
159 //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
160 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
161 reg_tmp = ((reg_backup & 0x3f) >> 0);
162@@ -730,7 +732,7 @@
163 reg_backup = (reg_backup & (~0x3f));
164 reg_backup |= (reg_tmp << 0);
165 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
166- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
167+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
168 //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
169 }
170 else if(calibration_pair == ANACAL_PAIR_C){
171@@ -740,7 +742,7 @@
172 reg_backup = (reg_backup & (~0x3f00));
173 reg_backup |= (reg_tmp << 8);
174 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
175- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
176+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
177 //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
178 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
179 reg_tmp = ((reg_backup & 0x3f) >> 0);
180@@ -748,7 +750,7 @@
181 reg_backup = (reg_backup & (~0x3f));
182 reg_backup |= (reg_tmp << 0);
183 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
184- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
185+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
186 //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
187 }
188 else if(calibration_pair == ANACAL_PAIR_D){
189@@ -758,7 +760,7 @@
190 reg_backup = (reg_backup & (~0x3f00));
191 reg_backup |= (reg_tmp << 8);
192 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
193- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
194+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
195 //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
196 reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
197 reg_tmp = ((reg_backup & 0x3f) >> 0);
198@@ -766,7 +768,7 @@
199 reg_backup = (reg_backup & (~0x3f));
200 reg_backup |= (reg_tmp << 0);
201 tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
202- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
203+ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
204 //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
205 }
206