blob: 8de4c2abeee7460cc4603a6e5c82cf2901f00ba8 [file] [log] [blame]
developer44e1bbf2022-01-28 17:20:00 +08001From 44ae4ed142265a6d50a9d3e6f4c395f97b6849ab Mon Sep 17 00:00:00 2001
2From: Zhanyong Wang <zhanyong.wang@mediatek.com>
3Date: Sat, 6 Nov 2021 20:06:30 +0800
4Subject: [PATCH 2/5] nvmem: mtk-efuse: support minimum one byte access stride
5 and granularity
6
7In order to support nvmem bits property, should support minimum 1 byte
8read stride and minimum 1 byte read granularity at the same time.
9
10Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
11Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
12Change-Id: Iafe1ebf195d58a3e9e3518913f795d14a01dfd3b
13---
14 drivers/nvmem/mtk-efuse.c | 13 +++++++------
15 1 file changed, 7 insertions(+), 6 deletions(-)
16
17diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
18index 856d9c3fc38e..2e728fed0b49 100644
19--- a/drivers/nvmem/mtk-efuse.c
20+++ b/drivers/nvmem/mtk-efuse.c
21@@ -19,11 +19,12 @@ static int mtk_reg_read(void *context,
22 unsigned int reg, void *_val, size_t bytes)
23 {
24 struct mtk_efuse_priv *priv = context;
25- u32 *val = _val;
26- int i = 0, words = bytes / 4;
27+ void __iomem *addr = priv->base + reg;
28+ u8 *val = _val;
29+ int i;
30
31- while (words--)
32- *val++ = readl(priv->base + reg + (i++ * 4));
33+ for (i = 0; i < bytes; i++, val++)
34+ *val = readb(addr + i);
35
36 return 0;
37 }
38@@ -58,8 +59,8 @@ static int mtk_efuse_probe(struct platform_device *pdev)
39 if (IS_ERR(priv->base))
40 return PTR_ERR(priv->base);
41
42- econfig.stride = 4;
43- econfig.word_size = 4;
44+ econfig.stride = 1;
45+ econfig.word_size = 1;
46 econfig.reg_read = mtk_reg_read;
47 econfig.reg_write = mtk_reg_write;
48 econfig.size = resource_size(res);
49--
502.18.0
51