developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7986b.dtsi" |
| 3 | / { |
| 4 | model = "MediaTek MT7986b RFB"; |
| 5 | compatible = "mediatek,mt7986b-rfb"; |
| 6 | chosen { |
| 7 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 8 | earlycon=uart8250,mmio32,0x11002000"; |
| 9 | }; |
| 10 | |
| 11 | memory { |
| 12 | // fpga ddr2: 128MB*2 |
| 13 | reg = <0 0x40000000 0 0x10000000>; |
| 14 | }; |
developer | c20f345 | 2021-05-26 17:27:35 +0800 | [diff] [blame] | 15 | |
| 16 | nmbm_snfi { |
| 17 | compatible = "generic,nmbm"; |
| 18 | |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <1>; |
| 21 | |
| 22 | lower-mtd-device = <&snand>; |
| 23 | forced-create; |
developer | c9faf4a | 2021-06-17 09:22:21 +0800 | [diff] [blame] | 24 | empty-page-ecc-protected; |
developer | c20f345 | 2021-05-26 17:27:35 +0800 | [diff] [blame] | 25 | |
| 26 | partitions { |
| 27 | compatible = "fixed-partitions"; |
| 28 | #address-cells = <1>; |
| 29 | #size-cells = <1>; |
| 30 | |
| 31 | partition@0 { |
| 32 | label = "BL2"; |
| 33 | reg = <0x00000 0x0100000>; |
| 34 | read-only; |
| 35 | }; |
| 36 | |
| 37 | partition@100000 { |
| 38 | label = "u-boot-env"; |
| 39 | reg = <0x0100000 0x0080000>; |
| 40 | }; |
| 41 | |
| 42 | partition@180000 { |
| 43 | label = "Factory"; |
| 44 | reg = <0x180000 0x0200000>; |
| 45 | }; |
| 46 | |
| 47 | partition@380000 { |
| 48 | label = "FIP"; |
| 49 | reg = <0x380000 0x0200000>; |
| 50 | }; |
| 51 | |
| 52 | partition@580000 { |
| 53 | label = "ubi"; |
| 54 | reg = <0x580000 0x4000000>; |
| 55 | }; |
| 56 | }; |
| 57 | }; |
developer | 86fc2a7 | 2021-06-23 17:30:23 +0800 | [diff] [blame] | 58 | |
| 59 | nmbm_spim_nand { |
| 60 | compatible = "generic,nmbm"; |
| 61 | |
| 62 | #address-cells = <1>; |
| 63 | #size-cells = <1>; |
| 64 | |
| 65 | lower-mtd-device = <&spi_nand>; |
| 66 | forced-create; |
| 67 | |
| 68 | partitions { |
| 69 | compatible = "fixed-partitions"; |
| 70 | #address-cells = <1>; |
| 71 | #size-cells = <1>; |
| 72 | |
| 73 | partition@0 { |
| 74 | label = "BL2"; |
| 75 | reg = <0x00000 0x0100000>; |
| 76 | read-only; |
| 77 | }; |
| 78 | |
| 79 | partition@100000 { |
| 80 | label = "u-boot-env"; |
| 81 | reg = <0x0100000 0x0080000>; |
| 82 | }; |
| 83 | |
| 84 | partition@180000 { |
| 85 | label = "Factory"; |
| 86 | reg = <0x180000 0x0200000>; |
| 87 | }; |
| 88 | |
| 89 | partition@380000 { |
| 90 | label = "FIP"; |
| 91 | reg = <0x380000 0x0200000>; |
| 92 | }; |
| 93 | |
| 94 | partition@580000 { |
| 95 | label = "ubi"; |
| 96 | reg = <0x580000 0x4000000>; |
| 97 | }; |
| 98 | }; |
| 99 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | &uart0 { |
| 103 | status = "okay"; |
| 104 | }; |
| 105 | |
| 106 | &watchdog { |
| 107 | status = "okay"; |
| 108 | }; |
| 109 | |
| 110 | ð { |
| 111 | status = "okay"; |
| 112 | |
| 113 | gmac0: mac@0 { |
| 114 | compatible = "mediatek,eth-mac"; |
| 115 | reg = <0>; |
| 116 | phy-mode = "2500base-x"; |
| 117 | |
| 118 | fixed-link { |
| 119 | speed = <2500>; |
| 120 | full-duplex; |
| 121 | pause; |
| 122 | }; |
| 123 | }; |
| 124 | |
| 125 | gmac1: mac@1 { |
| 126 | compatible = "mediatek,eth-mac"; |
| 127 | reg = <1>; |
| 128 | phy-mode = "2500base-x"; |
| 129 | |
| 130 | fixed-link { |
| 131 | speed = <2500>; |
| 132 | full-duplex; |
| 133 | pause; |
| 134 | }; |
| 135 | }; |
| 136 | |
| 137 | mdio: mdio-bus { |
| 138 | #address-cells = <1>; |
| 139 | #size-cells = <0>; |
| 140 | |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 141 | phy5: phy@5 { |
| 142 | compatible = "ethernet-phy-id67c9.de0a"; |
| 143 | reg = <5>; |
| 144 | reset-gpios = <&pio 6 1>; |
| 145 | reset-deassert-us = <20000>; |
| 146 | phy-mode = "2500base-x"; |
| 147 | }; |
| 148 | |
| 149 | phy6: phy@6 { |
| 150 | compatible = "ethernet-phy-id67c9.de0a"; |
| 151 | reg = <6>; |
| 152 | phy-mode = "2500base-x"; |
| 153 | }; |
| 154 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 155 | switch@0 { |
| 156 | compatible = "mediatek,mt7531"; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 157 | reg = <31>; |
developer | 5105943 | 2021-05-03 16:01:06 +0800 | [diff] [blame] | 158 | reset-gpios = <&pio 5 0>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 159 | |
| 160 | ports { |
| 161 | #address-cells = <1>; |
| 162 | #size-cells = <0>; |
| 163 | |
| 164 | port@0 { |
| 165 | reg = <0>; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 166 | label = "lan0"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 167 | }; |
| 168 | |
| 169 | port@1 { |
| 170 | reg = <1>; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 171 | label = "lan1"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 172 | }; |
| 173 | |
| 174 | port@2 { |
| 175 | reg = <2>; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 176 | label = "lan2"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 177 | }; |
| 178 | |
| 179 | port@3 { |
| 180 | reg = <3>; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 181 | label = "lan3"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 182 | }; |
| 183 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 184 | port@6 { |
| 185 | reg = <6>; |
| 186 | label = "cpu"; |
| 187 | ethernet = <&gmac0>; |
| 188 | phy-mode = "2500base-x"; |
| 189 | |
| 190 | fixed-link { |
| 191 | speed = <2500>; |
| 192 | full-duplex; |
| 193 | pause; |
| 194 | }; |
| 195 | }; |
| 196 | }; |
| 197 | }; |
| 198 | }; |
| 199 | }; |
| 200 | |
| 201 | &hnat { |
developer | e576351 | 2021-05-21 01:04:58 +0800 | [diff] [blame] | 202 | mtketh-wan = "eth1"; |
developer | d7edc13 | 2021-05-06 13:49:50 +0800 | [diff] [blame] | 203 | mtketh-lan = "lan"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 204 | mtketh-max-gmac = <2>; |
| 205 | status = "okay"; |
| 206 | }; |
| 207 | |
| 208 | &spi0 { |
| 209 | pinctrl-names = "default"; |
| 210 | pinctrl-0 = <&spi_flash_pins>; |
| 211 | cs-gpios = <0>, <0>; |
| 212 | status = "okay"; |
| 213 | spi_nor@0 { |
| 214 | #address-cells = <1>; |
| 215 | #size-cells = <1>; |
| 216 | compatible = "jedec,spi-nor"; |
| 217 | reg = <0>; |
| 218 | spi-max-frequency = <20000000>; |
| 219 | spi-tx-buswidth = <4>; |
| 220 | spi-rx-buswidth = <4>; |
| 221 | |
| 222 | partition@00000 { |
| 223 | label = "BL2"; |
| 224 | reg = <0x00000 0x0040000>; |
| 225 | }; |
| 226 | partition@40000 { |
| 227 | label = "u-boot-env"; |
| 228 | reg = <0x40000 0x0010000>; |
| 229 | }; |
developer | 298705c | 2021-06-05 18:48:19 +0800 | [diff] [blame] | 230 | factory: partition@50000 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 231 | label = "Factory"; |
| 232 | reg = <0x50000 0x00B0000>; |
| 233 | }; |
| 234 | partition@100000 { |
| 235 | label = "FIP"; |
| 236 | reg = <0x100000 0x0080000>; |
| 237 | }; |
| 238 | partition@180000 { |
| 239 | label = "firmware"; |
| 240 | reg = <0x180000 0xE00000>; |
| 241 | }; |
| 242 | }; |
developer | 86fc2a7 | 2021-06-23 17:30:23 +0800 | [diff] [blame] | 243 | spi_nand: spi_nand@1 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 244 | #address-cells = <1>; |
| 245 | #size-cells = <1>; |
| 246 | compatible = "spi-nand"; |
| 247 | reg = <1>; |
| 248 | spi-max-frequency = <20000000>; |
| 249 | spi-tx-buswidth = <4>; |
| 250 | spi-rx-buswidth = <4>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 251 | }; |
| 252 | }; |
| 253 | |
| 254 | &snand { |
| 255 | pinctrl-names = "default"; |
| 256 | /* pin shared with spic */ |
| 257 | pinctrl-0 = <&snfi_pins>; |
| 258 | status = "okay"; |
| 259 | mediatek,quad-spi; |
| 260 | |
| 261 | partitions { |
| 262 | compatible = "fixed-partitions"; |
| 263 | #address-cells = <1>; |
| 264 | #size-cells = <1>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 265 | }; |
| 266 | }; |
| 267 | |
| 268 | &spi1 { |
| 269 | pinctrl-names = "default"; |
| 270 | /* pin shared with snfi */ |
| 271 | pinctrl-0 = <&spic_pins>; |
| 272 | status = "okay"; |
| 273 | }; |
| 274 | |
| 275 | &pio { |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 276 | spi_flash_pins: spi-flash-pins-33-to-38 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 277 | mux { |
| 278 | function = "flash"; |
| 279 | groups = "spi0", "spi0_wp_hold"; |
| 280 | }; |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 281 | conf-pu { |
| 282 | pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; |
| 283 | drive-strength = <MTK_DRIVE_8mA>; |
| 284 | mediatek,pull-up-adv = <0>; /* bias-disable */ |
| 285 | }; |
| 286 | conf-pd { |
| 287 | pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; |
| 288 | drive-strength = <MTK_DRIVE_8mA>; |
| 289 | mediatek,pull-down-adv = <0>; /* bias-disable */ |
| 290 | }; |
| 291 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 292 | }; |
| 293 | |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 294 | snfi_pins: snfi-pins-23-to-28 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 295 | mux { |
| 296 | function = "flash"; |
| 297 | groups = "snfi"; |
| 298 | }; |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 299 | conf-clk { |
| 300 | pins = "SPI0_CLK"; |
| 301 | drive-strength = <MTK_DRIVE_8mA>; |
| 302 | mediatek,pull-down-adv = <0>; /* bias-disable */ |
| 303 | }; |
| 304 | conf-pu { |
| 305 | pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; |
| 306 | drive-strength = <MTK_DRIVE_6mA>; |
| 307 | mediatek,pull-up-adv = <0>; /* bias-disable */ |
| 308 | }; |
| 309 | conf-pd { |
| 310 | pins = "SPI0_MOSI", "SPI0_MISO"; |
| 311 | drive-strength = <MTK_DRIVE_6mA>; |
| 312 | mediatek,pull-down-adv = <0>; /* bias-disable */ |
| 313 | }; |
| 314 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 315 | }; |
| 316 | |
| 317 | spic_pins: spi1-pins { |
| 318 | mux { |
| 319 | function = "spi"; |
developer | 19d22f6 | 2021-05-27 17:36:23 +0800 | [diff] [blame] | 320 | groups = "spi1_2"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 321 | }; |
| 322 | }; |
| 323 | }; |