blob: b9263839221102e0e48c835970950a4fd8dba822 [file] [log] [blame]
developer705722e2021-12-14 17:47:28 +08001diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
developer32e626c2021-12-14 11:01:32 +08002index 7c56ee2..3a5a456 100644
developer705722e2021-12-14 17:47:28 +08003--- a/drivers/pwm/pwm-mediatek.c
4+++ b/drivers/pwm/pwm-mediatek.c
developer32e626c2021-12-14 11:01:32 +08005@@ -33,10 +32,13 @@
6 #define PWM45THRES_FIXUP 0x34
7
8 #define PWM_CLK_DIV_MAX 7
9+#define REG_V1 1
10+#define REG_V2 2
11
12 struct pwm_mediatek_of_data {
13 unsigned int num_pwms;
14 bool pwm45_fixup;
15+ int reg_ver;
16 };
17
18 /**
19@@ -57,10 +59,14 @@ struct pwm_mediatek_chip {
20 const struct pwm_mediatek_of_data *soc;
21 };
22
23-static const unsigned int pwm_mediatek_reg_offset[] = {
24+static const unsigned int mtk_pwm_reg_offset_v1[] = {
25 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
26 };
27
28+static const unsigned int mtk_pwm_reg_offset_v2[] = {
29+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x1c0, 0x200, 0x0240
30+};
31+
32 static inline struct pwm_mediatek_chip *
33 to_pwm_mediatek_chip(struct pwm_chip *chip)
34 {
35@@ -108,14 +114,38 @@ static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
36 static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
37 unsigned int num, unsigned int offset)
38 {
39- return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
40+ u32 pwm_offset;
41+
42+ switch (chip->soc->reg_ver) {
43+ case REG_V2:
44+ pwm_offset = mtk_pwm_reg_offset_v2[num];
45+ break;
46+
47+ case REG_V1:
48+ default:
49+ pwm_offset = mtk_pwm_reg_offset_v1[num];
50+ }
51+
52+ return readl(chip->regs + pwm_offset + offset);
53 }
54
55 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
56 unsigned int num, unsigned int offset,
57 u32 value)
58 {
59- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
60+ u32 pwm_offset;
61+
62+ switch (chip->soc->reg_ver) {
63+ case REG_V2:
64+ pwm_offset = mtk_pwm_reg_offset_v2[num];
65+ break;
66+
67+ case REG_V1:
68+ default:
69+ pwm_offset = mtk_pwm_reg_offset_v1[num];
70+ }
71+
72+ writel(value, chip->regs + pwm_offset + offset);
73 }
74
75 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
76@@ -281,36 +311,49 @@ static int pwm_mediatek_remove(struct platform_device *pdev)
77 static const struct pwm_mediatek_of_data mt2712_pwm_data = {
78 .num_pwms = 8,
79 .pwm45_fixup = false,
80+ .reg_ver = REG_V1,
81 };
82
83 static const struct pwm_mediatek_of_data mt7622_pwm_data = {
84 .num_pwms = 6,
85 .pwm45_fixup = false,
86+ .reg_ver = REG_V1,
87 };
88
89 static const struct pwm_mediatek_of_data mt7623_pwm_data = {
90 .num_pwms = 5,
91 .pwm45_fixup = true,
92+ .reg_ver = REG_V1,
93 };
94
95 static const struct pwm_mediatek_of_data mt7628_pwm_data = {
96 .num_pwms = 4,
97 .pwm45_fixup = true,
98+ .reg_ver = REG_V1,
99 };
100
101 static const struct pwm_mediatek_of_data mt7629_pwm_data = {
102 .num_pwms = 1,
103 .pwm45_fixup = false,
104+ .reg_ver = REG_V1,
105+};
106+
107+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
108+ .num_pwms = 3,
109+ .pwm45_fixup = false,
110+ .reg_ver = REG_V2,
111 };
112
113 static const struct pwm_mediatek_of_data mt7986_pwm_data = {
114 .num_pwms = 2,
115 .pwm45_fixup = false,
116+ .reg_ver = REG_V2,
117 };
118
119 static const struct pwm_mediatek_of_data mt8516_pwm_data = {
120 .num_pwms = 5,
121 .pwm45_fixup = false,
122+ .reg_ver = REG_V1,
123 };
124
125 static const struct of_device_id pwm_mediatek_of_match[] = {
126@@ -319,6 +362,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = {
127 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
128 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
129 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
130+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
131 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
132 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
133 { },