developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame^] | 1 | From d86af0076cbf7d99bdb4f28115159643b79ad3fa Mon Sep 17 00:00:00 2001 |
| 2 | From: Sujuan Chen <sujuan.chen@mediatek.com> |
| 3 | Date: Wed, 18 May 2022 11:08:15 +0800 |
| 4 | Subject: [PATCH 5/8] 9994-ethernet-update-ppe-from-mt7622-to-mt7986 |
| 5 | |
| 6 | Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com> |
| 7 | --- |
| 8 | drivers/net/ethernet/mediatek/mtk_eth_soc.c | 14 +++- |
| 9 | drivers/net/ethernet/mediatek/mtk_eth_soc.h | 7 +- |
| 10 | drivers/net/ethernet/mediatek/mtk_ppe.c | 24 ++++--- |
| 11 | drivers/net/ethernet/mediatek/mtk_ppe.h | 69 ++++++++++--------- |
| 12 | .../net/ethernet/mediatek/mtk_ppe_offload.c | 7 +- |
| 13 | drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 10 +++ |
| 14 | 6 files changed, 86 insertions(+), 45 deletions(-) |
| 15 | |
| 16 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 17 | index 2121335a1..01fc1e5c0 100644 |
| 18 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 19 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 20 | @@ -1467,16 +1467,27 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, |
| 21 | skb_checksum_none_assert(skb); |
| 22 | skb->protocol = eth_type_trans(skb, netdev); |
| 23 | |
| 24 | - hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; |
| 25 | +#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) |
| 26 | + hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2; |
| 27 | +#else |
| 28 | + hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; |
| 29 | +#endif |
| 30 | if (hash != MTK_RXD4_FOE_ENTRY) { |
| 31 | hash = jhash_1word(hash, 0); |
| 32 | skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); |
| 33 | } |
| 34 | |
| 35 | +#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) |
| 36 | + reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON_V2, trxd.rxd5); |
| 37 | + if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) |
| 38 | + mtk_ppe_check_skb(eth->ppe, skb, |
| 39 | + trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2); |
| 40 | +#else |
| 41 | reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); |
| 42 | if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) |
| 43 | mtk_ppe_check_skb(eth->ppe, skb, |
| 44 | trxd.rxd4 & MTK_RXD4_FOE_ENTRY); |
| 45 | +#endif |
| 46 | |
| 47 | if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { |
| 48 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
| 49 | @@ -3926,13 +3937,14 @@ static const struct mtk_soc_data mt7986_data = { |
| 50 | .required_clks = MT7986_CLKS_BITMAP, |
| 51 | .required_pctl = false, |
| 52 | .has_sram = true, |
| 53 | + .offload_version = 2, |
| 54 | .rss_num = 0, |
| 55 | .txrx = { |
| 56 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
| 57 | .rxd_size = sizeof(struct mtk_rx_dma), |
| 58 | .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, |
| 59 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
| 60 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2, |
| 61 | }, |
| 62 | }; |
| 63 | |
| 64 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 65 | index b52378bd6..fce1a7172 100644 |
| 66 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 67 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 68 | @@ -110,7 +110,7 @@ |
| 69 | #define MTK_GDMA_TCS_EN BIT(21) |
| 70 | #define MTK_GDMA_UCS_EN BIT(20) |
| 71 | #define MTK_GDMA_TO_PDMA 0x0 |
| 72 | -#define MTK_GDMA_TO_PPE 0x4444 |
| 73 | +#define MTK_GDMA_TO_PPE 0x3333 |
| 74 | #define MTK_GDMA_DROP_ALL 0x7777 |
| 75 | |
| 76 | /* Unicast Filter MAC Address Register - Low */ |
| 77 | @@ -560,6 +560,11 @@ |
| 78 | #define MTK_RXD4_SRC_PORT GENMASK(21, 19) |
| 79 | #define MTK_RXD4_ALG GENMASK(31, 22) |
| 80 | |
| 81 | +/* QDMA descriptor rxd4 */ |
| 82 | +#define MTK_RXD5_FOE_ENTRY_V2 GENMASK(14, 0) |
| 83 | +#define MTK_RXD5_PPE_CPU_REASON_V2 GENMASK(22, 18) |
| 84 | +#define MTK_RXD5_SRC_PORT_V2 GENMASK(29, 26) |
| 85 | + |
| 86 | /* QDMA descriptor rxd4 */ |
| 87 | #define RX_DMA_L4_VALID BIT(24) |
| 88 | #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ |
| 89 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 90 | index 3d75c22be..d46e91178 100755 |
| 91 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 92 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 93 | @@ -122,7 +122,7 @@ static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e) |
| 94 | hash = (hash >> 24) | ((hash & 0xffffff) << 8); |
| 95 | hash ^= hv1 ^ hv2 ^ hv3; |
| 96 | hash ^= hash >> 16; |
| 97 | - hash <<= 1; |
| 98 | + hash <<= 2; |
| 99 | hash &= MTK_PPE_ENTRIES - 1; |
| 100 | |
| 101 | return hash; |
| 102 | @@ -171,8 +171,12 @@ int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto, |
| 103 | MTK_FOE_IB1_BIND_CACHE; |
| 104 | entry->ib1 = val; |
| 105 | |
| 106 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 107 | + val = FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0xf) | |
| 108 | +#else |
| 109 | val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) | |
| 110 | FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0x1f) | |
| 111 | +#endif |
| 112 | FIELD_PREP(MTK_FOE_IB2_DEST_PORT, pse_port); |
| 113 | |
| 114 | if (is_multicast_ether_addr(dest_mac)) |
| 115 | @@ -359,12 +358,19 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, |
| 116 | |
| 117 | *ib2 &= ~MTK_FOE_IB2_PORT_MG; |
| 118 | *ib2 |= MTK_FOE_IB2_WDMA_WINFO; |
| 119 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 120 | + *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq); |
| 121 | + |
| 122 | + l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) | |
| 123 | + FIELD_PREP(MTK_FOE_WINFO_BSS, bss); |
| 124 | +#else |
| 125 | if (wdma_idx) |
| 126 | *ib2 |= MTK_FOE_IB2_WDMA_DEVIDX; |
| 127 | |
| 128 | l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) | |
| 129 | FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) | |
| 130 | FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq); |
| 131 | +#endif |
| 132 | |
| 133 | return 0; |
| 134 | } |
| 135 | @@ -741,6 +738,9 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
| 136 | MTK_PPE_TB_CFG_AGE_TCP | |
| 137 | MTK_PPE_TB_CFG_AGE_UDP | |
| 138 | MTK_PPE_TB_CFG_AGE_TCP_FIN | |
| 139 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 140 | + MTK_PPE_TB_CFG_INFO_SEL | |
| 141 | +#endif |
| 142 | FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS, |
| 143 | MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD) | |
| 144 | FIELD_PREP(MTK_PPE_TB_CFG_KEEPALIVE, |
| 145 | @@ -757,7 +755,8 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
| 146 | |
| 147 | mtk_ppe_cache_enable(ppe, true); |
| 148 | |
| 149 | - val = MTK_PPE_FLOW_CFG_IP4_TCP_FRAG | |
| 150 | + val = MTK_PPE_MD_TOAP_BYP_CRSN0 | |
| 151 | + MTK_PPE_MD_TOAP_BYP_CRSN1 | |
| 152 | + MTK_PPE_MD_TOAP_BYP_CRSN2 | |
| 153 | - MTK_PPE_FLOW_CFG_IP4_UDP_FRAG | |
| 154 | MTK_PPE_FLOW_CFG_IP6_3T_ROUTE | |
| 155 | MTK_PPE_FLOW_CFG_IP6_5T_ROUTE | |
| 156 | @@ -765,7 +765,8 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
| 157 | MTK_PPE_FLOW_CFG_IP4_NAT | |
| 158 | MTK_PPE_FLOW_CFG_IP4_NAPT | |
| 159 | MTK_PPE_FLOW_CFG_IP4_DSLITE | |
| 160 | - MTK_PPE_FLOW_CFG_IP4_NAT_FRAG; |
| 161 | + MTK_PPE_FLOW_CFG_IP4_NAT_FRAG | |
| 162 | + MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY; |
| 163 | ppe_w32(ppe, MTK_PPE_FLOW_CFG, val); |
| 164 | |
| 165 | val = FIELD_PREP(MTK_PPE_UNBIND_AGE_MIN_PACKETS, 1000) | |
| 166 | @@ -800,6 +801,11 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
| 167 | |
| 168 | ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0); |
| 169 | |
| 170 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 171 | + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); |
| 172 | + ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); |
| 173 | +#endif |
| 174 | + |
| 175 | return 0; |
| 176 | } |
| 177 | |
| 178 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 179 | index 1f5cf1c9a..a76f4b0ac 100644 |
| 180 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 181 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 182 | @@ -8,7 +8,11 @@ |
| 183 | #include <linux/bitfield.h> |
| 184 | #include <linux/rhashtable.h> |
| 185 | |
| 186 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 187 | +#define MTK_ETH_PPE_BASE 0x2000 |
| 188 | +#else |
| 189 | #define MTK_ETH_PPE_BASE 0xc00 |
| 190 | +#endif |
| 191 | |
| 192 | #define MTK_PPE_ENTRIES_SHIFT 3 |
| 193 | #define MTK_PPE_ENTRIES (1024 << MTK_PPE_ENTRIES_SHIFT) |
| 194 | @@ -16,20 +16,40 @@ |
| 195 | #define MTK_PPE_WAIT_TIMEOUT_US 1000000 |
| 196 | |
| 197 | #define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) |
| 198 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 199 | +#define MTK_FOE_IB1_UNBIND_SRC_PORT GENMASK(11, 8) |
| 200 | +#define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(19, 12) |
| 201 | +#define MTK_FOE_IB1_UNBIND_PREBIND BIT(22) |
| 202 | +#define MTK_FOE_IB1_UNBIND_PACKET_TYPE GENMASK(27, 23) |
| 203 | +#define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(7, 0) |
| 204 | +#define MTK_FOE_IB1_BIND_SRC_PORT GENMASK(11, 8) |
| 205 | +#define MTK_FOE_IB1_BIND_MC BIT(12) |
| 206 | +#define MTK_FOE_IB1_BIND_KEEPALIVE BIT(13) |
| 207 | +#define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(16, 14) |
| 208 | +#define MTK_FOE_IB1_BIND_PPPOE BIT(17) |
| 209 | +#define MTK_FOE_IB1_BIND_VLAN_TAG BIT(18) |
| 210 | +#define MTK_FOE_IB1_BIND_PKT_SAMPLE BIT(19) |
| 211 | +#define MTK_FOE_IB1_BIND_CACHE BIT(20) |
| 212 | +#define MTK_FOE_IB1_BIND_TUNNEL_DECAP BIT(21) |
| 213 | +#define MTK_FOE_IB1_BIND_TTL BIT(22) |
| 214 | +#define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 23) |
| 215 | +#else |
| 216 | #define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) |
| 217 | #define MTK_FOE_IB1_UNBIND_PREBIND BIT(24) |
| 218 | |
| 219 | #define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) |
| 220 | #define MTK_FOE_IB1_BIND_KEEPALIVE BIT(15) |
| 221 | #define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(18, 16) |
| 222 | #define MTK_FOE_IB1_BIND_PPPOE BIT(19) |
| 223 | #define MTK_FOE_IB1_BIND_VLAN_TAG BIT(20) |
| 224 | #define MTK_FOE_IB1_BIND_PKT_SAMPLE BIT(21) |
| 225 | #define MTK_FOE_IB1_BIND_CACHE BIT(22) |
| 226 | #define MTK_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) |
| 227 | #define MTK_FOE_IB1_BIND_TTL BIT(24) |
| 228 | |
| 229 | #define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 25) |
| 230 | +#endif |
| 231 | + |
| 232 | #define MTK_FOE_IB1_STATE GENMASK(29, 28) |
| 233 | #define MTK_FOE_IB1_UDP BIT(30) |
| 234 | #define MTK_FOE_IB1_STATIC BIT(31) |
| 235 | @@ -44,24 +47,42 @@ enum { |
| 236 | MTK_PPE_PKT_TYPE_IPV6_6RD = 7, |
| 237 | }; |
| 238 | |
| 239 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 240 | +#define MTK_FOE_IB2_QID GENMASK(6, 0) |
| 241 | +#define MTK_FOE_IB2_PORT_MG BIT(7) |
| 242 | +#define MTK_FOE_IB2_PSE_QOS BIT(8) |
| 243 | +#define MTK_FOE_IB2_DEST_PORT GENMASK(12, 9) |
| 244 | +#define MTK_FOE_IB2_MULTICAST BIT(13) |
| 245 | +#define MTK_FOE_IB2_MIB_CNT BIT(15) |
| 246 | +#define MTK_FOE_IB2_RX_IDX GENMASK(18, 17) |
| 247 | +#define MTK_FOE_IB2_WDMA_WINFO BIT(19) |
| 248 | +#define MTK_FOE_IB2_PORT_AG GENMASK(23, 20) |
| 249 | +#else |
| 250 | #define MTK_FOE_IB2_QID GENMASK(3, 0) |
| 251 | #define MTK_FOE_IB2_PSE_QOS BIT(4) |
| 252 | #define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5) |
| 253 | #define MTK_FOE_IB2_MULTICAST BIT(8) |
| 254 | |
| 255 | #define MTK_FOE_IB2_WDMA_QID2 GENMASK(13, 12) |
| 256 | +#define MTK_FOE_IB2_MIB_CNT BIT(15) |
| 257 | #define MTK_FOE_IB2_WDMA_DEVIDX BIT(16) |
| 258 | #define MTK_FOE_IB2_WDMA_WINFO BIT(17) |
| 259 | |
| 260 | #define MTK_FOE_IB2_PORT_MG GENMASK(17, 12) |
| 261 | |
| 262 | #define MTK_FOE_IB2_PORT_AG GENMASK(23, 18) |
| 263 | +#endif |
| 264 | |
| 265 | #define MTK_FOE_IB2_DSCP GENMASK(31, 24) |
| 266 | |
| 267 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 268 | +#define MTK_FOE_WINFO_BSS GENMASK(5, 0) |
| 269 | +#define MTK_FOE_WINFO_WCID GENMASK(15, 6) |
| 270 | +#else |
| 271 | #define MTK_FOE_VLAN2_WINFO_BSS GENMASK(5, 0) |
| 272 | #define MTK_FOE_VLAN2_WINFO_WCID GENMASK(13, 6) |
| 273 | #define MTK_FOE_VLAN2_WINFO_RING GENMASK(15, 14) |
| 274 | +#endif |
| 275 | |
| 276 | enum { |
| 277 | MTK_FOE_STATE_INVALID, |
| 278 | @@ -83,6 +81,11 @@ struct mtk_foe_mac_info { |
| 279 | |
| 280 | u16 pppoe_id; |
| 281 | u16 src_mac_lo; |
| 282 | + |
| 283 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 284 | + u16 minfo; |
| 285 | + u16 winfo; |
| 286 | +#endif |
| 287 | }; |
| 288 | |
| 289 | /* software-only entry type */ |
| 290 | @@ -200,7 +205,11 @@ struct mtk_foe_entry { |
| 291 | struct mtk_foe_ipv4_dslite dslite; |
| 292 | struct mtk_foe_ipv6 ipv6; |
| 293 | struct mtk_foe_ipv6_6rd ipv6_6rd; |
| 294 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 295 | + u32 data[23]; |
| 296 | +#else |
| 297 | u32 data[19]; |
| 298 | +#endif |
| 299 | }; |
| 300 | }; |
| 301 | |
| 302 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 303 | index d4a012608..5a4201447 100644 |
| 304 | --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 305 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 306 | @@ -192,7 +192,15 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, |
| 307 | if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) { |
| 308 | mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss, |
| 309 | info.wcid); |
| 310 | pse_port = PSE_PPE0_PORT; |
| 311 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 312 | + if (info.wdma_idx == 0) |
| 313 | + pse_port = PSE_WDMA0_PORT; |
| 314 | + else if (info.wdma_idx == 1) |
| 315 | + pse_port = PSE_WDMA1_PORT; |
| 316 | + else |
| 317 | + return -EOPNOTSUPP; |
| 318 | +#endif |
| 319 | *wed_index = info.wdma_idx; |
| 320 | goto out; |
| 321 | } |
| 322 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h |
| 323 | index 0c45ea090..d319f1861 100644 |
| 324 | --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h |
| 325 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h |
| 326 | @@ -21,6 +21,9 @@ |
| 327 | #define MTK_PPE_GLO_CFG_BUSY BIT(31) |
| 328 | |
| 329 | #define MTK_PPE_FLOW_CFG 0x204 |
| 330 | +#define MTK_PPE_MD_TOAP_BYP_CRSN0 BIT(1) |
| 331 | +#define MTK_PPE_MD_TOAP_BYP_CRSN1 BIT(2) |
| 332 | +#define MTK_PPE_MD_TOAP_BYP_CRSN2 BIT(3) |
| 333 | #define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG BIT(6) |
| 334 | #define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG BIT(7) |
| 335 | #define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE BIT(8) |
| 336 | @@ -35,6 +38,8 @@ |
| 337 | #define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL BIT(18) |
| 338 | #define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY BIT(19) |
| 339 | #define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY BIT(20) |
| 340 | +#define MTK_PPE_FLOW_CFG_IPV4_MAPE_EN BIT(21) |
| 341 | +#define MTK_PPE_FLOW_CFG_IPV4_MAPT_EN BIT(22) |
| 342 | |
| 343 | #define MTK_PPE_IP_PROTO_CHK 0x208 |
| 344 | #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0) |
| 345 | @@ -54,6 +59,7 @@ |
| 346 | #define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14) |
| 347 | #define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16) |
| 348 | #define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18) |
| 349 | +#define MTK_PPE_TB_CFG_INFO_SEL BIT(20) |
| 350 | |
| 351 | enum { |
| 352 | MTK_PPE_SCAN_MODE_DISABLED, |
| 353 | @@ -111,6 +117,8 @@ enum { |
| 354 | |
| 355 | #define MTK_PPE_DEFAULT_CPU_PORT 0x248 |
| 356 | #define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4)) |
| 357 | +#define MTK_PPE_DEFAULT_CPU_PORT1 0x24C |
| 358 | +#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4)) |
| 359 | |
| 360 | #define MTK_PPE_MTU_DROP 0x308 |
| 361 | |
| 362 | @@ -141,4 +149,6 @@ enum { |
| 363 | #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) |
| 364 | #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2) |
| 365 | |
| 366 | +#define MTK_PPE_SBW_CTRL 0x374 |
| 367 | + |
| 368 | #endif |
| 369 | -- |
| 370 | 2.18.0 |
| 371 | |