developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1 | From f392188951839efae7807b6287a62c78d1ed0088 Mon Sep 17 00:00:00 2001 |
| 2 | From: Sam Shih <sam.shih@mediatek.com> |
| 3 | Date: Fri, 2 Jun 2023 13:06:17 +0800 |
| 4 | Subject: [PATCH] |
| 5 | [spi-and-storage][999-2340-drivers-mtd-spi-nor-Add-calibration-support-for-spi-nor.patch] |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame] | 6 | |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame] | 7 | --- |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 8 | drivers/mtd/spi-nor/spi-nor.c | 40 +++++++++++++++++++++++++++++++++++ |
| 9 | 1 file changed, 40 insertions(+) |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame] | 10 | |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 11 | diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c |
| 12 | index 8d2bc03cd..198b57a92 100644 |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame] | 13 | --- a/drivers/mtd/spi-nor/spi-nor.c |
| 14 | +++ b/drivers/mtd/spi-nor/spi-nor.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 15 | @@ -4899,6 +4899,35 @@ static void spi_nor_debugfs_init(struct spi_nor *nor, |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame] | 16 | info->id_len, info->id); |
| 17 | } |
| 18 | |
| 19 | +static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) |
| 20 | +{ |
| 21 | + int ret; |
| 22 | + struct spi_nor *nor = (struct spi_nor *)priv; |
| 23 | + |
| 24 | + nor->reg_proto = SNOR_PROTO_1_1_1; |
| 25 | + nor->read_proto = SNOR_PROTO_1_1_1; |
| 26 | + nor->read_opcode = SPINOR_OP_READ; |
| 27 | + nor->addr_width = 3; |
| 28 | + nor->read_dummy = 0; |
| 29 | + |
| 30 | + return spi_nor_read_raw(nor, *addr, readlen, buf); |
| 31 | +} |
| 32 | + |
developer | 2460ee7 | 2023-02-07 18:16:20 +0800 | [diff] [blame] | 33 | +static int spi_nor_cal_read_4B(void *priv, u32 *addr, int addrlen, u8 *buf, |
| 34 | + int readlen) |
| 35 | +{ |
| 36 | + int ret; |
| 37 | + struct spi_nor *nor = (struct spi_nor *)priv; |
| 38 | + |
| 39 | + nor->reg_proto = SNOR_PROTO_1_1_1; |
| 40 | + nor->read_proto = SNOR_PROTO_1_1_1; |
| 41 | + nor->read_opcode = SPINOR_OP_READ_4B; |
| 42 | + nor->addr_width = 4; |
| 43 | + nor->read_dummy = 0; |
| 44 | + |
| 45 | + return spi_nor_read_raw(nor, *addr, readlen, buf); |
| 46 | +} |
| 47 | + |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame] | 48 | static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, |
| 49 | const char *name) |
| 50 | { |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 51 | @@ -4973,6 +5002,17 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame] | 52 | if (!nor->bouncebuf) |
| 53 | return -ENOMEM; |
| 54 | |
developer | 2460ee7 | 2023-02-07 18:16:20 +0800 | [diff] [blame] | 55 | + if(nor->spimem) { |
| 56 | + ret = spi_mem_do_calibration(nor->spimem, |
| 57 | + spi_nor_cal_read, nor); |
| 58 | + if (ret) { |
| 59 | + ret = spi_mem_do_calibration(nor->spimem, |
| 60 | + spi_nor_cal_read_4B, nor); |
| 61 | + if (ret) |
| 62 | + return ret; |
| 63 | + } |
| 64 | + } |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame] | 65 | + |
| 66 | info = spi_nor_get_flash_info(nor, name); |
| 67 | if (IS_ERR(info)) |
| 68 | return PTR_ERR(info); |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 69 | -- |
| 70 | 2.34.1 |
| 71 | |