developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 1 | From c1d0d0a15d4cdafa1ed0a61606fd5fefa85a6bb7 Mon Sep 17 00:00:00 2001 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 2 | From: Howard Hsu <howard-yh.hsu@mediatek.com> |
| 3 | Date: Tue, 20 Dec 2022 09:47:31 +0800 |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 4 | Subject: [PATCH 15/22] wifi: mt76: mt7996: support more options in |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 5 | .set_bitrate_mask() |
| 6 | |
| 7 | With this patch, driver can support runtime configuration for single |
| 8 | rate, (HE)GI and HE_Ltf through .set_bitrate_mask(). Please noted that |
| 9 | currently we do not support to fix any single parameter for EHT mode. |
| 10 | --- |
| 11 | mt7996/mcu.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++++++- |
| 12 | 1 file changed, 137 insertions(+), 2 deletions(-) |
| 13 | |
| 14 | diff --git a/mt7996/mcu.c b/mt7996/mcu.c |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 15 | index cd86209b..8a7487ba 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 16 | --- a/mt7996/mcu.c |
| 17 | +++ b/mt7996/mcu.c |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 18 | @@ -1610,6 +1610,136 @@ int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 19 | MCU_WM_UNI_CMD(RA), true); |
| 20 | } |
| 21 | |
| 22 | +static int |
| 23 | +mt7996_mcu_set_part_fixed_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, |
| 24 | + struct ieee80211_sta *sta, void *data, u32 field) |
| 25 | +{ |
| 26 | + struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; |
| 27 | + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; |
| 28 | + struct sta_phy *phy = data; |
| 29 | + struct sta_rec_ra_fixed *ra; |
| 30 | + struct sk_buff *skb; |
| 31 | + struct tlv *tlv; |
| 32 | + |
| 33 | + skb = __mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, |
| 34 | + &msta->wcid, |
| 35 | + MT7996_STA_UPDATE_MAX_SIZE); |
| 36 | + |
| 37 | + if (IS_ERR(skb)) |
| 38 | + return PTR_ERR(skb); |
| 39 | + |
| 40 | + tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_RA_UPDATE, sizeof(*ra)); |
| 41 | + ra = (struct sta_rec_ra_fixed*)tlv; |
| 42 | + |
| 43 | + switch (field) { |
| 44 | + case RATE_PARAM_AUTO: |
| 45 | + break; |
| 46 | + case RATE_PARAM_FIXED: |
| 47 | + case RATE_PARAM_FIXED_MCS: |
| 48 | + case RATE_PARAM_FIXED_GI: |
| 49 | + case RATE_PARAM_FIXED_HE_LTF: |
| 50 | + if (phy) |
| 51 | + ra->phy = *phy; |
| 52 | + break; |
| 53 | + default: |
| 54 | + break; |
| 55 | + } |
| 56 | + ra->field = cpu_to_le32(field); |
| 57 | + |
| 58 | + return mt76_mcu_skb_send_msg(&dev->mt76, skb, |
| 59 | + MCU_WMWA_UNI_CMD(STA_REC_UPDATE), true); |
| 60 | +} |
| 61 | + |
| 62 | + |
| 63 | +static int |
| 64 | +mt7996_mcu_add_rate_ctrl_fixed(struct mt7996_dev *dev, struct ieee80211_vif *vif, |
| 65 | + struct ieee80211_sta *sta) |
| 66 | +{ |
| 67 | + struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; |
| 68 | + struct cfg80211_chan_def *chandef = &mvif->phy->mt76->chandef; |
| 69 | + struct cfg80211_bitrate_mask *mask = &mvif->bitrate_mask; |
| 70 | + enum nl80211_band band = chandef->chan->band; |
| 71 | + struct sta_phy phy = {}; |
| 72 | + int ret, nrates = 0; |
| 73 | + |
| 74 | +#define __sta_phy_bitrate_mask_check(_mcs, _gi, _ht, _he) \ |
| 75 | + do { \ |
| 76 | + u8 i, gi = mask->control[band]._gi; \ |
| 77 | + gi = (_he) ? gi : gi == NL80211_TXRATE_FORCE_SGI; \ |
| 78 | + for (i = 0; i <= sta->deflink.bandwidth; i++) { \ |
| 79 | + phy.sgi |= gi << (i << (_he)); \ |
| 80 | + phy.he_ltf |= mask->control[band].he_ltf << (i << (_he));\ |
| 81 | + } \ |
| 82 | + for (i = 0; i < ARRAY_SIZE(mask->control[band]._mcs); i++) { \ |
| 83 | + if (!mask->control[band]._mcs[i]) \ |
| 84 | + continue; \ |
| 85 | + nrates += hweight16(mask->control[band]._mcs[i]); \ |
| 86 | + phy.mcs = ffs(mask->control[band]._mcs[i]) - 1; \ |
| 87 | + if (_ht) \ |
| 88 | + phy.mcs += 8 * i; \ |
| 89 | + } \ |
| 90 | + } while (0) |
| 91 | + |
| 92 | + if (sta->deflink.he_cap.has_he) { |
| 93 | + __sta_phy_bitrate_mask_check(he_mcs, he_gi, 0, 1); |
| 94 | + } else if (sta->deflink.vht_cap.vht_supported) { |
| 95 | + __sta_phy_bitrate_mask_check(vht_mcs, gi, 0, 0); |
| 96 | + } else if (sta->deflink.ht_cap.ht_supported) { |
| 97 | + __sta_phy_bitrate_mask_check(ht_mcs, gi, 1, 0); |
| 98 | + } else { |
| 99 | + nrates = hweight32(mask->control[band].legacy); |
| 100 | + phy.mcs = ffs(mask->control[band].legacy) - 1; |
| 101 | + } |
| 102 | +#undef __sta_phy_bitrate_mask_check |
| 103 | + |
| 104 | + /* fall back to auto rate control */ |
| 105 | + if (mask->control[band].gi == NL80211_TXRATE_DEFAULT_GI && |
| 106 | + mask->control[band].he_gi == GENMASK(7, 0) && |
| 107 | + mask->control[band].he_ltf == GENMASK(7, 0) && |
| 108 | + nrates != 1) |
| 109 | + return 0; |
| 110 | + |
| 111 | + /* fixed single rate */ |
| 112 | + if (nrates == 1) { |
| 113 | + ret = mt7996_mcu_set_part_fixed_rate_ctrl(dev, vif, sta, &phy, |
| 114 | + RATE_PARAM_FIXED_MCS); |
| 115 | + if (ret) |
| 116 | + return ret; |
| 117 | + } |
| 118 | + |
| 119 | + /* fixed GI */ |
| 120 | + if (mask->control[band].gi != NL80211_TXRATE_DEFAULT_GI || |
| 121 | + mask->control[band].he_gi != GENMASK(7, 0)) { |
| 122 | + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; |
| 123 | + u32 addr; |
| 124 | + |
| 125 | + /* firmware updates only TXCMD but doesn't take WTBL into |
| 126 | + * account, so driver should update here to reflect the |
| 127 | + * actual txrate hardware sends out. |
| 128 | + */ |
| 129 | + addr = mt7996_mac_wtbl_lmac_addr(dev, msta->wcid.idx, 7); |
| 130 | + if (sta->deflink.he_cap.has_he) |
| 131 | + mt76_rmw_field(dev, addr, GENMASK(31, 24), phy.sgi); |
| 132 | + else |
| 133 | + mt76_rmw_field(dev, addr, GENMASK(15, 12), phy.sgi); |
| 134 | + |
| 135 | + ret = mt7996_mcu_set_part_fixed_rate_ctrl(dev, vif, sta, &phy, |
| 136 | + RATE_PARAM_FIXED_GI); |
| 137 | + if (ret) |
| 138 | + return ret; |
| 139 | + } |
| 140 | + |
| 141 | + /* fixed HE_LTF */ |
| 142 | + if (mask->control[band].he_ltf != GENMASK(7, 0)) { |
| 143 | + ret = mt7996_mcu_set_part_fixed_rate_ctrl(dev, vif, sta, &phy, |
| 144 | + RATE_PARAM_FIXED_HE_LTF); |
| 145 | + if (ret) |
| 146 | + return ret; |
| 147 | + } |
| 148 | + |
| 149 | + return 0; |
| 150 | +} |
| 151 | + |
| 152 | static void |
| 153 | mt7996_mcu_sta_rate_ctrl_tlv(struct sk_buff *skb, struct mt7996_dev *dev, |
| 154 | struct ieee80211_vif *vif, struct ieee80211_sta *sta) |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 155 | @@ -1719,6 +1849,7 @@ int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 156 | struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; |
| 157 | struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; |
| 158 | struct sk_buff *skb; |
| 159 | + int ret; |
| 160 | |
| 161 | skb = __mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, |
| 162 | &msta->wcid, |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 163 | @@ -1738,8 +1869,12 @@ int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 164 | */ |
| 165 | mt7996_mcu_sta_rate_ctrl_tlv(skb, dev, vif, sta); |
| 166 | |
| 167 | - return mt76_mcu_skb_send_msg(&dev->mt76, skb, |
| 168 | - MCU_WMWA_UNI_CMD(STA_REC_UPDATE), true); |
| 169 | + ret = mt76_mcu_skb_send_msg(&dev->mt76, skb, |
| 170 | + MCU_WMWA_UNI_CMD(STA_REC_UPDATE), true); |
| 171 | + if (ret) |
| 172 | + return ret; |
| 173 | + |
| 174 | + return mt7996_mcu_add_rate_ctrl_fixed(dev, vif, sta); |
| 175 | } |
| 176 | |
| 177 | static int |
| 178 | -- |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 179 | 2.39.2 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 180 | |