developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1 | From 5abef195abf3faa6f8e22a2e6996316f14c4f21c Mon Sep 17 00:00:00 2001 |
| 2 | From: Sam Shih <sam.shih@mediatek.com> |
| 3 | Date: Fri, 2 Jun 2023 13:06:13 +0800 |
| 4 | Subject: [PATCH] |
| 5 | [spi-and-storage][999-2324-mtd-spinand-micron-Use-more-specific-names.patch] |
developer | 41370d5 | 2022-03-16 16:01:59 +0800 | [diff] [blame] | 6 | |
developer | 41370d5 | 2022-03-16 16:01:59 +0800 | [diff] [blame] | 7 | --- |
| 8 | drivers/mtd/nand/spi/micron.c | 60 +++++++++++++++++------------------ |
| 9 | 1 file changed, 30 insertions(+), 30 deletions(-) |
| 10 | |
| 11 | diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 12 | index 5d370cfcd..afe3ba37d 100644 |
developer | 41370d5 | 2022-03-16 16:01:59 +0800 | [diff] [blame] | 13 | --- a/drivers/mtd/nand/spi/micron.c |
| 14 | +++ b/drivers/mtd/nand/spi/micron.c |
| 15 | @@ -28,7 +28,7 @@ |
| 16 | |
| 17 | #define MICRON_SELECT_DIE(x) ((x) << 6) |
| 18 | |
| 19 | -static SPINAND_OP_VARIANTS(read_cache_variants, |
| 20 | +static SPINAND_OP_VARIANTS(quadio_read_cache_variants, |
| 21 | SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
| 22 | SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| 23 | SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
| 24 | @@ -36,11 +36,11 @@ static SPINAND_OP_VARIANTS(read_cache_variants, |
| 25 | SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| 26 | SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| 27 | |
| 28 | -static SPINAND_OP_VARIANTS(write_cache_variants, |
| 29 | +static SPINAND_OP_VARIANTS(x4_write_cache_variants, |
| 30 | SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
| 31 | SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| 32 | |
| 33 | -static SPINAND_OP_VARIANTS(update_cache_variants, |
| 34 | +static SPINAND_OP_VARIANTS(x4_update_cache_variants, |
| 35 | SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), |
| 36 | SPINAND_PROG_LOAD(false, 0, NULL, 0)); |
| 37 | |
| 38 | @@ -120,9 +120,9 @@ static const struct spinand_info micron_spinand_table[] = { |
| 39 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), |
| 40 | NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), |
| 41 | NAND_ECCREQ(8, 512), |
| 42 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 43 | - &write_cache_variants, |
| 44 | - &update_cache_variants), |
| 45 | + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| 46 | + &x4_write_cache_variants, |
| 47 | + &x4_update_cache_variants), |
| 48 | 0, |
| 49 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 50 | micron_8_ecc_get_status)), |
| 51 | @@ -131,9 +131,9 @@ static const struct spinand_info micron_spinand_table[] = { |
| 52 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25), |
| 53 | NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), |
| 54 | NAND_ECCREQ(8, 512), |
| 55 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 56 | - &write_cache_variants, |
| 57 | - &update_cache_variants), |
| 58 | + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| 59 | + &x4_write_cache_variants, |
| 60 | + &x4_update_cache_variants), |
| 61 | 0, |
| 62 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 63 | micron_8_ecc_get_status)), |
| 64 | @@ -142,9 +142,9 @@ static const struct spinand_info micron_spinand_table[] = { |
| 65 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), |
| 66 | NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| 67 | NAND_ECCREQ(8, 512), |
| 68 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 69 | - &write_cache_variants, |
| 70 | - &update_cache_variants), |
| 71 | + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| 72 | + &x4_write_cache_variants, |
| 73 | + &x4_update_cache_variants), |
| 74 | 0, |
| 75 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 76 | micron_8_ecc_get_status)), |
| 77 | @@ -153,9 +153,9 @@ static const struct spinand_info micron_spinand_table[] = { |
| 78 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), |
| 79 | NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| 80 | NAND_ECCREQ(8, 512), |
| 81 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 82 | - &write_cache_variants, |
| 83 | - &update_cache_variants), |
| 84 | + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| 85 | + &x4_write_cache_variants, |
| 86 | + &x4_update_cache_variants), |
| 87 | 0, |
| 88 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 89 | micron_8_ecc_get_status)), |
| 90 | @@ -164,9 +164,9 @@ static const struct spinand_info micron_spinand_table[] = { |
| 91 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36), |
| 92 | NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2), |
| 93 | NAND_ECCREQ(8, 512), |
| 94 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 95 | - &write_cache_variants, |
| 96 | - &update_cache_variants), |
| 97 | + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| 98 | + &x4_write_cache_variants, |
| 99 | + &x4_update_cache_variants), |
| 100 | 0, |
| 101 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 102 | micron_8_ecc_get_status), |
| 103 | @@ -176,9 +176,9 @@ static const struct spinand_info micron_spinand_table[] = { |
| 104 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), |
| 105 | NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| 106 | NAND_ECCREQ(8, 512), |
| 107 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 108 | - &write_cache_variants, |
| 109 | - &update_cache_variants), |
| 110 | + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| 111 | + &x4_write_cache_variants, |
| 112 | + &x4_update_cache_variants), |
| 113 | SPINAND_HAS_CR_FEAT_BIT, |
| 114 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 115 | micron_8_ecc_get_status)), |
| 116 | @@ -187,9 +187,9 @@ static const struct spinand_info micron_spinand_table[] = { |
| 117 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), |
| 118 | NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| 119 | NAND_ECCREQ(8, 512), |
| 120 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 121 | - &write_cache_variants, |
| 122 | - &update_cache_variants), |
| 123 | + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| 124 | + &x4_write_cache_variants, |
| 125 | + &x4_update_cache_variants), |
| 126 | SPINAND_HAS_CR_FEAT_BIT, |
| 127 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 128 | micron_8_ecc_get_status)), |
| 129 | @@ -198,9 +198,9 @@ static const struct spinand_info micron_spinand_table[] = { |
| 130 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46), |
| 131 | NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), |
| 132 | NAND_ECCREQ(8, 512), |
| 133 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 134 | - &write_cache_variants, |
| 135 | - &update_cache_variants), |
| 136 | + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| 137 | + &x4_write_cache_variants, |
| 138 | + &x4_update_cache_variants), |
| 139 | SPINAND_HAS_CR_FEAT_BIT, |
| 140 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 141 | micron_8_ecc_get_status), |
| 142 | @@ -210,9 +210,9 @@ static const struct spinand_info micron_spinand_table[] = { |
| 143 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47), |
| 144 | NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), |
| 145 | NAND_ECCREQ(8, 512), |
| 146 | - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 147 | - &write_cache_variants, |
| 148 | - &update_cache_variants), |
| 149 | + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| 150 | + &x4_write_cache_variants, |
| 151 | + &x4_update_cache_variants), |
| 152 | SPINAND_HAS_CR_FEAT_BIT, |
| 153 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 154 | micron_8_ecc_get_status), |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 155 | -- |
| 156 | 2.34.1 |
| 157 | |