blob: 21d5dc844da6b1044aaf79a0fb69327864ecf1ec [file] [log] [blame]
developer1b76b3f2021-12-22 19:53:19 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-spim-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986b gsw RFB";
7 compatible = "mediatek,mt7986a-2500wan-gsw-spim-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 gsw: gsw@0 {
14 compatible = "mediatek,mt753x";
15 mediatek,ethsys = <&ethsys>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 };
19
20 memory {
21 reg = <0 0x40000000 0 0x10000000>;
22 };
23
24 sound {
25 compatible = "mediatek,mt7986-wm8960-machine";
26 mediatek,platform = <&afe>;
27 audio-routing = "Headphone", "HP_L",
28 "Headphone", "HP_R",
29 "LINPUT1", "AMIC",
30 "RINPUT1", "AMIC";
31 mediatek,audio-codec = <&wm8960>;
32 status = "okay";
33 };
34};
35
36&pwm {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
39 status = "okay";
40};
41
42&uart0 {
43 status = "okay";
44};
45
46&uart1 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&uart1_pins>;
49 status = "okay";
50};
51
52&uart2 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&uart2_pins>;
55 status = "okay";
56};
57
58&i2c0 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c_pins>;
61 status = "okay";
62
63 wm8960: wm8960@1a {
64 compatible = "wlf,wm8960";
65 reg = <0x1a>;
66 };
67};
68
69&auxadc {
70 status = "okay";
71};
72
73&watchdog {
74 status = "okay";
75};
76
77&eth {
78 status = "okay";
79
80 gmac0: mac@0 {
81 compatible = "mediatek,eth-mac";
82 reg = <0>;
83 phy-mode = "2500base-x";
84
85 fixed-link {
86 speed = <2500>;
87 full-duplex;
88 pause;
89 };
90 };
91
92 gmac1: mac@1 {
93 compatible = "mediatek,eth-mac";
94 reg = <1>;
95 phy-mode = "2500base-x";
96
97 fixed-link {
98 speed = <2500>;
99 full-duplex;
100 pause;
101 };
102 };
103
104 mdio: mdio-bus {
105 #address-cells = <1>;
106 #size-cells = <0>;
107
108 phy5: phy@5 {
109 compatible = "ethernet-phy-id67c9.de0a";
110 reg = <5>;
111 reset-gpios = <&pio 6 1>;
112 reset-deassert-us = <20000>;
113 phy-mode = "2500base-x";
114 };
115
116 phy6: phy@6 {
117 compatible = "ethernet-phy-id67c9.de0a";
118 reg = <6>;
119 phy-mode = "2500base-x";
120 };
121
122 };
123};
124
125&gsw {
126 mediatek,mdio = <&mdio>;
127 mediatek,portmap = "lllll";
128 mediatek,mdio_master_pinmux = <1>;
129 reset-gpios = <&pio 5 0>;
130 interrupt-parent = <&pio>;
131 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
132 status = "okay";
133
134 port5: port@5 {
135 compatible = "mediatek,mt753x-port";
136 reg = <5>;
137 phy-mode = "sgmii";
138
139 fixed-link {
140 speed = <2500>;
141 full-duplex;
142 };
143
144 };
145
146 port6: port@6 {
147 compatible = "mediatek,mt753x-port";
148 mediatek,ssc-on;
149 reg = <6>;
150 phy-mode = "sgmii";
151 fixed-link {
152 speed = <2500>;
153 full-duplex;
154 };
155 };
156};
157
158&hnat {
159 mtketh-wan = "eth1";
160 mtketh-lan = "lan";
161 mtketh-max-gmac = <2>;
162 status = "okay";
163};
164
165&spi0 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&spi_flash_pins>;
168 cs-gpios = <0>, <0>;
169 status = "okay";
170
171 spi_nor@0 {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 compatible = "jedec,spi-nor";
175 reg = <0>;
176 spi-max-frequency = <20000000>;
177 spi-tx-buswidth = <4>;
178 spi-rx-buswidth = <4>;
179 };
180
181 spi_nand: spi_nand@1 {
182 #address-cells = <1>;
183 #size-cells = <1>;
184 compatible = "spi-nand";
185 reg = <1>;
186 spi-max-frequency = <20000000>;
187 spi-tx-buswidth = <4>;
188 spi-rx-buswidth = <4>;
189 };
190};
191
192&spi1 {
193 pinctrl-names = "default";
194 pinctrl-0 = <&spic_pins_g2>;
195 status = "okay";
196};
197
198&pcie0 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pcie0_pins>;
201 status = "okay";
202};
203
204&wbsys {
205 mediatek,mtd-eeprom = <&factory 0x0000>;
206 status = "okay";
207};
208
209&pio {
210 spi_flash_pins: spi-flash-pins-33-to-38 {
211 mux {
212 function = "flash";
213 groups = "spi0", "spi0_wp_hold";
214 };
215 conf-pu {
216 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
217 drive-strength = <MTK_DRIVE_8mA>;
218 mediatek,pull-up-adv = <0>; /* bias-disable */
219 };
220 conf-pd {
221 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
222 drive-strength = <MTK_DRIVE_8mA>;
223 mediatek,pull-down-adv = <0>; /* bias-disable */
224 };
225 };
226};