developer | 7e2761e | 2023-10-12 08:11:13 +0800 | [diff] [blame] | 1 | From ab77df3cc660c0aa0f46060499d8704dc389a2a6 Mon Sep 17 00:00:00 2001 |
| 2 | From: StanleyYP Wang <StanleyYP.Wang@mediatek.com> |
| 3 | Date: Mon, 24 Jul 2023 16:39:22 +0800 |
| 4 | Subject: [PATCH 63/98] wifi: mt76: mt7996: add wtbl_info support for kite |
| 5 | |
| 6 | Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> |
| 7 | --- |
| 8 | mt7996/mtk_debug.h | 22 +++++++++++++ |
| 9 | mt7996/mtk_debugfs.c | 74 ++++++++++++++++++++++++++++++++++++++++++-- |
| 10 | 2 files changed, 93 insertions(+), 3 deletions(-) |
| 11 | |
| 12 | diff --git a/mt7996/mtk_debug.h b/mt7996/mtk_debug.h |
| 13 | index 9718c2c..1611345 100644 |
| 14 | --- a/mt7996/mtk_debug.h |
| 15 | +++ b/mt7996/mtk_debug.h |
| 16 | @@ -1088,6 +1088,17 @@ enum cipher_suit { |
| 17 | #define WF_LWTBL_AAD_OM_MASK \ |
| 18 | 0x00008000 // 15-15 |
| 19 | #define WF_LWTBL_AAD_OM_SHIFT 15 |
| 20 | +/* kite DW2 field bit 13-14 */ |
| 21 | +#define WF_LWTBL_DUAL_PTEC_EN_DW 2 |
| 22 | +#define WF_LWTBL_DUAL_PTEC_EN_ADDR 8 |
| 23 | +#define WF_LWTBL_DUAL_PTEC_EN_MASK \ |
| 24 | + 0x00002000 // 13-13 |
| 25 | +#define WF_LWTBL_DUAL_PTEC_EN_SHIFT 13 |
| 26 | +#define WF_LWTBL_DUAL_CTS_CAP_DW 2 |
| 27 | +#define WF_LWTBL_DUAL_CTS_CAP_ADDR 8 |
| 28 | +#define WF_LWTBL_DUAL_CTS_CAP_MASK \ |
| 29 | + 0x00004000 // 14-14 |
| 30 | +#define WF_LWTBL_DUAL_CTS_CAP_SHIFT 14 |
| 31 | #define WF_LWTBL_CIPHER_SUIT_PGTK_DW 2 |
| 32 | #define WF_LWTBL_CIPHER_SUIT_PGTK_ADDR 8 |
| 33 | #define WF_LWTBL_CIPHER_SUIT_PGTK_MASK \ |
| 34 | @@ -1305,6 +1316,8 @@ enum cipher_suit { |
| 35 | #define WF_LWTBL_AF_ADDR 20 |
| 36 | #define WF_LWTBL_AF_MASK \ |
| 37 | 0x00000007 // 2- 0 |
| 38 | +#define WF_LWTBL_AF_MASK_7992 \ |
| 39 | + 0x0000000f // 3- 0 |
| 40 | #define WF_LWTBL_AF_SHIFT 0 |
| 41 | #define WF_LWTBL_AF_HE_DW 5 |
| 42 | #define WF_LWTBL_AF_HE_ADDR 20 |
| 43 | @@ -1565,16 +1578,25 @@ enum cipher_suit { |
| 44 | #define WF_LWTBL_PRITX_SW_MODE_MASK \ |
| 45 | 0x00008000 // 15-15 |
| 46 | #define WF_LWTBL_PRITX_SW_MODE_SHIFT 15 |
| 47 | +#define WF_LWTBL_PRITX_SW_MODE_MASK_7992 \ |
| 48 | + 0x00004000 // 14-14 |
| 49 | +#define WF_LWTBL_PRITX_SW_MODE_SHIFT_7992 14 |
| 50 | #define WF_LWTBL_PRITX_ERSU_DW 9 |
| 51 | #define WF_LWTBL_PRITX_ERSU_ADDR 36 |
| 52 | #define WF_LWTBL_PRITX_ERSU_MASK \ |
| 53 | 0x00010000 // 16-16 |
| 54 | #define WF_LWTBL_PRITX_ERSU_SHIFT 16 |
| 55 | +#define WF_LWTBL_PRITX_ERSU_MASK_7992 \ |
| 56 | + 0x00008000 // 15-15 |
| 57 | +#define WF_LWTBL_PRITX_ERSU_SHIFT_7992 15 |
| 58 | #define WF_LWTBL_PRITX_PLR_DW 9 |
| 59 | #define WF_LWTBL_PRITX_PLR_ADDR 36 |
| 60 | #define WF_LWTBL_PRITX_PLR_MASK \ |
| 61 | 0x00020000 // 17-17 |
| 62 | #define WF_LWTBL_PRITX_PLR_SHIFT 17 |
| 63 | +#define WF_LWTBL_PRITX_PLR_MASK_7992 \ |
| 64 | + 0x00030000 // 17-16 |
| 65 | +#define WF_LWTBL_PRITX_PLR_SHIFT_7992 16 |
| 66 | #define WF_LWTBL_PRITX_DCM_DW 9 |
| 67 | #define WF_LWTBL_PRITX_DCM_ADDR 36 |
| 68 | #define WF_LWTBL_PRITX_DCM_MASK \ |
| 69 | diff --git a/mt7996/mtk_debugfs.c b/mt7996/mtk_debugfs.c |
| 70 | index f56ad88..ce48664 100644 |
| 71 | --- a/mt7996/mtk_debugfs.c |
| 72 | +++ b/mt7996/mtk_debugfs.c |
| 73 | @@ -1011,7 +1011,8 @@ static void parse_fmac_lwtbl_dw0_1(struct seq_file *s, u8 *lwtbl) |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | -static const struct berse_wtbl_parse WTBL_LMAC_DW2[] = { |
| 78 | +static const struct berse_wtbl_parse *WTBL_LMAC_DW2; |
| 79 | +static const struct berse_wtbl_parse WTBL_LMAC_DW2_7996[] = { |
| 80 | {"AID", WF_LWTBL_AID_MASK, WF_LWTBL_AID_SHIFT, false}, |
| 81 | {"GID_SU", WF_LWTBL_GID_SU_MASK, NO_SHIFT_DEFINE, false}, |
| 82 | {"SPP_EN", WF_LWTBL_SPP_EN_MASK, NO_SHIFT_DEFINE, false}, |
| 83 | @@ -1032,6 +1033,26 @@ static const struct berse_wtbl_parse WTBL_LMAC_DW2[] = { |
| 84 | {NULL,} |
| 85 | }; |
| 86 | |
| 87 | +static const struct berse_wtbl_parse WTBL_LMAC_DW2_7992[] = { |
| 88 | + {"AID", WF_LWTBL_AID_MASK, WF_LWTBL_AID_SHIFT, false}, |
| 89 | + {"GID_SU", WF_LWTBL_GID_SU_MASK, NO_SHIFT_DEFINE, false}, |
| 90 | + {"DUAL_PTEC_EN", WF_LWTBL_DUAL_PTEC_EN_MASK, NO_SHIFT_DEFINE, false}, |
| 91 | + {"DUAL_CTS_CAP", WF_LWTBL_DUAL_CTS_CAP_MASK, NO_SHIFT_DEFINE, false}, |
| 92 | + {"CIPHER_PGTK",WF_LWTBL_CIPHER_SUIT_PGTK_MASK, WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT, true}, |
| 93 | + {"FROM_DS", WF_LWTBL_FD_MASK, NO_SHIFT_DEFINE, false}, |
| 94 | + {"TO_DS", WF_LWTBL_TD_MASK, NO_SHIFT_DEFINE, false}, |
| 95 | + {"SW", WF_LWTBL_SW_MASK, NO_SHIFT_DEFINE, false}, |
| 96 | + {"UL", WF_LWTBL_UL_MASK, NO_SHIFT_DEFINE, false}, |
| 97 | + {"TX_POWER_SAVE", WF_LWTBL_TX_PS_MASK, NO_SHIFT_DEFINE, true}, |
| 98 | + {"QOS", WF_LWTBL_QOS_MASK, NO_SHIFT_DEFINE, false}, |
| 99 | + {"HT", WF_LWTBL_HT_MASK, NO_SHIFT_DEFINE, false}, |
| 100 | + {"VHT", WF_LWTBL_VHT_MASK, NO_SHIFT_DEFINE, false}, |
| 101 | + {"HE", WF_LWTBL_HE_MASK, NO_SHIFT_DEFINE, false}, |
| 102 | + {"EHT", WF_LWTBL_EHT_MASK, NO_SHIFT_DEFINE, false}, |
| 103 | + {"MESH", WF_LWTBL_MESH_MASK, NO_SHIFT_DEFINE, true}, |
| 104 | + {NULL,} |
| 105 | +}; |
| 106 | + |
| 107 | static void parse_fmac_lwtbl_dw2(struct seq_file *s, u8 *lwtbl) |
| 108 | { |
| 109 | u32 *addr = 0; |
| 110 | @@ -1141,7 +1162,8 @@ static void parse_fmac_lwtbl_dw4(struct seq_file *s, u8 *lwtbl) |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | -static const struct berse_wtbl_parse WTBL_LMAC_DW5[] = { |
| 115 | +static const struct berse_wtbl_parse *WTBL_LMAC_DW5; |
| 116 | +static const struct berse_wtbl_parse WTBL_LMAC_DW5_7996[] = { |
| 117 | {"AF", WF_LWTBL_AF_MASK, WF_LWTBL_AF_SHIFT, false}, |
| 118 | {"AF_HE", WF_LWTBL_AF_HE_MASK, WF_LWTBL_AF_HE_SHIFT,false}, |
| 119 | {"RTS", WF_LWTBL_RTS_MASK, NO_SHIFT_DEFINE, false}, |
| 120 | @@ -1163,6 +1185,27 @@ static const struct berse_wtbl_parse WTBL_LMAC_DW5[] = { |
| 121 | {NULL,} |
| 122 | }; |
| 123 | |
| 124 | +static const struct berse_wtbl_parse WTBL_LMAC_DW5_7992[] = { |
| 125 | + {"AF", WF_LWTBL_AF_MASK_7992, WF_LWTBL_AF_SHIFT, false}, |
| 126 | + {"RTS", WF_LWTBL_RTS_MASK, NO_SHIFT_DEFINE, false}, |
| 127 | + {"SMPS", WF_LWTBL_SMPS_MASK, NO_SHIFT_DEFINE, false}, |
| 128 | + {"DYN_BW", WF_LWTBL_DYN_BW_MASK, NO_SHIFT_DEFINE, true}, |
| 129 | + {"MMSS", WF_LWTBL_MMSS_MASK, WF_LWTBL_MMSS_SHIFT,false}, |
| 130 | + {"USR", WF_LWTBL_USR_MASK, NO_SHIFT_DEFINE, false}, |
| 131 | + {"SR_RATE", WF_LWTBL_SR_R_MASK, WF_LWTBL_SR_R_SHIFT,false}, |
| 132 | + {"SR_ABORT", WF_LWTBL_SR_ABORT_MASK, NO_SHIFT_DEFINE, true}, |
| 133 | + {"TX_POWER_OFFSET", WF_LWTBL_TX_POWER_OFFSET_MASK, WF_LWTBL_TX_POWER_OFFSET_SHIFT, false}, |
| 134 | + {"LTF_EHT", WF_LWTBL_LTF_EHT_MASK, WF_LWTBL_LTF_EHT_SHIFT, false}, |
| 135 | + {"GI_EHT", WF_LWTBL_GI_EHT_MASK, WF_LWTBL_GI_EHT_SHIFT, false}, |
| 136 | + {"DOPPL", WF_LWTBL_DOPPL_MASK, NO_SHIFT_DEFINE, false}, |
| 137 | + {"TXOP_PS_CAP", WF_LWTBL_TXOP_PS_CAP_MASK, NO_SHIFT_DEFINE, false}, |
| 138 | + {"DONOT_UPDATE_I_PSM", WF_LWTBL_DU_I_PSM_MASK, NO_SHIFT_DEFINE, true}, |
| 139 | + {"I_PSM", WF_LWTBL_I_PSM_MASK, NO_SHIFT_DEFINE, false}, |
| 140 | + {"PSM", WF_LWTBL_PSM_MASK, NO_SHIFT_DEFINE, false}, |
| 141 | + {"SKIP_TX", WF_LWTBL_SKIP_TX_MASK, NO_SHIFT_DEFINE, true}, |
| 142 | + {NULL,} |
| 143 | +}; |
| 144 | + |
| 145 | static void parse_fmac_lwtbl_dw5(struct seq_file *s, u8 *lwtbl) |
| 146 | { |
| 147 | u32 *addr = 0; |
| 148 | @@ -1281,7 +1324,8 @@ static void parse_fmac_lwtbl_dw8(struct seq_file *s, u8 *lwtbl) |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | -static const struct berse_wtbl_parse WTBL_LMAC_DW9[] = { |
| 153 | +static const struct berse_wtbl_parse *WTBL_LMAC_DW9; |
| 154 | +static const struct berse_wtbl_parse WTBL_LMAC_DW9_7996[] = { |
| 155 | {"RX_AVG_MPDU_SIZE", WF_LWTBL_RX_AVG_MPDU_SIZE_MASK, WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT, false}, |
| 156 | {"PRITX_SW_MODE", WF_LWTBL_PRITX_SW_MODE_MASK, NO_SHIFT_DEFINE, false}, |
| 157 | {"PRITX_ERSU", WF_LWTBL_PRITX_ERSU_MASK, NO_SHIFT_DEFINE, false}, |
| 158 | @@ -1295,6 +1339,20 @@ static const struct berse_wtbl_parse WTBL_LMAC_DW9[] = { |
| 159 | {NULL,} |
| 160 | }; |
| 161 | |
| 162 | +static const struct berse_wtbl_parse WTBL_LMAC_DW9_7992[] = { |
| 163 | + {"RX_AVG_MPDU_SIZE", WF_LWTBL_RX_AVG_MPDU_SIZE_MASK, WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT, false}, |
| 164 | + {"PRITX_SW_MODE", WF_LWTBL_PRITX_SW_MODE_MASK_7992, NO_SHIFT_DEFINE, false}, |
| 165 | + {"PRITX_ERSU", WF_LWTBL_PRITX_ERSU_MASK_7992, NO_SHIFT_DEFINE, false}, |
| 166 | + {"PRITX_PLR", WF_LWTBL_PRITX_PLR_MASK_7992, NO_SHIFT_DEFINE, true}, |
| 167 | + {"PRITX_DCM", WF_LWTBL_PRITX_DCM_MASK, NO_SHIFT_DEFINE, false}, |
| 168 | + {"PRITX_ER106T", WF_LWTBL_PRITX_ER106T_MASK, NO_SHIFT_DEFINE, true}, |
| 169 | + /* {"FCAP(0:20 1:~40)", WTBL_FCAP_20_TO_160_MHZ, WTBL_FCAP_20_TO_160_MHZ_OFFSET}, */ |
| 170 | + {"MPDU_FAIL_CNT", WF_LWTBL_MPDU_FAIL_CNT_MASK, WF_LWTBL_MPDU_FAIL_CNT_SHIFT, false}, |
| 171 | + {"MPDU_OK_CNT", WF_LWTBL_MPDU_OK_CNT_MASK, WF_LWTBL_MPDU_OK_CNT_SHIFT, false}, |
| 172 | + {"RATE_IDX", WF_LWTBL_RATE_IDX_MASK, WF_LWTBL_RATE_IDX_SHIFT, true}, |
| 173 | + {NULL,} |
| 174 | +}; |
| 175 | + |
| 176 | char *fcap_name[] = {"20MHz", "20/40MHz", "20/40/80MHz", "20/40/80/160/80+80MHz", "20/40/80/160/80+80/320MHz"}; |
| 177 | |
| 178 | static void parse_fmac_lwtbl_dw9(struct seq_file *s, u8 *lwtbl) |
| 179 | @@ -2670,6 +2728,16 @@ int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir) |
| 180 | { |
| 181 | struct mt7996_dev *dev = phy->dev; |
| 182 | |
| 183 | + if (is_mt7996(&dev->mt76)) { |
| 184 | + WTBL_LMAC_DW2 = WTBL_LMAC_DW2_7996; |
| 185 | + WTBL_LMAC_DW5 = WTBL_LMAC_DW5_7996; |
| 186 | + WTBL_LMAC_DW9 = WTBL_LMAC_DW9_7996; |
| 187 | + } else { |
| 188 | + WTBL_LMAC_DW2 = WTBL_LMAC_DW2_7992; |
| 189 | + WTBL_LMAC_DW5 = WTBL_LMAC_DW5_7992; |
| 190 | + WTBL_LMAC_DW9 = WTBL_LMAC_DW9_7992; |
| 191 | + } |
| 192 | + |
| 193 | mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0); |
| 194 | |
| 195 | /* agg */ |
| 196 | -- |
| 197 | 2.18.0 |
| 198 | |