developer | e5e687d | 2023-08-08 16:05:33 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * Copyright (c) 2023 MediaTek Inc. All Rights Reserved. |
| 4 | * |
| 5 | * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _TOPS_TDMA_H_ |
| 9 | #define _TOPS_TDMA_H_ |
| 10 | |
| 11 | #include <linux/bitops.h> |
| 12 | #include <linux/bitfield.h> |
| 13 | |
| 14 | /* TDMA */ |
| 15 | #define TDMA_BASE (0x6000) |
| 16 | |
| 17 | #define TDMA_TX_CTX_IDX_0 (0x008) |
| 18 | #define TDMA_RX_MAX_CNT_X(idx) (0x104 + ((idx) * 0x10)) |
| 19 | #define TDMA_RX_CRX_IDX_X(idx) (0x108 + ((idx) * 0x10)) |
| 20 | #define TDMA_RX_DRX_IDX_X(idx) (0x10C + ((idx) * 0x10)) |
| 21 | #define TDMA_GLO_CFG0 (0x204) |
| 22 | #define TDMA_RST_IDX (0x208) |
| 23 | #define TDMA_TX_XDMA_FIFO_CFG0 (0x238) |
| 24 | #define TDMA_RX_XDMA_FIFO_CFG0 (0x23C) |
| 25 | #define TDMA_PREF_TX_CFG (0x2D0) |
| 26 | #define TDMA_PREF_TX_FIFO_CFG0 (0x2D4) |
| 27 | #define TDMA_PREF_RX_CFG (0x2DC) |
| 28 | #define TDMA_PREF_RX_FIFO_CFG0 (0x2E0) |
| 29 | #define TDMA_PREF_SIDX_CFG (0x2E4) |
| 30 | #define TDMA_WRBK_TX_CFG (0x300) |
| 31 | #define TDMA_WRBK_TX_FIFO_CFG0 (0x304) |
| 32 | #define TDMA_WRBK_RX_CFG (0x344) |
| 33 | #define TDMA_WRBK_RX_FIFO_CFGX(x) (0x348 + 0x4 * (x)) |
| 34 | #define TDMA_WRBK_SIDX_CFG (0x388) |
| 35 | #define TDMA_PREF_RX_FIFO_CFG1 (0x3EC) |
| 36 | |
| 37 | /* TDMA_GLO_CFG0 */ |
| 38 | #define TX_DMA_EN (BIT(0)) |
| 39 | #define TX_DMA_BUSY (BIT(1)) |
| 40 | #define RX_DMA_EN (BIT(2)) |
| 41 | #define RX_DMA_BUSY (BIT(3)) |
| 42 | #define DMA_BT_SIZE_MASK (0x7) |
| 43 | #define DMA_BT_SIZE_SHIFT (11) |
| 44 | #define OTSD_THRES_MASK (0xF) |
| 45 | #define OTSD_THRES_SHIFT (14) |
| 46 | #define CDM_FCNT_THRES_MASK (0xF) |
| 47 | #define CDM_FCNT_THRES_SHIFT (18) |
| 48 | #define LB_MODE (BIT(24)) |
| 49 | #define PKT_WCOMP (BIT(27)) |
| 50 | #define DEC_WCOMP (BIT(28)) |
| 51 | |
| 52 | /* TDMA_RST_IDX */ |
| 53 | #define RST_DTX_IDX_0 (BIT(0)) |
| 54 | #define RST_DRX_IDX_X(idx) (BIT(16 + (idx))) |
| 55 | |
| 56 | /* TDMA_TX_XDMA_FIFO_CFG0 TDMA_RX_XDMA_FIFO_CFG0 */ |
| 57 | #define PAR_FIFO_CLEAR (BIT(0)) |
| 58 | #define CMD_FIFO_CLEAR (BIT(4)) |
| 59 | #define DMAD_FIFO_CLEAR (BIT(8)) |
| 60 | #define ARR_FIFO_CLEAR (BIT(12)) |
| 61 | #define LEN_FIFO_CLEAR (BIT(15)) |
| 62 | #define WID_FIFO_CLEAR (BIT(18)) |
| 63 | #define BID_FIFO_CLEAR (BIT(21)) |
| 64 | |
| 65 | /* TDMA_SDL_CFG */ |
| 66 | #define SDL_EN (BIT(16)) |
| 67 | #define SDL_MASK (0xFFFF) |
| 68 | #define SDL_SHIFT (0) |
| 69 | |
| 70 | /* TDMA_PREF_TX_CFG TDMA_PREF_RX_CFG */ |
| 71 | #define PREF_BUSY BIT(1) |
| 72 | #define PREF_EN BIT(0) |
| 73 | |
| 74 | /* TDMA_PREF_TX_FIFO_CFG0 TDMA_PREF_RX_FIFO_CFG0 TDMA_PREF_RX_FIFO_CFG1 */ |
| 75 | #define PREF_TX_RING0_CLEAR (BIT(0)) |
| 76 | #define PREF_RX_RINGX_CLEAR(x) (BIT((((x) % 2) * 16))) |
| 77 | #define PREF_RX_RING1_CLEAR (BIT(0)) |
| 78 | #define PREF_RX_RING2_CLEAR (BIT(16)) |
| 79 | #define PREF_RX_RING3_CLEAR (BIT(0)) |
| 80 | #define PREF_RX_RING4_CLEAR (BIT(16)) |
| 81 | |
| 82 | /* TDMA_PREF_SIDX_CFG TDMA_WRBK_SIDX_CFG */ |
| 83 | #define TX_RING0_SIDX_CLR (BIT(0)) |
| 84 | #define RX_RINGX_SIDX_CLR(x) (BIT(4 + (x))) |
| 85 | |
| 86 | /* TDMA_WRBK_TX_FIFO_CFG0 TDMA_WRBK_RX_FIFO_CFGX */ |
| 87 | #define WRBK_RING_CLEAR (BIT(0)) |
| 88 | |
| 89 | /* TDMA_WRBK_TX_CFG TDMA_WRBK_RX_CFG */ |
| 90 | #define WRBK_BUSY (BIT(0)) |
| 91 | #define BURST_SIZE_SHIFT (6) |
| 92 | #define BURST_SIZE_MASK (0x1F) |
| 93 | #define WRBK_THRES_SHIFT (14) |
| 94 | #define WRBK_THRES_MASK (0x3F) |
| 95 | #define FLUSH_TIMER_EN (BIT(21)) |
| 96 | #define MAX_PENDING_TIME_SHIFT (22) |
| 97 | #define MAX_PENDING_TIME_MASK (0xFF) |
| 98 | #define WRBK_EN (BIT(30)) |
| 99 | |
| 100 | #define TDMA_RING_NUM (4) |
| 101 | #define TDMA_RING_NUM_MOD (TDMA_RING_NUM - 1) |
| 102 | |
| 103 | enum tops_net_cmd { |
| 104 | TOPS_NET_CMD_NULL, |
| 105 | TOPS_NET_CMD_STOP, |
| 106 | TOPS_NET_CMD_START, |
| 107 | |
| 108 | __TOPS_NET_CMD_MAX, |
| 109 | }; |
| 110 | |
| 111 | void mtk_tops_tdma_record_last_state(void); |
| 112 | void mtk_tops_tdma_reset(void); |
| 113 | int mtk_tops_tdma_enable(void); |
| 114 | void mtk_tops_tdma_disable(void); |
| 115 | int mtk_tops_tdma_init(struct platform_device *pdev); |
| 116 | void mtk_tops_tdma_deinit(struct platform_device *pdev); |
| 117 | #endif /* _TOPS_TDMA_H_ */ |