developer | e5e687d | 2023-08-08 16:05:33 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * Copyright (c) 2023 MediaTek Inc. All Rights Reserved. |
| 4 | * |
| 5 | * Author: Ren-Ting Wang <ren-ting.wang@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _TOPS_MCU_H_ |
| 9 | #define _TOPS_MCU_H_ |
| 10 | |
| 11 | #include <linux/clk.h> |
| 12 | #include <linux/bits.h> |
| 13 | #include <linux/list.h> |
| 14 | #include <linux/wait.h> |
| 15 | #include <linux/timer.h> |
| 16 | #include <linux/device.h> |
| 17 | #include <linux/spinlock.h> |
| 18 | #include <linux/workqueue.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | |
| 21 | #include "tops.h" |
| 22 | |
| 23 | struct mcu_state; |
| 24 | |
| 25 | #define TOP_CORE_BASE (0x001000) |
| 26 | #define TOP_SEC_BASE (0x00A000) |
| 27 | #define TOP_L2SRAM (0x100000) |
| 28 | #define TOP_CORE_M_DTCM (0x300000) |
| 29 | #define TOP_CORE_M_ITCM (0x310000) |
| 30 | #define CLUST_CORE_BASE(x) (0x501000 + 0x1000 * (x)) |
| 31 | #define CLUST_SEC_BASE (0x50A000) |
| 32 | #define CLUST_L2SRAM (0x700000) |
| 33 | #define CLUST_CORE_X_DTCM(x) (0x800000 + 0x20000 * (x)) |
| 34 | #define CLUST_CORE_X_ITCM(x) (0x810000 + 0x20000 * (x)) |
| 35 | |
| 36 | /* CORE */ |
| 37 | #define TOP_CORE_NPU_SW_RST (TOP_CORE_BASE + 0x00) |
| 38 | #define TOP_CORE_NPU_CTRL (TOP_CORE_BASE + 0x04) |
| 39 | #define TOP_CORE_OCD_CTRL (TOP_CORE_BASE + 0x18) |
| 40 | |
| 41 | #define TOP_CORE_DBG_CTRL (TOP_SEC_BASE + 0x64) |
| 42 | #define TOP_CORE_M_STAT_VECTOR_SEL (TOP_SEC_BASE + 0x68) |
| 43 | #define TOP_CORE_M_RESET_VECTOR (TOP_SEC_BASE + 0x6C) |
| 44 | |
| 45 | #define CLUST_CORE_NPU_SW_RST(x) (CLUST_CORE_BASE(x) + 0x00) |
| 46 | #define CLUST_CORE_NPU_CTRL(x) (CLUST_CORE_BASE(x) + 0x04) |
| 47 | #define CLUST_CORE_OCD_CTRL(x) (CLUST_CORE_BASE(x) + 0x18) |
| 48 | |
| 49 | #define CLUST_CORE_DBG_CTRL (CLUST_SEC_BASE + 0x64) |
| 50 | #define CLUST_CORE_X_STAT_VECTOR_SEL(x) (CLUST_SEC_BASE + 0x68 + (0xC * (x))) |
| 51 | #define CLUST_CORE_X_RESET_VECTOR(x) (CLUST_SEC_BASE + 0x6C + (0xC * (x))) |
| 52 | |
| 53 | #define MCU_ACT_ABNORMAL (BIT(MCU_ACT_ABNORMAL_BIT)) |
| 54 | #define MCU_ACT_RESET (BIT(MCU_ACT_RESET_BIT)) |
| 55 | #define MCU_ACT_NETSTOP (BIT(MCU_ACT_NETSTOP_BIT)) |
| 56 | #define MCU_ACT_SHUTDOWN (BIT(MCU_ACT_SHUTDOWN_BIT)) |
| 57 | #define MCU_ACT_INIT (BIT(MCU_ACT_INIT_BIT)) |
| 58 | #define MCU_ACT_STALL (BIT(MCU_ACT_STALL_BIT)) |
| 59 | #define MCU_ACT_FREERUN (BIT(MCU_ACT_FREERUN_BIT)) |
| 60 | |
| 61 | #define MCU_CTRL_ARG_NUM 2 |
| 62 | |
| 63 | enum mcu_act { |
| 64 | MCU_ACT_ABNORMAL_BIT, |
| 65 | MCU_ACT_RESET_BIT, |
| 66 | MCU_ACT_NETSTOP_BIT, |
| 67 | MCU_ACT_SHUTDOWN_BIT, |
| 68 | MCU_ACT_INIT_BIT, |
| 69 | MCU_ACT_STALL_BIT, |
| 70 | MCU_ACT_FREERUN_BIT, |
| 71 | |
| 72 | __MCU_ACT_MAX, |
| 73 | }; |
| 74 | |
| 75 | enum mcu_state_type { |
| 76 | MCU_STATE_TYPE_SHUTDOWN, |
| 77 | MCU_STATE_TYPE_INIT, |
| 78 | MCU_STATE_TYPE_FREERUN, |
| 79 | MCU_STATE_TYPE_STALL, |
| 80 | MCU_STATE_TYPE_NETSTOP, |
| 81 | MCU_STATE_TYPE_RESET, |
| 82 | MCU_STATE_TYPE_ABNORMAL, |
| 83 | |
| 84 | __MCU_STATE_TYPE_MAX, |
| 85 | }; |
| 86 | |
| 87 | enum mcu_cmd_type { |
| 88 | MCU_CMD_TYPE_NULL, |
| 89 | MCU_CMD_TYPE_INIT_DONE, |
| 90 | MCU_CMD_TYPE_STALL, |
| 91 | MCU_CMD_TYPE_STALL_DONE, |
| 92 | MCU_CMD_TYPE_FREERUN, |
| 93 | MCU_CMD_TYPE_FREERUN_DONE, |
| 94 | MCU_CMD_TYPE_ASSERT_RESET, |
| 95 | MCU_CMD_TYPE_ASSERT_RESET_DONE, |
| 96 | MCU_CMD_TYPE_RELEASE_RESET, |
| 97 | MCU_CMD_TYPE_RELEASE_RESET_DONE, |
| 98 | |
| 99 | __MCU_CMD_TYPE_MAX, |
| 100 | }; |
| 101 | |
| 102 | enum mcu_event_type { |
| 103 | MCU_EVENT_TYPE_NULL, |
| 104 | MCU_EVENT_TYPE_SYNC_TNL, |
| 105 | MCU_EVENT_TYPE_WDT_TIMEOUT, |
| 106 | MCU_EVENT_TYPE_FE_RESET, |
| 107 | |
| 108 | __MCU_EVENT_TYPE_MAX, |
| 109 | }; |
| 110 | |
| 111 | struct mcu_ctrl_cmd { |
| 112 | enum mcu_event_type e; |
| 113 | u32 arg[MCU_CTRL_ARG_NUM]; |
| 114 | /* |
| 115 | * if bit n (BIT(enum core_id)) == 1, send control message to that core. |
| 116 | * default send to all cores if core_mask == 0 |
| 117 | */ |
| 118 | u32 core_mask; |
| 119 | }; |
| 120 | |
| 121 | struct mcu_state { |
| 122 | enum mcu_state_type state; |
| 123 | struct mcu_state *(*state_trans)(u32 mcu_act, struct mcu_state *state); |
| 124 | int (*enter)(struct mcu_state *state); |
| 125 | int (*leave)(struct mcu_state *state); |
| 126 | }; |
| 127 | |
| 128 | bool mtk_tops_mcu_alive(void); |
| 129 | bool mtk_tops_mcu_bring_up_done(void); |
| 130 | bool mtk_tops_mcu_netsys_fe_rst(void); |
| 131 | int mtk_tops_mcu_stall(struct mcu_ctrl_cmd *mcmd, |
| 132 | void (*callback)(void *param), void *param); |
| 133 | int mtk_tops_mcu_reset(struct mcu_ctrl_cmd *mcmd, |
| 134 | void (*callback)(void *param), void *param); |
| 135 | |
| 136 | int mtk_tops_mcu_bring_up(struct platform_device *pdev); |
| 137 | void mtk_tops_mcu_tear_down(struct platform_device *pdev); |
| 138 | int mtk_tops_mcu_init(struct platform_device *pdev); |
| 139 | void mtk_tops_mcu_deinit(struct platform_device *pdev); |
| 140 | #endif /* _TOPS_MCU_H_ */ |