blob: 822aaad1c514d493f86ba80ced2ad9e2caff6799 [file] [log] [blame]
developer1d1e4562022-03-17 00:06:34 +08001From 0b8c7d725830b5873c648777ab7813fff9d5951f Mon Sep 17 00:00:00 2001
developer20d67712022-03-02 14:09:32 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Mon, 3 Jan 2022 17:09:53 +0800
developer1d1e4562022-03-17 00:06:34 +08004Subject: [PATCH 3/6] mt76: mt7915: rework rx testmode stats
developer20d67712022-03-02 14:09:32 +08005
6---
developer1d1e4562022-03-17 00:06:34 +08007 mac80211.c | 3 +-
8 mt76.h | 5 +++
9 mt76_connac_mcu.h | 1 +
10 mt7915/mcu.h | 1 +
11 mt7915/testmode.c | 82 ++++++++++++++++++++++++++++++++++++++---------
12 mt7915/testmode.h | 28 ++++++++++++++++
13 testmode.c | 3 ++
14 testmode.h | 3 ++
developer20d67712022-03-02 14:09:32 +080015 8 files changed, 109 insertions(+), 17 deletions(-)
16
17diff --git a/mac80211.c b/mac80211.c
developer1d1e4562022-03-17 00:06:34 +080018index 5b53d008..5a4ac5de 100644
developer20d67712022-03-02 14:09:32 +080019--- a/mac80211.c
20+++ b/mac80211.c
21@@ -737,7 +737,8 @@ void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb)
22 }
23
24 #ifdef CONFIG_NL80211_TESTMODE
25- if (phy->test.state == MT76_TM_STATE_RX_FRAMES) {
26+ if (!(phy->test.flag & MT_TM_FW_RX_COUNT) &&
27+ phy->test.state == MT76_TM_STATE_RX_FRAMES) {
28 phy->test.rx_stats.packets[q]++;
29 if (status->flag & RX_FLAG_FAILED_FCS_CRC)
30 phy->test.rx_stats.fcs_error[q]++;
31diff --git a/mt76.h b/mt76.h
developer1d1e4562022-03-17 00:06:34 +080032index 81078be3..d5f8650f 100644
developer20d67712022-03-02 14:09:32 +080033--- a/mt76.h
34+++ b/mt76.h
35@@ -583,6 +583,8 @@ struct mt76_testmode_ops {
36 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
37 };
38
39+#define MT_TM_FW_RX_COUNT BIT(0)
40+
41 struct mt76_testmode_data {
42 enum mt76_testmode_state state;
43
44@@ -614,6 +616,8 @@ struct mt76_testmode_data {
45
46 u8 addr[3][ETH_ALEN];
47
48+ u8 flag;
49+
50 u32 tx_pending;
51 u32 tx_queued;
52 u16 tx_queued_limit;
53@@ -621,6 +625,7 @@ struct mt76_testmode_data {
54 struct {
55 u64 packets[__MT_RXQ_MAX];
56 u64 fcs_error[__MT_RXQ_MAX];
57+ u64 len_mismatch;
58 } rx_stats;
59 };
60
61diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developer1d1e4562022-03-17 00:06:34 +080062index c3c93338..54419864 100644
developer20d67712022-03-02 14:09:32 +080063--- a/mt76_connac_mcu.h
64+++ b/mt76_connac_mcu.h
65@@ -980,6 +980,7 @@ enum {
66 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
67 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
68 MCU_EXT_CMD_MURU_CTRL = 0x9f,
69+ MCU_EXT_CMD_RX_STAT = 0xa4,
70 MCU_EXT_CMD_SET_SPR = 0xa8,
71 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
72 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
73diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer1d1e4562022-03-17 00:06:34 +080074index 960072a4..52368dc3 100644
developer20d67712022-03-02 14:09:32 +080075--- a/mt7915/mcu.h
76+++ b/mt7915/mcu.h
77@@ -28,6 +28,7 @@ struct mt7915_mcu_txd {
78 enum {
79 MCU_ATE_SET_TRX = 0x1,
80 MCU_ATE_SET_FREQ_OFFSET = 0xa,
81+ MCU_ATE_SET_PHY_COUNT = 0x11,
82 MCU_ATE_SET_SLOT_TIME = 0x13,
83 MCU_ATE_CLEAN_TXQUEUE = 0x1c,
84 };
85diff --git a/mt7915/testmode.c b/mt7915/testmode.c
developer1d1e4562022-03-17 00:06:34 +080086index d6f71436..e8bf616c 100644
developer20d67712022-03-02 14:09:32 +080087--- a/mt7915/testmode.c
88+++ b/mt7915/testmode.c
89@@ -133,6 +133,21 @@ mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid)
90 sizeof(req), false);
91 }
92
93+static int
94+mt7915_tm_set_phy_count(struct mt7915_phy *phy, u8 control)
95+{
96+ struct mt7915_dev *dev = phy->dev;
97+ struct mt7915_tm_cmd req = {
98+ .testmode_en = 1,
99+ .param_idx = MCU_ATE_SET_PHY_COUNT,
100+ .param.cfg.enable = control,
101+ .param.cfg.band = phy != &dev->phy,
102+ };
103+
104+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
105+ sizeof(req), false);
106+}
107+
108 static int
109 mt7915_tm_set_slot_time(struct mt7915_phy *phy, u8 slot_time, u8 sifs)
110 {
developer1d1e4562022-03-17 00:06:34 +0800111@@ -438,6 +453,8 @@ mt7915_tm_init(struct mt7915_phy *phy, bool en)
developer20d67712022-03-02 14:09:32 +0800112 mt7915_mcu_add_bss_info(phy, phy->monitor_vif, en);
113 mt7915_mcu_add_sta(dev, phy->monitor_vif, NULL, en);
114
115+ phy->mt76->test.flag |= MT_TM_FW_RX_COUNT;
116+
117 if (!en)
118 mt7915_tm_set_tam_arb(phy, en, 0);
119 }
developer1d1e4562022-03-17 00:06:34 +0800120@@ -503,18 +520,63 @@ mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
developer20d67712022-03-02 14:09:32 +0800121 mt7915_tm_set_trx(phy, TM_MAC_TX, en);
122 }
123
124+static int
125+mt7915_tm_get_rx_stats(struct mt7915_phy *phy, bool clear)
126+{
127+#define CMD_RX_STAT_BAND 0x3
128+ struct mt76_testmode_data *td = &phy->mt76->test;
129+ struct mt7915_tm_rx_stat_band *rs_band;
130+ struct mt7915_dev *dev = phy->dev;
131+ struct sk_buff *skb;
132+ struct {
133+ u8 format_id;
134+ u8 band;
135+ u8 _rsv[2];
136+ } __packed req = {
137+ .format_id = CMD_RX_STAT_BAND,
138+ .band = phy != &dev->phy,
139+ };
140+ int ret;
141+
142+ ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_EXT_CMD(RX_STAT),
143+ &req, sizeof(req), true, &skb);
144+ if (ret)
145+ return ret;
146+
147+ rs_band = (struct mt7915_tm_rx_stat_band *)skb->data;
148+ /* pr_info("mdrdy_cnt = %d\n", le32_to_cpu(rs_band->mdrdy_cnt)); */
149+ /* pr_info("fcs_err = %d\n", le16_to_cpu(rs_band->fcs_err)); */
150+ /* pr_info("len_mismatch = %d\n", le16_to_cpu(rs_band->len_mismatch)); */
151+ /* pr_info("fcs_ok = %d\n", le16_to_cpu(rs_band->fcs_succ)); */
152+
153+ if (!clear) {
154+ enum mt76_rxq_id q = req.band ? MT_RXQ_EXT : MT_RXQ_MAIN;
155+
156+ td->rx_stats.packets[q] += le32_to_cpu(rs_band->mdrdy_cnt);
157+ td->rx_stats.fcs_error[q] += le16_to_cpu(rs_band->fcs_err);
158+ td->rx_stats.len_mismatch += le16_to_cpu(rs_band->len_mismatch);
159+ }
160+
161+ dev_kfree_skb(skb);
162+
163+ return 0;
164+}
165+
166 static void
167 mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
168 {
169 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
170
171 if (en) {
172- struct mt7915_dev *dev = phy->dev;
173-
174 mt7915_tm_update_channel(phy);
175
176 /* read-clear */
177- mt76_rr(dev, MT_MIB_SDR3(phy != &dev->phy));
178+ mt7915_tm_get_rx_stats(phy, true);
179+
180+ /* clear fw count */
181+ mt7915_tm_set_phy_count(phy, 0);
182+ mt7915_tm_set_phy_count(phy, 1);
183+
184 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
185 }
186 }
developer1d1e4562022-03-17 00:06:34 +0800187@@ -738,12 +800,8 @@ static int
developer20d67712022-03-02 14:09:32 +0800188 mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
189 {
190 struct mt7915_phy *phy = mphy->priv;
191- struct mt7915_dev *dev = phy->dev;
192- enum mt76_rxq_id q;
193 void *rx, *rssi;
194- u16 fcs_err;
195 int i;
196- u32 cnt;
197
198 rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX);
199 if (!rx)
developer1d1e4562022-03-17 00:06:34 +0800200@@ -787,15 +845,7 @@ mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
developer20d67712022-03-02 14:09:32 +0800201
202 nla_nest_end(msg, rx);
203
204- cnt = mt76_rr(dev, MT_MIB_SDR3(phy->band_idx));
205- fcs_err = is_mt7915(&dev->mt76) ? FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) :
206- FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt);
207-
208- q = phy->band_idx ? MT_RXQ_EXT : MT_RXQ_MAIN;
209- mphy->test.rx_stats.packets[q] += fcs_err;
210- mphy->test.rx_stats.fcs_error[q] += fcs_err;
211-
212- return 0;
213+ return mt7915_tm_get_rx_stats(phy, false);
214 }
215
216 const struct mt76_testmode_ops mt7915_testmode_ops = {
217diff --git a/mt7915/testmode.h b/mt7915/testmode.h
developer1d1e4562022-03-17 00:06:34 +0800218index 5573ac30..a1c54c89 100644
developer20d67712022-03-02 14:09:32 +0800219--- a/mt7915/testmode.h
220+++ b/mt7915/testmode.h
221@@ -33,6 +33,12 @@ struct mt7915_tm_clean_txq {
222 u8 rsv;
223 };
224
225+struct mt7915_tm_cfg {
226+ u8 enable;
227+ u8 band;
228+ u8 _rsv[2];
229+};
230+
231 struct mt7915_tm_cmd {
232 u8 testmode_en;
233 u8 param_idx;
234@@ -43,6 +49,7 @@ struct mt7915_tm_cmd {
235 struct mt7915_tm_freq_offset freq;
236 struct mt7915_tm_slot_time slot;
237 struct mt7915_tm_clean_txq clean;
238+ struct mt7915_tm_cfg cfg;
239 u8 test[72];
240 } param;
241 } __packed;
242@@ -102,4 +109,25 @@ enum {
243 TAM_ARB_OP_MODE_FORCE_SU = 5,
244 };
245
246+struct mt7915_tm_rx_stat_band {
247+ u8 category;
248+
249+ /* mac */
250+ __le16 fcs_err;
251+ __le16 len_mismatch;
252+ __le16 fcs_succ;
253+ __le32 mdrdy_cnt;
254+ /* phy */
255+ __le16 fcs_err_cck;
256+ __le16 fcs_err_ofdm;
257+ __le16 pd_cck;
258+ __le16 pd_ofdm;
259+ __le16 sig_err_cck;
260+ __le16 sfd_err_cck;
261+ __le16 sig_err_ofdm;
262+ __le16 tag_err_ofdm;
263+ __le16 mdrdy_cnt_cck;
264+ __le16 mdrdy_cnt_ofdm;
265+};
266+
267 #endif
268diff --git a/testmode.c b/testmode.c
developer1d1e4562022-03-17 00:06:34 +0800269index 7cd00794..e6d1f702 100644
developer20d67712022-03-02 14:09:32 +0800270--- a/testmode.c
271+++ b/testmode.c
272@@ -559,6 +559,9 @@ mt76_testmode_dump_stats(struct mt76_phy *phy, struct sk_buff *msg)
273 nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_PACKETS, rx_packets,
274 MT76_TM_STATS_ATTR_PAD) ||
275 nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_FCS_ERROR, rx_fcs_error,
276+ MT76_TM_STATS_ATTR_PAD) ||
277+ nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_LEN_MISMATCH,
278+ td->rx_stats.len_mismatch,
279 MT76_TM_STATS_ATTR_PAD))
280 return -EMSGSIZE;
281
282diff --git a/testmode.h b/testmode.h
developer1d1e4562022-03-17 00:06:34 +0800283index 5e2792d8..89613266 100644
developer20d67712022-03-02 14:09:32 +0800284--- a/testmode.h
285+++ b/testmode.h
286@@ -101,6 +101,8 @@ enum mt76_testmode_attr {
287 * @MT76_TM_STATS_ATTR_RX_FCS_ERROR: number of rx packets with FCS error (u64)
288 * @MT76_TM_STATS_ATTR_LAST_RX: information about the last received packet
289 * see &enum mt76_testmode_rx_attr
290+ * @MT76_TM_STATS_ATTR_RX_LEN_MISMATCH: number of rx packets with length
291+ * mismatch error (u64)
292 */
293 enum mt76_testmode_stats_attr {
294 MT76_TM_STATS_ATTR_UNSPEC,
295@@ -113,6 +115,7 @@ enum mt76_testmode_stats_attr {
296 MT76_TM_STATS_ATTR_RX_PACKETS,
297 MT76_TM_STATS_ATTR_RX_FCS_ERROR,
298 MT76_TM_STATS_ATTR_LAST_RX,
299+ MT76_TM_STATS_ATTR_RX_LEN_MISMATCH,
300
301 /* keep last */
302 NUM_MT76_TM_STATS_ATTRS,
303--
developer1d1e4562022-03-17 00:06:34 +08003042.18.0
developer20d67712022-03-02 14:09:32 +0800305