developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 1 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 2 | index 4075ec2..524c5d9 100644 |
| 3 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 4 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 5 | @@ -1796,17 +1796,17 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, |
| 6 | skb_checksum_none_assert(skb); |
| 7 | skb->protocol = eth_type_trans(skb, netdev); |
| 8 | |
| 9 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 10 | - hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2; |
| 11 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 12 | + hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2; |
| 13 | #else |
| 14 | - hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; |
| 15 | + hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; |
| 16 | #endif |
| 17 | if (hash != MTK_RXD4_FOE_ENTRY) { |
| 18 | hash = jhash_1word(hash, 0); |
| 19 | skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); |
| 20 | } |
| 21 | |
| 22 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 23 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 24 | reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON_V2, trxd.rxd5); |
| 25 | if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) { |
| 26 | for (i = 0; i < eth->ppe_num; i++) { |
| 27 | @@ -4626,11 +4626,15 @@ static const struct mtk_soc_data mt7988_data = { |
| 28 | .required_clks = MT7988_CLKS_BITMAP, |
| 29 | .required_pctl = false, |
| 30 | .has_sram = true, |
| 31 | + .has_accounting = true, |
| 32 | + .hash_way = 4, |
| 33 | + .offload_version = 2, |
| 34 | .txrx = { |
| 35 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
| 36 | .rxd_size = sizeof(struct mtk_rx_dma_v2), |
| 37 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
| 38 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2, |
| 39 | + .qdma_tx_sch = 4, |
| 40 | }, |
| 41 | }; |
| 42 | |
| 43 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 44 | index 5b39d87..94bd423 100644 |
| 45 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 46 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 47 | @@ -118,7 +118,7 @@ |
| 48 | #define MTK_GDMA_UCS_EN BIT(20) |
| 49 | #define MTK_GDMA_STRP_CRC BIT(16) |
| 50 | #define MTK_GDMA_TO_PDMA 0x0 |
| 51 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 52 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 53 | #define MTK_GDMA_TO_PPE0 0x3333 |
| 54 | #define MTK_GDMA_TO_PPE1 0x4444 |
| 55 | #else |
| 56 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 57 | index 98f61fe..bd504d4 100755 |
| 58 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 59 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 60 | @@ -211,7 +211,7 @@ int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto, |
| 61 | MTK_FOE_IB1_BIND_CACHE; |
| 62 | entry->ib1 = val; |
| 63 | |
| 64 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 65 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 66 | val = FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0xf) | |
| 67 | #else |
| 68 | val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) | |
| 69 | @@ -403,7 +403,7 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, |
| 70 | |
| 71 | *ib2 &= ~MTK_FOE_IB2_PORT_MG; |
| 72 | *ib2 |= MTK_FOE_IB2_WDMA_WINFO; |
| 73 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 74 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 75 | *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq); |
| 76 | |
| 77 | l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) | |
| 78 | @@ -867,13 +867,16 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
| 79 | mtk_ppe_init_foe_table(ppe); |
| 80 | ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys); |
| 81 | |
| 82 | - val = MTK_PPE_TB_CFG_ENTRY_80B | |
| 83 | + val = |
| 84 | +#if !defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 85 | + MTK_PPE_TB_CFG_ENTRY_80B | |
| 86 | +#endif |
| 87 | MTK_PPE_TB_CFG_AGE_NON_L4 | |
| 88 | MTK_PPE_TB_CFG_AGE_UNBIND | |
| 89 | MTK_PPE_TB_CFG_AGE_TCP | |
| 90 | MTK_PPE_TB_CFG_AGE_UDP | |
| 91 | MTK_PPE_TB_CFG_AGE_TCP_FIN | |
| 92 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 93 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 94 | MTK_PPE_TB_CFG_INFO_SEL | |
| 95 | #endif |
| 96 | FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS, |
| 97 | @@ -937,7 +940,7 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
| 98 | |
| 99 | ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0); |
| 100 | |
| 101 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 102 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 103 | ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); |
| 104 | ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); |
| 105 | #endif |
| 106 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 107 | index 703b2bd..03b4dfb 100644 |
| 108 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 109 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 110 | @@ -8,7 +8,7 @@ |
| 111 | #include <linux/bitfield.h> |
| 112 | #include <linux/rhashtable.h> |
| 113 | |
| 114 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 115 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 116 | #define MTK_MAX_PPE_NUM 2 |
| 117 | #define MTK_ETH_PPE_BASE 0x2000 |
| 118 | #else |
| 119 | @@ -22,7 +22,7 @@ |
| 120 | #define MTK_PPE_WAIT_TIMEOUT_US 1000000 |
| 121 | |
| 122 | #define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) |
| 123 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 124 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 125 | #define MTK_FOE_IB1_UNBIND_SRC_PORT GENMASK(11, 8) |
| 126 | #define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(19, 12) |
| 127 | #define MTK_FOE_IB1_UNBIND_PREBIND BIT(22) |
| 128 | @@ -70,7 +70,7 @@ enum { |
| 129 | MTK_PPE_PKT_TYPE_IPV6_6RD = 7, |
| 130 | }; |
| 131 | |
| 132 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 133 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 134 | #define MTK_FOE_IB2_QID GENMASK(6, 0) |
| 135 | #define MTK_FOE_IB2_PORT_MG BIT(7) |
| 136 | #define MTK_FOE_IB2_PSE_QOS BIT(8) |
| 137 | @@ -98,7 +98,18 @@ enum { |
| 138 | |
| 139 | #define MTK_FOE_IB2_DSCP GENMASK(31, 24) |
| 140 | |
| 141 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 142 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 143 | +#define MTK_FOE_WINFO_WCID GENMASK(15, 0) |
| 144 | +#define MTK_FOE_WINFO_BSS GENMASK(23, 16) |
| 145 | + |
| 146 | +#define MTK_FOE_WINFO_PAO_USR_INFO GENMASK(15, 0) |
| 147 | +#define MTK_FOE_WINFO_PAO_TID GENMASK(19, 16) |
| 148 | +#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20) |
| 149 | +#define MTK_FOE_WINFO_PAO_IS_PRIOR BIT(21) |
| 150 | +#define MTK_FOE_WINFO_PAO_IS_SP BIT(22) |
| 151 | +#define MTK_FOE_WINFO_PAO_HF BIT(23) |
| 152 | +#define MTK_FOE_WINFO_PAO_AMSDU_EN BIT(24) |
| 153 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 154 | #define MTK_FOE_WINFO_BSS GENMASK(5, 0) |
| 155 | #define MTK_FOE_WINFO_WCID GENMASK(15, 6) |
| 156 | #else |
| 157 | @@ -128,7 +139,12 @@ struct mtk_foe_mac_info { |
| 158 | u16 pppoe_id; |
| 159 | u16 src_mac_lo; |
| 160 | |
| 161 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 162 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 163 | + u16 minfo; |
| 164 | + u16 resv1; |
| 165 | + u32 winfo; |
| 166 | + u32 winfo_pao; |
| 167 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 168 | u16 minfo; |
| 169 | u16 winfo; |
| 170 | #endif |
| 171 | @@ -249,7 +265,9 @@ struct mtk_foe_entry { |
| 172 | struct mtk_foe_ipv4_dslite dslite; |
| 173 | struct mtk_foe_ipv6 ipv6; |
| 174 | struct mtk_foe_ipv6_6rd ipv6_6rd; |
| 175 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 176 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 177 | + u32 data[31]; |
| 178 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 179 | u32 data[23]; |
| 180 | #else |
| 181 | u32 data[19]; |
| 182 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 183 | index a5bf090..0e41ff2 100755 |
| 184 | --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 185 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 186 | @@ -195,7 +195,7 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, |
| 187 | mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss, |
| 188 | info.wcid); |
| 189 | pse_port = 3; |
| 190 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 191 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 192 | if (info.wdma_idx == 0) |
| 193 | pse_port = 8; |
| 194 | else if (info.wdma_idx == 1) |
| 195 | @@ -452,7 +452,7 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f) |
| 196 | return -ENOMEM; |
| 197 | |
| 198 | i = 0; |
| 199 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 200 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 201 | if (idev && idev->netdev_ops->ndo_fill_receive_path) { |
| 202 | ctx.dev = idev; |
| 203 | idev->netdev_ops->ndo_fill_receive_path(&ctx, &path); |