blob: 61b68af44c72a217b77648920fa6c2e54142a22f [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-spim-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986a RFB";
7 compatible = "mediatek,mt7986a-2500wan-spim-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 sound {
18 compatible = "mediatek,mt7986-wm8960-machine";
19 mediatek,platform = <&afe>;
20 audio-routing = "Headphone", "HP_L",
21 "Headphone", "HP_R",
22 "LINPUT1", "AMIC",
23 "RINPUT1", "AMIC";
24 mediatek,audio-codec = <&wm8960>;
25 status = "okay";
26 };
27};
28
developer209e52d2022-06-30 11:32:57 +080029&fan {
30 pwms = <&pwm 1 50000 0>;
31 status = "disabled";
32};
33
developer565bacb2021-09-28 21:26:32 +080034&pwm {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
37 status = "okay";
38};
39
40&uart0 {
41 status = "okay";
42};
43
44&uart1 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&uart1_pins>;
47 status = "okay";
48};
49
50&uart2 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&uart2_pins>;
developere0c42a12022-08-19 11:01:38 +080053 status = "okay";
developer565bacb2021-09-28 21:26:32 +080054};
55
56&i2c0 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&i2c_pins>;
59 status = "okay";
60
61 wm8960: wm8960@1a {
62 compatible = "wlf,wm8960";
63 reg = <0x1a>;
64 };
65};
66
67&auxadc {
68 status = "okay";
69};
70
71&watchdog {
72 status = "okay";
73};
74
75&eth {
76 status = "okay";
77
78 gmac0: mac@0 {
79 compatible = "mediatek,eth-mac";
80 reg = <0>;
81 phy-mode = "2500base-x";
developer283fc452022-08-18 19:50:33 +080082
83 fixed-link {
84 speed = <2500>;
85 full-duplex;
86 pause;
developer283fc452022-08-18 19:50:33 +080087 };
developer565bacb2021-09-28 21:26:32 +080088 };
89
90 gmac1: mac@1 {
91 compatible = "mediatek,eth-mac";
92 reg = <1>;
93 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080094 phy-handle = <&phy6>;
developer565bacb2021-09-28 21:26:32 +080095 };
96
97 mdio: mdio-bus {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
developerf0a1e452022-08-15 12:06:11 +0800101 reset-gpios = <&pio 6 1>;
102 reset-delay-us = <600>;
103
developer565bacb2021-09-28 21:26:32 +0800104 phy5: phy@5 {
developere0c42a12022-08-19 11:01:38 +0800105 compatible = "ethernet-phy-ieee802.3-c45";
developer565bacb2021-09-28 21:26:32 +0800106 reg = <5>;
developer565bacb2021-09-28 21:26:32 +0800107 };
108
109 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +0800110 compatible = "ethernet-phy-ieee802.3-c45";
developer565bacb2021-09-28 21:26:32 +0800111 reg = <6>;
developer565bacb2021-09-28 21:26:32 +0800112 };
113
114 switch@0 {
115 compatible = "mediatek,mt7531";
116 reg = <31>;
117 reset-gpios = <&pio 5 0>;
118
119 ports {
120 #address-cells = <1>;
121 #size-cells = <0>;
122
123 port@0 {
124 reg = <0>;
125 label = "lan0";
126 };
127
128 port@1 {
129 reg = <1>;
130 label = "lan1";
131 };
132
133 port@2 {
134 reg = <2>;
135 label = "lan2";
136 };
137
138 port@3 {
139 reg = <3>;
140 label = "lan3";
141 };
142
143 port@4 {
144 reg = <4>;
145 label = "lan4";
146 };
147
148 port@5 {
149 reg = <5>;
150 label = "lan5";
151 phy-mode = "2500base-x";
developere0c42a12022-08-19 11:01:38 +0800152 phy-handle = <&phy5>;
developer565bacb2021-09-28 21:26:32 +0800153 };
154
155 port@6 {
156 reg = <6>;
157 label = "cpu";
158 ethernet = <&gmac0>;
159 phy-mode = "2500base-x";
160
161 fixed-link {
162 speed = <2500>;
163 full-duplex;
164 pause;
165 };
166 };
167 };
168 };
169 };
170};
171
172&hnat {
173 mtketh-wan = "eth1";
174 mtketh-lan = "lan";
175 mtketh-max-gmac = <2>;
176 status = "okay";
177};
178
179&spi0 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&spi_flash_pins>;
182 cs-gpios = <0>, <0>;
183 status = "okay";
184
185 spi_nor@0 {
186 #address-cells = <1>;
187 #size-cells = <1>;
188 compatible = "jedec,spi-nor";
189 reg = <0>;
190 spi-max-frequency = <20000000>;
191 spi-tx-buswidth = <4>;
192 spi-rx-buswidth = <4>;
193 };
194
195 spi_nand: spi_nand@1 {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 compatible = "spi-nand";
199 reg = <1>;
200 spi-max-frequency = <20000000>;
201 spi-tx-buswidth = <4>;
202 spi-rx-buswidth = <4>;
203 };
204};
205
206&spi1 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&spic_pins_g2>;
209 status = "okay";
210};
211
212&pcie0 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&pcie0_pins>;
215 status = "okay";
216};
217
218&wbsys {
219 mediatek,mtd-eeprom = <&factory 0x0000>;
220 status = "okay";
developere138bcd2021-12-06 09:20:47 +0800221 pinctrl-names = "default", "dbdc";
222 pinctrl-0 = <&wf_2g_5g_pins>;
223 pinctrl-1 = <&wf_dbdc_pins>;
developer565bacb2021-09-28 21:26:32 +0800224};
225
226&pio {
227 spi_flash_pins: spi-flash-pins-33-to-38 {
228 mux {
229 function = "flash";
230 groups = "spi0", "spi0_wp_hold";
231 };
232 conf-pu {
233 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
234 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800235 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800236 };
237 conf-pd {
238 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
239 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800240 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800241 };
242 };
developere138bcd2021-12-06 09:20:47 +0800243
244 wf_2g_5g_pins: wf_2g_5g-pins {
245 mux {
246 function = "wifi";
247 groups = "wf_2g", "wf_5g";
248 };
249 conf {
250 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
251 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
252 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
253 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
254 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
255 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
256 "WF1_TOP_CLK", "WF1_TOP_DATA";
257 drive-strength = <MTK_DRIVE_4mA>;
258 };
259 };
260
261 wf_dbdc_pins: wf_dbdc-pins {
262 mux {
263 function = "wifi";
264 groups = "wf_dbdc";
265 };
266 conf {
267 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
268 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
269 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
270 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
271 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
272 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
273 "WF1_TOP_CLK", "WF1_TOP_DATA";
274 drive-strength = <MTK_DRIVE_4mA>;
275 };
276 };
developer565bacb2021-09-28 21:26:32 +0800277};