developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7986a.dtsi" |
| 3 | #include "mt7986a-pinctrl.dtsi" |
| 4 | / { |
| 5 | model = "MediaTek MT7986a RFB"; |
| 6 | compatible = "mediatek,mt7986a-2500wan-sd-rfb"; |
| 7 | chosen { |
| 8 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 9 | earlycon=uart8250,mmio32,0x11002000 \ |
| 10 | root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; |
| 11 | }; |
| 12 | |
| 13 | memory { |
| 14 | reg = <0 0x40000000 0 0x10000000>; |
| 15 | }; |
| 16 | |
| 17 | sound { |
| 18 | compatible = "mediatek,mt7986-wm8960-machine"; |
| 19 | mediatek,platform = <&afe>; |
| 20 | audio-routing = "Headphone", "HP_L", |
| 21 | "Headphone", "HP_R", |
| 22 | "LINPUT1", "AMIC", |
| 23 | "RINPUT1", "AMIC"; |
| 24 | mediatek,audio-codec = <&wm8960>; |
| 25 | status = "okay"; |
| 26 | }; |
| 27 | |
| 28 | reg_3p3v: regulator-3p3v { |
| 29 | compatible = "regulator-fixed"; |
| 30 | regulator-name = "fixed-3.3V"; |
| 31 | regulator-min-microvolt = <3300000>; |
| 32 | regulator-max-microvolt = <3300000>; |
| 33 | regulator-boot-on; |
| 34 | regulator-always-on; |
| 35 | }; |
| 36 | }; |
| 37 | |
developer | 209e52d | 2022-06-30 11:32:57 +0800 | [diff] [blame] | 38 | &fan { |
| 39 | pwms = <&pwm 1 50000 0>; |
| 40 | status = "disabled"; |
| 41 | }; |
| 42 | |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 43 | &pwm { |
| 44 | pinctrl-names = "default"; |
| 45 | pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>; |
| 46 | status = "okay"; |
| 47 | }; |
| 48 | |
| 49 | &uart0 { |
| 50 | status = "okay"; |
| 51 | }; |
| 52 | |
| 53 | &uart1 { |
| 54 | pinctrl-names = "default"; |
| 55 | pinctrl-0 = <&uart1_pins>; |
| 56 | status = "okay"; |
| 57 | }; |
| 58 | |
| 59 | &uart2 { |
| 60 | pinctrl-names = "default"; |
| 61 | pinctrl-0 = <&uart2_pins>; |
developer | e0c42a1 | 2022-08-19 11:01:38 +0800 | [diff] [blame^] | 62 | status = "okay"; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | &i2c0 { |
| 66 | pinctrl-names = "default"; |
| 67 | pinctrl-0 = <&i2c_pins>; |
| 68 | status = "okay"; |
| 69 | |
| 70 | wm8960: wm8960@1a { |
| 71 | compatible = "wlf,wm8960"; |
| 72 | reg = <0x1a>; |
| 73 | }; |
| 74 | }; |
| 75 | |
| 76 | &auxadc { |
| 77 | status = "okay"; |
| 78 | }; |
| 79 | |
| 80 | &watchdog { |
| 81 | status = "okay"; |
| 82 | }; |
| 83 | |
| 84 | ð { |
| 85 | status = "okay"; |
| 86 | |
| 87 | gmac0: mac@0 { |
| 88 | compatible = "mediatek,eth-mac"; |
| 89 | reg = <0>; |
| 90 | phy-mode = "2500base-x"; |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame] | 91 | |
| 92 | fixed-link { |
| 93 | speed = <2500>; |
| 94 | full-duplex; |
| 95 | pause; |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame] | 96 | }; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | gmac1: mac@1 { |
| 100 | compatible = "mediatek,eth-mac"; |
| 101 | reg = <1>; |
| 102 | phy-mode = "2500base-x"; |
developer | f0a1e45 | 2022-08-15 12:06:11 +0800 | [diff] [blame] | 103 | phy-handle = <&phy6>; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | mdio: mdio-bus { |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <0>; |
| 109 | |
developer | f0a1e45 | 2022-08-15 12:06:11 +0800 | [diff] [blame] | 110 | reset-gpios = <&pio 6 1>; |
| 111 | reset-delay-us = <600>; |
| 112 | |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 113 | phy5: phy@5 { |
developer | e0c42a1 | 2022-08-19 11:01:38 +0800 | [diff] [blame^] | 114 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 115 | reg = <5>; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | phy6: phy@6 { |
developer | f0a1e45 | 2022-08-15 12:06:11 +0800 | [diff] [blame] | 119 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 120 | reg = <6>; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 121 | }; |
| 122 | |
| 123 | switch@0 { |
| 124 | compatible = "mediatek,mt7531"; |
| 125 | reg = <31>; |
| 126 | reset-gpios = <&pio 5 0>; |
| 127 | |
| 128 | ports { |
| 129 | #address-cells = <1>; |
| 130 | #size-cells = <0>; |
| 131 | |
| 132 | port@0 { |
| 133 | reg = <0>; |
| 134 | label = "lan0"; |
| 135 | }; |
| 136 | |
| 137 | port@1 { |
| 138 | reg = <1>; |
| 139 | label = "lan1"; |
| 140 | }; |
| 141 | |
| 142 | port@2 { |
| 143 | reg = <2>; |
| 144 | label = "lan2"; |
| 145 | }; |
| 146 | |
| 147 | port@3 { |
| 148 | reg = <3>; |
| 149 | label = "lan3"; |
| 150 | }; |
| 151 | |
| 152 | port@4 { |
| 153 | reg = <4>; |
| 154 | label = "lan4"; |
| 155 | }; |
| 156 | |
| 157 | port@5 { |
| 158 | reg = <5>; |
| 159 | label = "lan5"; |
| 160 | phy-mode = "2500base-x"; |
developer | e0c42a1 | 2022-08-19 11:01:38 +0800 | [diff] [blame^] | 161 | phy-handle = <&phy5>; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 162 | }; |
| 163 | |
| 164 | port@6 { |
| 165 | reg = <6>; |
| 166 | label = "cpu"; |
| 167 | ethernet = <&gmac0>; |
| 168 | phy-mode = "2500base-x"; |
| 169 | |
| 170 | fixed-link { |
| 171 | speed = <2500>; |
| 172 | full-duplex; |
| 173 | pause; |
| 174 | }; |
| 175 | }; |
| 176 | }; |
| 177 | }; |
| 178 | }; |
| 179 | }; |
| 180 | |
| 181 | &hnat { |
| 182 | mtketh-wan = "eth1"; |
| 183 | mtketh-lan = "lan"; |
| 184 | mtketh-max-gmac = <2>; |
| 185 | status = "okay"; |
| 186 | }; |
| 187 | |
| 188 | &mmc0 { |
| 189 | pinctrl-names = "default", "state_uhs"; |
| 190 | pinctrl-0 = <&mmc0_pins_default>; |
| 191 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 192 | bus-width = <4>; |
| 193 | max-frequency = <52000000>; |
| 194 | cap-sd-highspeed; |
| 195 | vmmc-supply = <®_3p3v>; |
| 196 | vqmmc-supply = <®_3p3v>; |
| 197 | status = "okay"; |
| 198 | }; |
| 199 | |
| 200 | &pcie0 { |
| 201 | pinctrl-names = "default"; |
| 202 | pinctrl-0 = <&pcie0_pins>; |
| 203 | status = "okay"; |
| 204 | }; |
| 205 | |
| 206 | &pio { |
| 207 | mmc0_pins_default: mmc0-pins-50-to-61-default { |
| 208 | mux { |
| 209 | function = "flash"; |
| 210 | groups = "emmc_51"; |
| 211 | }; |
| 212 | conf-cmd-dat { |
| 213 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 214 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 215 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 216 | input-enable; |
| 217 | drive-strength = <MTK_DRIVE_4mA>; |
| 218 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 219 | }; |
| 220 | conf-clk { |
| 221 | pins = "EMMC_CK"; |
| 222 | drive-strength = <MTK_DRIVE_6mA>; |
| 223 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 224 | }; |
| 225 | conf-ds { |
| 226 | pins = "EMMC_DSL"; |
| 227 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 228 | }; |
| 229 | conf-rst { |
| 230 | pins = "EMMC_RSTB"; |
| 231 | drive-strength = <MTK_DRIVE_4mA>; |
| 232 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 233 | }; |
| 234 | }; |
| 235 | |
| 236 | mmc0_pins_uhs: mmc0-pins-50-to-61-uhs { |
| 237 | mux { |
| 238 | function = "flash"; |
| 239 | groups = "emmc_51"; |
| 240 | }; |
| 241 | conf-cmd-dat { |
| 242 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 243 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 244 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 245 | input-enable; |
| 246 | drive-strength = <MTK_DRIVE_4mA>; |
| 247 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 248 | }; |
| 249 | conf-clk { |
| 250 | pins = "EMMC_CK"; |
| 251 | drive-strength = <MTK_DRIVE_6mA>; |
| 252 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 253 | }; |
| 254 | conf-ds { |
| 255 | pins = "EMMC_DSL"; |
| 256 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 257 | }; |
| 258 | conf-rst { |
| 259 | pins = "EMMC_RSTB"; |
| 260 | drive-strength = <MTK_DRIVE_4mA>; |
| 261 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 262 | }; |
| 263 | }; |
| 264 | |
| 265 | wf_2g_5g_pins: wf_2g_5g-pins { |
| 266 | mux { |
| 267 | function = "wifi"; |
| 268 | groups = "wf_2g", "wf_5g"; |
| 269 | }; |
| 270 | conf { |
| 271 | pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", |
| 272 | "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", |
| 273 | "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", |
| 274 | "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", |
| 275 | "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", |
| 276 | "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", |
| 277 | "WF1_TOP_CLK", "WF1_TOP_DATA"; |
| 278 | drive-strength = <MTK_DRIVE_4mA>; |
| 279 | }; |
| 280 | }; |
| 281 | |
| 282 | wf_dbdc_pins: wf_dbdc-pins { |
| 283 | mux { |
| 284 | function = "wifi"; |
| 285 | groups = "wf_dbdc"; |
| 286 | }; |
| 287 | conf { |
| 288 | pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", |
| 289 | "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", |
| 290 | "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", |
| 291 | "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", |
| 292 | "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", |
| 293 | "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", |
| 294 | "WF1_TOP_CLK", "WF1_TOP_DATA"; |
| 295 | drive-strength = <MTK_DRIVE_4mA>; |
| 296 | }; |
| 297 | }; |
| 298 | }; |