developer | 32e626c | 2021-12-14 11:01:32 +0800 | [diff] [blame] | 1 | diff --git a/build_dir/target-aarch64_cortex-a53_musl/linux-mediatek_mt7981/linux-5.4.163/drivers/pwm/pwm-mediatek.c b/build_dir/target-aarch64_cortex-a53_musl/linux-mediatek_mt7981/linux-5.4.163/drivers/pwm/pwm-mediatek.c |
| 2 | index 7c56ee2..3a5a456 100644 |
| 3 | --- a/build_dir/target-aarch64_cortex-a53_musl/linux-mediatek_mt7981/linux-5.4.163/drivers/pwm/pwm-mediatek.c |
| 4 | +++ b/build_dir/target-aarch64_cortex-a53_musl/linux-mediatek_mt7981/linux-5.4.163/drivers/pwm/pwm-mediatek.c |
| 5 | @@ -20,7 +20,6 @@ |
| 6 | #include <linux/slab.h> |
| 7 | #include <linux/types.h> |
| 8 | |
| 9 | - |
| 10 | /* PWM registers and bits definitions */ |
| 11 | #define PWMCON 0x00 |
| 12 | #define PWMHDUR 0x04 |
| 13 | @@ -33,10 +32,13 @@ |
| 14 | #define PWM45THRES_FIXUP 0x34 |
| 15 | |
| 16 | #define PWM_CLK_DIV_MAX 7 |
| 17 | +#define REG_V1 1 |
| 18 | +#define REG_V2 2 |
| 19 | |
| 20 | struct pwm_mediatek_of_data { |
| 21 | unsigned int num_pwms; |
| 22 | bool pwm45_fixup; |
| 23 | + int reg_ver; |
| 24 | }; |
| 25 | |
| 26 | /** |
| 27 | @@ -57,10 +59,14 @@ struct pwm_mediatek_chip { |
| 28 | const struct pwm_mediatek_of_data *soc; |
| 29 | }; |
| 30 | |
| 31 | -static const unsigned int pwm_mediatek_reg_offset[] = { |
| 32 | +static const unsigned int mtk_pwm_reg_offset_v1[] = { |
| 33 | 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 |
| 34 | }; |
| 35 | |
| 36 | +static const unsigned int mtk_pwm_reg_offset_v2[] = { |
| 37 | + 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x1c0, 0x200, 0x0240 |
| 38 | +}; |
| 39 | + |
| 40 | static inline struct pwm_mediatek_chip * |
| 41 | to_pwm_mediatek_chip(struct pwm_chip *chip) |
| 42 | { |
| 43 | @@ -108,14 +114,38 @@ static void pwm_mediatek_clk_disable(struct pwm_chip *chip, |
| 44 | static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip, |
| 45 | unsigned int num, unsigned int offset) |
| 46 | { |
| 47 | - return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset); |
| 48 | + u32 pwm_offset; |
| 49 | + |
| 50 | + switch (chip->soc->reg_ver) { |
| 51 | + case REG_V2: |
| 52 | + pwm_offset = mtk_pwm_reg_offset_v2[num]; |
| 53 | + break; |
| 54 | + |
| 55 | + case REG_V1: |
| 56 | + default: |
| 57 | + pwm_offset = mtk_pwm_reg_offset_v1[num]; |
| 58 | + } |
| 59 | + |
| 60 | + return readl(chip->regs + pwm_offset + offset); |
| 61 | } |
| 62 | |
| 63 | static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, |
| 64 | unsigned int num, unsigned int offset, |
| 65 | u32 value) |
| 66 | { |
| 67 | - writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); |
| 68 | + u32 pwm_offset; |
| 69 | + |
| 70 | + switch (chip->soc->reg_ver) { |
| 71 | + case REG_V2: |
| 72 | + pwm_offset = mtk_pwm_reg_offset_v2[num]; |
| 73 | + break; |
| 74 | + |
| 75 | + case REG_V1: |
| 76 | + default: |
| 77 | + pwm_offset = mtk_pwm_reg_offset_v1[num]; |
| 78 | + } |
| 79 | + |
| 80 | + writel(value, chip->regs + pwm_offset + offset); |
| 81 | } |
| 82 | |
| 83 | static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, |
| 84 | @@ -281,36 +311,49 @@ static int pwm_mediatek_remove(struct platform_device *pdev) |
| 85 | static const struct pwm_mediatek_of_data mt2712_pwm_data = { |
| 86 | .num_pwms = 8, |
| 87 | .pwm45_fixup = false, |
| 88 | + .reg_ver = REG_V1, |
| 89 | }; |
| 90 | |
| 91 | static const struct pwm_mediatek_of_data mt7622_pwm_data = { |
| 92 | .num_pwms = 6, |
| 93 | .pwm45_fixup = false, |
| 94 | + .reg_ver = REG_V1, |
| 95 | }; |
| 96 | |
| 97 | static const struct pwm_mediatek_of_data mt7623_pwm_data = { |
| 98 | .num_pwms = 5, |
| 99 | .pwm45_fixup = true, |
| 100 | + .reg_ver = REG_V1, |
| 101 | }; |
| 102 | |
| 103 | static const struct pwm_mediatek_of_data mt7628_pwm_data = { |
| 104 | .num_pwms = 4, |
| 105 | .pwm45_fixup = true, |
| 106 | + .reg_ver = REG_V1, |
| 107 | }; |
| 108 | |
| 109 | static const struct pwm_mediatek_of_data mt7629_pwm_data = { |
| 110 | .num_pwms = 1, |
| 111 | .pwm45_fixup = false, |
| 112 | + .reg_ver = REG_V1, |
| 113 | +}; |
| 114 | + |
| 115 | +static const struct pwm_mediatek_of_data mt7981_pwm_data = { |
| 116 | + .num_pwms = 3, |
| 117 | + .pwm45_fixup = false, |
| 118 | + .reg_ver = REG_V2, |
| 119 | }; |
| 120 | |
| 121 | static const struct pwm_mediatek_of_data mt7986_pwm_data = { |
| 122 | .num_pwms = 2, |
| 123 | .pwm45_fixup = false, |
| 124 | + .reg_ver = REG_V2, |
| 125 | }; |
| 126 | |
| 127 | static const struct pwm_mediatek_of_data mt8516_pwm_data = { |
| 128 | .num_pwms = 5, |
| 129 | .pwm45_fixup = false, |
| 130 | + .reg_ver = REG_V1, |
| 131 | }; |
| 132 | |
| 133 | static const struct of_device_id pwm_mediatek_of_match[] = { |
| 134 | @@ -319,6 +362,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = { |
| 135 | { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, |
| 136 | { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, |
| 137 | { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, |
| 138 | + { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, |
| 139 | { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, |
| 140 | { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, |
| 141 | { }, |