developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* Copyright (C) 2020 MediaTek Inc. */ |
| 3 | |
| 4 | #ifndef __BERSA_MCU_H |
| 5 | #define __BERSA_MCU_H |
| 6 | |
| 7 | #include "../mt76_connac_mcu.h" |
| 8 | |
| 9 | struct bersa_mcu_txd { |
| 10 | __le32 txd[8]; |
| 11 | |
| 12 | __le16 len; |
| 13 | __le16 pq_id; |
| 14 | |
| 15 | u8 cid; |
| 16 | u8 pkt_type; |
| 17 | u8 set_query; /* FW don't care */ |
| 18 | u8 seq; |
| 19 | |
| 20 | u8 uc_d2b0_rev; |
| 21 | u8 ext_cid; |
| 22 | u8 s2d_index; |
| 23 | u8 ext_cid_ack; |
| 24 | |
| 25 | u32 reserved[5]; |
| 26 | } __packed __aligned(4); |
| 27 | |
| 28 | /** |
| 29 | * struct bersa_uni_txd - mcu command descriptor for firmware v3 |
| 30 | * @txd: hardware descriptor |
| 31 | * @len: total length not including txd |
| 32 | * @cid: command identifier |
| 33 | * @pkt_type: must be 0xa0 (cmd packet by long format) |
| 34 | * @frag_n: fragment number |
| 35 | * @seq: sequence number |
| 36 | * @checksum: 0 mean there is no checksum |
| 37 | * @s2d_index: index for command source and destination |
| 38 | * Definition | value | note |
| 39 | * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM |
| 40 | * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM |
| 41 | * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA |
| 42 | * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM |
| 43 | * |
| 44 | * @option: command option |
| 45 | * BIT[0]: UNI_CMD_OPT_BIT_ACK |
| 46 | * set to 1 to request a fw reply |
| 47 | * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY |
| 48 | * is set, mcu firmware will send response event EID = 0x01 |
| 49 | * (UNI_EVENT_ID_CMD_RESULT) to the host. |
| 50 | * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD |
| 51 | * 0: original command |
| 52 | * 1: unified command |
| 53 | * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY |
| 54 | * 0: QUERY command |
| 55 | * 1: SET command |
| 56 | */ |
| 57 | struct bersa_uni_txd { |
| 58 | __le32 txd[8]; |
| 59 | |
| 60 | /* DW1 */ |
| 61 | __le16 len; |
| 62 | __le16 cid; |
| 63 | |
| 64 | /* DW2 */ |
| 65 | u8 reserved; |
| 66 | u8 pkt_type; |
| 67 | u8 frag_n; |
| 68 | u8 seq; |
| 69 | |
| 70 | /* DW3 */ |
| 71 | __le16 checksum; |
| 72 | u8 s2d_index; |
| 73 | u8 option; |
| 74 | |
| 75 | /* DW4 */ |
| 76 | u8 reserved2[4]; |
| 77 | } __packed __aligned(4); |
| 78 | |
| 79 | enum { |
| 80 | MCU_ATE_SET_TRX = 0x1, |
| 81 | MCU_ATE_SET_FREQ_OFFSET = 0xa, |
| 82 | MCU_ATE_SET_SLOT_TIME = 0x13, |
| 83 | MCU_ATE_CLEAN_TXQUEUE = 0x1c, |
| 84 | }; |
| 85 | |
| 86 | struct bersa_mcu_rxd { |
| 87 | __le32 rxd[8]; |
| 88 | |
| 89 | __le16 len; |
| 90 | __le16 pkt_type_id; |
| 91 | |
| 92 | u8 eid; |
| 93 | u8 seq; |
| 94 | u8 option; |
| 95 | u8 __rsv; |
| 96 | |
| 97 | u8 ext_eid; |
| 98 | u8 __rsv1[2]; |
| 99 | u8 s2d_index; |
| 100 | }; |
| 101 | |
| 102 | struct bersa_mcu_uni_event { |
| 103 | u8 cid; |
| 104 | u8 __rsv[3]; |
| 105 | __le32 status; /* 0: success, others: fail */ |
| 106 | } __packed; |
| 107 | |
| 108 | struct bersa_mcu_thermal_ctrl { |
| 109 | u8 ctrl_id; |
| 110 | u8 band_idx; |
| 111 | union { |
| 112 | struct { |
| 113 | u8 protect_type; /* 1: duty admit, 2: radio off */ |
| 114 | u8 trigger_type; /* 0: low, 1: high */ |
| 115 | } __packed type; |
| 116 | struct { |
| 117 | u8 duty_level; /* level 0~3 */ |
| 118 | u8 duty_cycle; |
| 119 | } __packed duty; |
| 120 | }; |
| 121 | } __packed; |
| 122 | |
| 123 | struct bersa_mcu_thermal_notify { |
| 124 | struct bersa_mcu_rxd rxd; |
| 125 | |
| 126 | struct bersa_mcu_thermal_ctrl ctrl; |
| 127 | __le32 temperature; |
| 128 | u8 rsv[8]; |
| 129 | } __packed; |
| 130 | |
| 131 | struct bersa_mcu_csa_notify { |
| 132 | struct bersa_mcu_rxd rxd; |
| 133 | |
| 134 | u8 omac_idx; |
| 135 | u8 csa_count; |
| 136 | u8 band_idx; |
| 137 | u8 rsv; |
| 138 | } __packed; |
| 139 | |
| 140 | struct bersa_mcu_rdd_report { |
| 141 | struct bersa_mcu_rxd rxd; |
| 142 | |
| 143 | u8 band_idx; |
| 144 | u8 long_detected; |
| 145 | u8 constant_prf_detected; |
| 146 | u8 staggered_prf_detected; |
| 147 | u8 radar_type_idx; |
| 148 | u8 periodic_pulse_num; |
| 149 | u8 long_pulse_num; |
| 150 | u8 hw_pulse_num; |
| 151 | |
| 152 | u8 out_lpn; |
| 153 | u8 out_spn; |
| 154 | u8 out_crpn; |
| 155 | u8 out_crpw; |
| 156 | u8 out_crbn; |
| 157 | u8 out_stgpn; |
| 158 | u8 out_stgpw; |
| 159 | |
| 160 | u8 rsv; |
| 161 | |
| 162 | __le32 out_pri_const; |
| 163 | __le32 out_pri_stg[3]; |
| 164 | |
| 165 | struct { |
| 166 | __le32 start; |
| 167 | __le16 pulse_width; |
| 168 | __le16 pulse_power; |
| 169 | u8 mdrdy_flag; |
| 170 | u8 rsv[3]; |
| 171 | } long_pulse[32]; |
| 172 | |
| 173 | struct { |
| 174 | __le32 start; |
| 175 | __le16 pulse_width; |
| 176 | __le16 pulse_power; |
| 177 | u8 mdrdy_flag; |
| 178 | u8 rsv[3]; |
| 179 | } periodic_pulse[32]; |
| 180 | |
| 181 | struct { |
| 182 | __le32 start; |
| 183 | __le16 pulse_width; |
| 184 | __le16 pulse_power; |
| 185 | u8 sc_pass; |
| 186 | u8 sw_reset; |
| 187 | u8 mdrdy_flag; |
| 188 | u8 tx_active; |
| 189 | } hw_pulse[32]; |
| 190 | } __packed; |
| 191 | |
| 192 | struct bersa_mcu_background_chain_ctrl { |
| 193 | u8 chan; /* primary channel */ |
| 194 | u8 central_chan; /* central channel */ |
| 195 | u8 bw; |
| 196 | u8 tx_stream; |
| 197 | u8 rx_stream; |
| 198 | |
| 199 | u8 monitor_chan; /* monitor channel */ |
| 200 | u8 monitor_central_chan;/* monitor central channel */ |
| 201 | u8 monitor_bw; |
| 202 | u8 monitor_tx_stream; |
| 203 | u8 monitor_rx_stream; |
| 204 | |
| 205 | u8 scan_mode; /* 0: ScanStop |
| 206 | * 1: ScanStart |
| 207 | * 2: ScanRunning |
| 208 | */ |
| 209 | u8 band_idx; /* DBDC */ |
| 210 | u8 monitor_scan_type; |
| 211 | u8 band; /* 0: 2.4GHz, 1: 5GHz */ |
| 212 | u8 rsv[2]; |
| 213 | } __packed; |
| 214 | |
| 215 | struct bersa_mcu_eeprom { |
| 216 | u8 _rsv[4]; |
| 217 | |
| 218 | __le16 tag; |
| 219 | __le16 len; |
| 220 | u8 buffer_mode; |
| 221 | u8 format; |
| 222 | __le16 buf_len; |
| 223 | } __packed; |
| 224 | |
| 225 | struct bersa_mcu_eeprom_info { |
| 226 | __le32 addr; |
| 227 | __le32 valid; |
| 228 | u8 data[16]; |
| 229 | } __packed; |
| 230 | |
| 231 | struct bersa_mcu_phy_rx_info { |
| 232 | u8 category; |
| 233 | u8 rate; |
| 234 | u8 mode; |
| 235 | u8 nsts; |
| 236 | u8 gi; |
| 237 | u8 coding; |
| 238 | u8 stbc; |
| 239 | u8 bw; |
| 240 | }; |
| 241 | |
| 242 | struct bersa_mcu_mib { |
| 243 | __le16 tag; |
| 244 | __le16 len; |
| 245 | __le32 offs; |
| 246 | __le64 data; |
| 247 | } __packed; |
| 248 | |
| 249 | enum bersa_chan_mib_offs { |
| 250 | /* bersa */ |
| 251 | MIB_BUSY_TIME = 0, |
| 252 | MIB_TX_TIME = 6, |
| 253 | MIB_RX_TIME = 8, |
| 254 | MIB_OBSS_AIRTIME = 499, |
| 255 | }; |
| 256 | |
| 257 | struct edca { |
| 258 | __le16 tag; |
| 259 | __le16 len; |
| 260 | |
| 261 | u8 queue; |
| 262 | u8 set; |
| 263 | u8 cw_min; |
| 264 | u8 cw_max; |
| 265 | __le16 txop; |
| 266 | u8 aifs; |
| 267 | u8 __rsv; |
| 268 | }; |
| 269 | |
| 270 | struct bersa_mcu_muru_stats { |
| 271 | __le32 event_id; |
| 272 | struct { |
| 273 | __le32 cck_cnt; |
| 274 | __le32 ofdm_cnt; |
| 275 | __le32 htmix_cnt; |
| 276 | __le32 htgf_cnt; |
| 277 | __le32 vht_su_cnt; |
| 278 | __le32 vht_2mu_cnt; |
| 279 | __le32 vht_3mu_cnt; |
| 280 | __le32 vht_4mu_cnt; |
| 281 | __le32 he_su_cnt; |
| 282 | __le32 he_ext_su_cnt; |
| 283 | __le32 he_2ru_cnt; |
| 284 | __le32 he_2mu_cnt; |
| 285 | __le32 he_3ru_cnt; |
| 286 | __le32 he_3mu_cnt; |
| 287 | __le32 he_4ru_cnt; |
| 288 | __le32 he_4mu_cnt; |
| 289 | __le32 he_5to8ru_cnt; |
| 290 | __le32 he_9to16ru_cnt; |
| 291 | __le32 he_gtr16ru_cnt; |
| 292 | } dl; |
| 293 | |
| 294 | struct { |
| 295 | __le32 hetrig_su_cnt; |
| 296 | __le32 hetrig_2ru_cnt; |
| 297 | __le32 hetrig_3ru_cnt; |
| 298 | __le32 hetrig_4ru_cnt; |
| 299 | __le32 hetrig_5to8ru_cnt; |
| 300 | __le32 hetrig_9to16ru_cnt; |
| 301 | __le32 hetrig_gtr16ru_cnt; |
| 302 | __le32 hetrig_2mu_cnt; |
| 303 | __le32 hetrig_3mu_cnt; |
| 304 | __le32 hetrig_4mu_cnt; |
| 305 | } ul; |
| 306 | }; |
| 307 | |
| 308 | #define WMM_AIFS_SET BIT(0) |
| 309 | #define WMM_CW_MIN_SET BIT(1) |
| 310 | #define WMM_CW_MAX_SET BIT(2) |
| 311 | #define WMM_TXOP_SET BIT(3) |
| 312 | #define WMM_PARAM_SET GENMASK(3, 0) |
| 313 | |
| 314 | #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) |
| 315 | #define MCU_PKT_ID 0xa0 |
| 316 | |
| 317 | enum { |
| 318 | MCU_FW_LOG_WM, |
| 319 | MCU_FW_LOG_WA, |
| 320 | MCU_FW_LOG_TO_HOST, |
| 321 | MCU_FW_LOG_RELAY = 16 |
| 322 | }; |
| 323 | |
| 324 | enum { |
| 325 | MCU_TWT_AGRT_ADD, |
| 326 | MCU_TWT_AGRT_MODIFY, |
| 327 | MCU_TWT_AGRT_DELETE, |
| 328 | MCU_TWT_AGRT_TEARDOWN, |
| 329 | MCU_TWT_AGRT_GET_TSF, |
| 330 | }; |
| 331 | |
| 332 | enum { |
| 333 | MCU_WA_PARAM_CMD_QUERY, |
| 334 | MCU_WA_PARAM_CMD_SET, |
| 335 | MCU_WA_PARAM_CMD_CAPABILITY, |
| 336 | MCU_WA_PARAM_CMD_DEBUG, |
| 337 | }; |
| 338 | |
| 339 | enum { |
| 340 | MCU_WA_PARAM_PDMA_RX = 0x04, |
| 341 | MCU_WA_PARAM_CPU_UTIL = 0x0b, |
| 342 | MCU_WA_PARAM_RED = 0x0e, |
| 343 | }; |
| 344 | |
| 345 | enum mcu_mmps_mode { |
| 346 | MCU_MMPS_STATIC, |
| 347 | MCU_MMPS_DYNAMIC, |
| 348 | MCU_MMPS_RSV, |
| 349 | MCU_MMPS_DISABLE, |
| 350 | }; |
| 351 | |
| 352 | enum { |
| 353 | SCS_SEND_DATA, |
| 354 | SCS_SET_MANUAL_PD_TH, |
| 355 | SCS_CONFIG, |
| 356 | SCS_ENABLE, |
| 357 | SCS_SHOW_INFO, |
| 358 | SCS_GET_GLO_ADDR, |
| 359 | SCS_GET_GLO_ADDR_EVENT, |
| 360 | }; |
| 361 | |
| 362 | struct bss_rate_tlv { |
| 363 | __le16 tag; |
| 364 | __le16 len; |
| 365 | u8 __rsv1[4]; |
| 366 | __le16 bc_trans; |
| 367 | __le16 mc_trans; |
| 368 | u8 short_preamble; |
| 369 | u8 bc_fixed_rate; |
| 370 | u8 mc_fixed_rate; |
| 371 | u8 __rsv2[1]; |
| 372 | } __packed; |
| 373 | |
| 374 | struct bss_ra_tlv { |
| 375 | __le16 tag; |
| 376 | __le16 len; |
| 377 | u8 short_preamble; |
| 378 | u8 force_sgi; |
| 379 | u8 force_gf; |
| 380 | u8 ht_mode; |
| 381 | u8 se_off; |
| 382 | u8 antenna_idx; |
| 383 | __le16 max_phyrate; |
| 384 | u8 force_tx_streams; |
| 385 | u8 __rsv[3]; |
| 386 | } __packed; |
| 387 | |
| 388 | struct bss_rlm_tlv { |
| 389 | __le16 tag; |
| 390 | __le16 len; |
| 391 | u8 control_channel; |
| 392 | u8 center_chan; |
| 393 | u8 center_chan2; |
| 394 | u8 bw; |
| 395 | u8 tx_streams; |
| 396 | u8 rx_streams; |
| 397 | u8 ht_op_info; |
| 398 | u8 sco; |
| 399 | u8 band; |
| 400 | u8 __rsv[3]; |
| 401 | } __packed; |
| 402 | |
| 403 | struct bss_color_tlv { |
| 404 | __le16 tag; |
| 405 | __le16 len; |
| 406 | u8 enable; |
| 407 | u8 color; |
| 408 | u8 rsv[2]; |
| 409 | } __packed; |
| 410 | |
| 411 | #define MAX_BEACON_SIZE 512 |
| 412 | struct bss_bcn_content_tlv { |
| 413 | __le16 tag; |
| 414 | __le16 len; |
| 415 | __le16 tim_ie_pos; |
| 416 | __le16 csa_ie_pos; |
| 417 | __le16 bcc_ie_pos; |
| 418 | u8 enable; |
| 419 | u8 type; |
| 420 | __le16 pkt_len; |
| 421 | u8 pkt[MAX_BEACON_SIZE]; |
| 422 | } __packed; |
| 423 | |
| 424 | struct bss_bcn_cntdwn_tlv { |
| 425 | __le16 tag; |
| 426 | __le16 len; |
| 427 | u8 cnt; |
| 428 | u8 rsv[3]; |
| 429 | } __packed; |
| 430 | |
| 431 | struct bss_bcn_mbss_tlv { |
| 432 | #define MAX_BEACON_NUM 32 |
| 433 | __le16 tag; |
| 434 | __le16 len; |
| 435 | __le32 bitmap; |
| 436 | __le16 offset[MAX_BEACON_NUM]; |
| 437 | } __packed __aligned(4); |
| 438 | |
| 439 | struct bss_txcmd_tlv { |
| 440 | __le16 tag; |
| 441 | __le16 len; |
| 442 | u8 txcmd_mode; |
| 443 | u8 __rsv[3]; |
| 444 | } __packed; |
| 445 | |
| 446 | struct bss_sec_tlv { |
| 447 | __le16 tag; |
| 448 | __le16 len; |
| 449 | u8 __rsv1[2]; |
| 450 | u8 cipher; |
| 451 | u8 __rsv2[1]; |
| 452 | } __packed; |
| 453 | |
| 454 | struct bss_power_save { |
| 455 | __le16 tag; |
| 456 | __le16 len; |
| 457 | u8 profile; |
| 458 | u8 _rsv[3]; |
| 459 | } __packed; |
| 460 | |
| 461 | struct bss_mld_tlv { |
| 462 | __le16 tag; |
| 463 | __le16 len; |
| 464 | u8 group_mld_id; |
| 465 | u8 own_mld_id; |
| 466 | u8 mac_addr[ETH_ALEN]; |
| 467 | u8 remap_idx; |
| 468 | u8 __rsv[3]; |
| 469 | } __packed; |
| 470 | |
| 471 | struct hdr_trans_en { |
| 472 | __le16 tag; |
| 473 | __le16 len; |
| 474 | u8 enable; |
| 475 | u8 check_bssid; |
| 476 | u8 mode; |
| 477 | u8 __rsv; |
| 478 | } __packed; |
| 479 | |
| 480 | struct hdr_trans_vlan { |
| 481 | __le16 tag; |
| 482 | __le16 len; |
| 483 | u8 insert_vlan; |
| 484 | u8 remove_vlan; |
| 485 | u8 tid; |
| 486 | u8 __rsv; |
| 487 | } __packed; |
| 488 | |
| 489 | struct hdr_trans_blacklist { |
| 490 | __le16 tag; |
| 491 | __le16 len; |
| 492 | u8 idx; |
| 493 | u8 enable; |
| 494 | __le16 type; |
| 495 | } __packed; |
| 496 | |
| 497 | #define BERSA_HDR_TRANS_MAX_SIZE (sizeof(struct hdr_trans_en) + \ |
| 498 | sizeof(struct hdr_trans_vlan) + \ |
| 499 | sizeof(struct hdr_trans_blacklist)) |
| 500 | |
| 501 | enum { |
| 502 | UNI_HDR_TRANS_EN, |
| 503 | UNI_HDR_TRANS_VLAN, |
| 504 | UNI_HDR_TRANS_BLACKLIST, |
| 505 | }; |
| 506 | |
| 507 | enum { |
| 508 | RATE_PARAM_FIXED = 3, |
| 509 | RATE_PARAM_MMPS_UPDATE = 5, |
| 510 | RATE_PARAM_FIXED_HE_LTF = 7, |
| 511 | RATE_PARAM_FIXED_MCS, |
| 512 | RATE_PARAM_FIXED_GI = 11, |
| 513 | RATE_PARAM_AUTO = 20, |
| 514 | }; |
| 515 | |
| 516 | #define RATE_CFG_MCS GENMASK(3, 0) |
| 517 | #define RATE_CFG_NSS GENMASK(7, 4) |
| 518 | #define RATE_CFG_GI GENMASK(11, 8) |
| 519 | #define RATE_CFG_BW GENMASK(15, 12) |
| 520 | #define RATE_CFG_STBC GENMASK(19, 16) |
| 521 | #define RATE_CFG_LDPC GENMASK(23, 20) |
| 522 | #define RATE_CFG_PHY_TYPE GENMASK(27, 24) |
| 523 | #define RATE_CFG_HE_LTF GENMASK(31, 28) |
| 524 | |
| 525 | enum { |
| 526 | THERMAL_PROTECT_PARAMETER_CTRL, |
| 527 | THERMAL_PROTECT_BASIC_INFO, |
| 528 | THERMAL_PROTECT_ENABLE, |
| 529 | THERMAL_PROTECT_DISABLE, |
| 530 | THERMAL_PROTECT_DUTY_CONFIG, |
| 531 | THERMAL_PROTECT_MECH_INFO, |
| 532 | THERMAL_PROTECT_DUTY_INFO, |
| 533 | THERMAL_PROTECT_STATE_ACT, |
| 534 | }; |
| 535 | |
| 536 | enum { |
| 537 | MT_BF_SOUNDING_ON = 1, |
| 538 | MT_BF_TYPE_UPDATE = 20, |
| 539 | MT_BF_MODULE_UPDATE = 25 |
| 540 | }; |
| 541 | |
| 542 | enum { |
| 543 | MURU_SET_ARB_OP_MODE = 14, |
| 544 | MURU_SET_PLATFORM_TYPE = 25, |
| 545 | }; |
| 546 | |
| 547 | enum { |
| 548 | MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1, |
| 549 | MURU_PLATFORM_TYPE_PERF_LEVEL_2, |
| 550 | }; |
| 551 | |
| 552 | /* tx cmd tx statistics */ |
| 553 | enum { |
| 554 | MURU_SET_TXC_TX_STATS_EN = 150, |
| 555 | MURU_GET_TXC_TX_STATS = 151, |
| 556 | }; |
| 557 | |
| 558 | enum { |
| 559 | CMD_BAND_NONE, |
| 560 | CMD_BAND_24G, |
| 561 | CMD_BAND_5G, |
| 562 | CMD_BAND_6G, |
| 563 | }; |
| 564 | |
| 565 | struct bss_req_hdr { |
| 566 | u8 bss_idx; |
| 567 | u8 __rsv[3]; |
| 568 | } __packed; |
| 569 | |
| 570 | enum { |
| 571 | UNI_CHANNEL_SWITCH, |
| 572 | UNI_CHANNEL_RX_PATH, |
| 573 | }; |
| 574 | #define BERSA_BSS_UPDATE_MAX_SIZE (sizeof(struct bss_req_hdr) + \ |
| 575 | sizeof(struct mt76_connac_bss_basic_tlv) + \ |
| 576 | sizeof(struct bss_rlm_tlv) +\ |
| 577 | sizeof(struct bss_ra_tlv) + \ |
| 578 | sizeof(struct bss_info_uni_he) + \ |
| 579 | sizeof(struct bss_rate_tlv) +\ |
| 580 | sizeof(struct bss_txcmd_tlv) +\ |
| 581 | sizeof(struct bss_power_save) +\ |
| 582 | sizeof(struct bss_sec_tlv) +\ |
| 583 | sizeof(struct bss_mld_tlv)) |
| 584 | |
| 585 | #define BERSA_BEACON_UPDATE_SIZE (sizeof(struct bss_req_hdr) + \ |
| 586 | sizeof(struct bss_bcn_content_tlv) + \ |
| 587 | sizeof(struct bss_bcn_cntdwn_tlv) + \ |
| 588 | sizeof(struct bss_bcn_mbss_tlv)) |
| 589 | |
| 590 | enum { |
| 591 | UNI_BAND_CONFIG_RADIO_ENABLE, |
| 592 | UNI_BAND_CONFIG_EDCCA_ENABLE = 0x5, |
| 593 | UNI_BAND_CONFIG_EDCCA_THRESHOLD = 0x6, |
| 594 | UNI_BAND_CONFIG_RTS_THRESHOLD = 0x8, |
| 595 | }; |
| 596 | |
| 597 | enum { |
| 598 | UNI_WSYS_CONFIG_FW_LOG_CTRL, |
| 599 | UNI_WSYS_CONFIG_FW_DBG_CTRL, |
| 600 | }; |
| 601 | |
| 602 | enum { |
| 603 | UNI_RDD_CTRL_PARM, |
| 604 | }; |
| 605 | |
| 606 | enum { |
| 607 | UNI_TXPOWER_SHOW_INFO = 0x7, |
| 608 | }; |
| 609 | |
| 610 | enum { |
| 611 | UNI_EFUSE_ACCESS = 1, |
| 612 | UNI_EFUSE_BUFFER_MODE, |
| 613 | UNI_EFUSE_FREE_BLOCK, |
| 614 | UNI_EFUSE_BUFFER_RD, |
| 615 | }; |
| 616 | |
| 617 | enum { |
| 618 | UNI_VOW_DRR_CTRL, |
| 619 | UNI_VOW_FEATURE_CTRL, |
| 620 | UNI_VOW_BSSGROUP_CTRL_1_GROUP, |
| 621 | UNI_VOW_BSSGROUP_TOKEN_CFG, |
| 622 | UNI_VOW_BSSGROUP_CTRL_ALL_GROUP, |
| 623 | UNI_VOW_BSSGROUP_BW_GROUP_QUANTUM, |
| 624 | UNI_VOW_BSSGROUP_BW_GROUP_QUANTUM_ALL, |
| 625 | UNI_VOW_AT_PROC_EST_FEATURE, |
| 626 | UNI_VOW_AT_PROC_EST_MONITOR_PERIOD, |
| 627 | UNI_VOW_AT_PROC_EST_GROUP_RATIO, |
| 628 | UNI_VOW_AT_PROC_EST_GROUP_TO_BAND_MAPPING, |
| 629 | UNI_VOW_RX_AT_AIRTIME_EN, |
| 630 | UNI_VOW_RX_AT_MIBTIME_EN, |
| 631 | UNI_VOW_RX_AT_EARLYEND_EN, |
| 632 | UNI_VOW_RX_AT_AIRTIME_CLR_EN, |
| 633 | UNI_VOW_RX_AT_STA_WMM_CTRL, |
| 634 | UNI_VOW_RX_AT_MBSS_WMM_CTRL, |
| 635 | UNI_VOW_RX_AT_ED_OFFSET, |
| 636 | UNI_VOW_RX_AT_SW_TIMER, |
| 637 | UNI_VOW_RX_AT_BACKOFF_TIMER, |
| 638 | UNI_VOW_RX_AT_REPORT_RX_NONWIFI_TIME, |
| 639 | UNI_VOW_RX_AT_REPORT_RX_OBSS_TIME, |
| 640 | UNI_VOW_RX_AT_REPORT_MIB_OBSS_TIME, |
| 641 | UNI_VOW_RX_AT_REPORT_PER_STA_RX_TIME, |
| 642 | UNI_VOW_RED_ENABLE, |
| 643 | UNI_VOW_RED_TX_RPT, |
| 644 | }; |
| 645 | |
| 646 | enum { |
| 647 | UNI_CMD_MIB_DATA, |
| 648 | }; |
| 649 | |
| 650 | #endif |