| developer | 472dc5c | 2021-12-16 10:28:37 +0800 | [diff] [blame] | 1 | diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c |
| 2 | index e1ef012..4fd4721 100644 |
| 3 | --- a/drivers/i2c/busses/i2c-mt65xx.c |
| 4 | +++ b/drivers/i2c/busses/i2c-mt65xx.c |
| 5 | @@ -157,7 +157,7 @@ static const u16 mt_i2c_regs_v1[] = { |
| 6 | |
| 7 | static const u16 mt_i2c_regs_v2[] = { |
| 8 | [OFFSET_DATA_PORT] = 0x0, |
| 9 | - [OFFSET_SLAVE_ADDR] = 0x4, |
| 10 | + [OFFSET_SLAVE_ADDR] = 0x94, |
| 11 | [OFFSET_INTR_MASK] = 0x8, |
| 12 | [OFFSET_INTR_STAT] = 0xc, |
| 13 | [OFFSET_CONTROL] = 0x10, |
| 14 | @@ -289,6 +289,18 @@ static const struct mtk_i2c_compatible mt7622_compat = { |
| 15 | .ltiming_adjust = 0, |
| 16 | }; |
| 17 | |
| 18 | +static const struct mtk_i2c_compatible mt7981_compat = { |
| 19 | + .regs = mt_i2c_regs_v2, |
| 20 | + .pmic_i2c = 0, |
| 21 | + .dcm = 0, |
| 22 | + .auto_restart = 1, |
| 23 | + .aux_len_reg = 1, |
| 24 | + .support_33bits = 1, |
| 25 | + .timing_adjust = 1, |
| 26 | + .dma_sync = 1, |
| 27 | + .ltiming_adjust = 1, |
| 28 | +}; |
| 29 | + |
| 30 | static const struct mtk_i2c_compatible mt7986_compat = { |
| 31 | .quirks = &mt7622_i2c_quirks, |
| 32 | .regs = mt_i2c_regs_v1, |
| 33 | @@ -332,6 +344,7 @@ static const struct of_device_id mtk_i2c_of_match[] = { |
| 34 | { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, |
| 35 | { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, |
| 36 | { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, |
| 37 | + { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat }, |
| 38 | { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, |
| 39 | { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, |
| 40 | { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, |
| 41 | -- |
| 42 | 2.18.0 |
| 43 | |