| developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h |
| 2 | index c3d6756..d84c45d 100644 |
| 3 | --- a/drivers/clk/mediatek/clk-mtk.h |
| 4 | +++ b/drivers/clk/mediatek/clk-mtk.h |
| 5 | @@ -231,6 +231,7 @@ struct mtk_pll_data { |
| 6 | uint32_t pcw_reg; |
| 7 | int pcw_shift; |
| 8 | uint32_t pcw_chg_reg; |
| 9 | + int pcw_chg_shift; |
| 10 | const struct mtk_pll_div_table *div_table; |
| 11 | const char *parent_name; |
| 12 | }; |
| 13 | diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c |
| 14 | index f440f2c..db318fe 100644 |
| 15 | --- a/drivers/clk/mediatek/clk-pll.c |
| 16 | +++ b/drivers/clk/mediatek/clk-pll.c |
| 17 | @@ -136,7 +136,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, |
| 18 | pll->data->pcw_shift); |
| 19 | val |= pcw << pll->data->pcw_shift; |
| 20 | writel(val, pll->pcw_addr); |
| 21 | - chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; |
| 22 | + if (pll->data->pcw_chg_shift) |
| 23 | + chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift); |
| 24 | + else |
| 25 | + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; |
| 26 | writel(chg, pll->pcw_chg_addr); |
| 27 | if (pll->tuner_addr) |
| 28 | writel(val + 1, pll->tuner_addr); |