| developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright (c) 2022 MediaTek Inc. |
| 4 | * Author: Henry Yen <henry.yen@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef MTK_ETH_RESET_H |
| 8 | #define MTK_ETH_RESET_H |
| 9 | |
| 10 | /* Frame Engine Reset FSM */ |
| 11 | #define MTK_FE_START_RESET 0x2000 |
| 12 | #define MTK_FE_RESET_DONE 0x2001 |
| 13 | #define MTK_WIFI_RESET_DONE 0x2002 |
| developer | be97172 | 2022-05-23 13:51:05 +0800 | [diff] [blame] | 14 | #define MTK_WIFI_CHIP_ONLINE 0x2003 |
| 15 | #define MTK_WIFI_CHIP_OFFLINE 0x2004 |
| developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 16 | #define MTK_FE_RESET_NAT_DONE 0x4001 |
| 17 | |
| developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 18 | #define MTK_FE_STOP_TRAFFIC (0x2005) |
| 19 | #define MTK_FE_STOP_TRAFFIC_DONE (0x2006) |
| 20 | #define MTK_FE_START_TRAFFIC (0x2007) |
| 21 | |
| developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 22 | /* ADMA Rx Debug Monitor */ |
| 23 | #define MTK_ADMA_RX_DBG0 (PDMA_BASE + 0x238) |
| 24 | #define MTK_ADMA_RX_DBG1 (PDMA_BASE + 0x23C) |
| 25 | |
| 26 | /* PPE Configurations */ |
| 27 | #define MTK_PPE_GLO_CFG(x) (PPE_BASE(x) + 0x00) |
| 28 | #define MTK_PPE_TB_CFG(x) (PPE_BASE(x) + 0x1C) |
| 29 | #define MTK_PPE_BIND_LMT_1(x) (PPE_BASE(x) + 0x30) |
| 30 | #define MTK_PPE_KA(x) (PPE_BASE(x) + 0x34) |
| 31 | #define MTK_PPE_KA_CFG_MASK (0x3 << 12) |
| 32 | #define MTK_PPE_NTU_KA_MASK (0xFF << 16) |
| 33 | #define MTK_PPE_KA_T_MASK (0xFFFF << 0) |
| 34 | #define MTK_PPE_TCP_KA_MASK (0xFF << 16) |
| 35 | #define MTK_PPE_UDP_KA_MASK (0xFF << 24) |
| 36 | #define MTK_PPE_TICK_SEL_MASK (0x1 << 24) |
| 37 | #define MTK_PPE_SCAN_MODE_MASK (0x3 << 16) |
| 38 | #define MTK_PPE_BUSY BIT(31) |
| 39 | |
| developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 40 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 41 | #define MTK_WDMA_CNT (0x3) |
| 42 | #else |
| 43 | #define MTK_WDMA_CNT (0x2) |
| 44 | #endif |
| 45 | |
| developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 46 | enum mtk_reset_type { |
| 47 | MTK_TYPE_COLD_RESET = 0, |
| 48 | MTK_TYPE_WARM_RESET, |
| 49 | }; |
| 50 | |
| 51 | enum mtk_reset_event_id { |
| 52 | MTK_EVENT_FORCE = 0, |
| 53 | MTK_EVENT_WARM_CNT = 1, |
| 54 | MTK_EVENT_COLD_CNT = 2, |
| 55 | MTK_EVENT_TOTAL_CNT = 3, |
| 56 | MTK_EVENT_FQ_EMPTY = 8, |
| 57 | MTK_EVENT_TSO_FAIL = 12, |
| 58 | MTK_EVENT_TSO_ILLEGAL = 13, |
| 59 | MTK_EVENT_TSO_ALIGN = 14, |
| 60 | MTK_EVENT_RFIFO_OV = 18, |
| 61 | MTK_EVENT_RFIFO_UF = 19, |
| 62 | }; |
| 63 | |
| 64 | extern struct notifier_block mtk_eth_netdevice_nb __read_mostly; |
| 65 | extern struct completion wait_ser_done; |
| 66 | extern char* mtk_reset_event_name[32]; |
| 67 | extern atomic_t reset_lock; |
| developer | 37482a4 | 2022-12-26 13:31:13 +0800 | [diff] [blame] | 68 | extern struct completion wait_nat_done; |
| 69 | extern u32 mtk_reset_flag; |
| developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 70 | |
| 71 | irqreturn_t mtk_handle_fe_irq(int irq, void *_eth); |
| 72 | u32 mtk_check_reset_event(struct mtk_eth *eth, u32 status); |
| 73 | int mtk_eth_cold_reset(struct mtk_eth *eth); |
| 74 | int mtk_eth_warm_reset(struct mtk_eth *eth); |
| 75 | void mtk_reset_event_update(struct mtk_eth *eth, u32 id); |
| 76 | void mtk_dump_netsys_info(void *_eth); |
| 77 | void mtk_dma_monitor(struct timer_list *t); |
| 78 | void mtk_prepare_reset_fe(struct mtk_eth *eth); |
| 79 | void mtk_prepare_reset_ppe(struct mtk_eth *eth, u32 ppe_id); |
| 80 | |
| 81 | #endif /* MTK_ETH_RESET_H */ |