blob: 96deb54c9187179a4c4b0ffdc78e1188d42c4024 [file] [log] [blame]
developer4f0d2ba2023-08-21 17:33:25 +08001--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
2+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
developerdca80e32023-10-19 16:24:46 +08003@@ -1840,6 +1840,11 @@ static void mtk_tx_set_dma_desc_v3(struc
4 trace_printk("[%s] skb_shinfo(skb)->nr_frags=%x HNAT_SKB_CB2(skb)->magic=%x txd4=%x<-----\n",
5 __func__, skb_shinfo(skb)->nr_frags, HNAT_SKB_CB2(skb)->magic, data);
6 #endif
7+ /* forward to eip197 if this packet is going to encrypt */
8+ if (unlikely(skb_hnat_cdrt(skb) && is_magic_tag_valid(skb))) {
9+ data &= ((~TX_DMA_TPORT_MASK) << TX_DMA_TPORT_SHIFT);
10+ data |= (EIP197_QDMA_TPORT & TX_DMA_TPORT_MASK) << TX_DMA_TPORT_SHIFT;
11+ }
12 WRITE_ONCE(desc->txd4, data);
13
14 data = 0;
15@@ -1862,6 +1867,14 @@ static void mtk_tx_set_dma_desc_v3(struc
16
17 WRITE_ONCE(desc->txd7, 0);
18 WRITE_ONCE(desc->txd8, 0);
19+ if (unlikely(skb_hnat_cdrt(skb) && is_magic_tag_valid(skb))) {
20+ /* carry cdrt index for encryption */
21+ data = (skb_hnat_cdrt(skb) & TX_DMA_CDRT_MASK) << TX_DMA_CDRT_SHIFT;
22+ WRITE_ONCE(desc->txd8, data);
23+ skb_hnat_magic_tag(skb) = 0;
24+ } else {
25+ WRITE_ONCE(desc->txd8, 0);
26+ }
27 }
28
29 static void mtk_tx_set_dma_desc(struct sk_buff *skb, struct net_device *dev, void *txd,
30@@ -2331,6 +2344,7 @@ static int mtk_poll_rx(struct napi_struc
developer4f0d2ba2023-08-21 17:33:25 +080031
32 skb_hnat_alg(skb) = 0;
33 skb_hnat_filled(skb) = 0;
34+ skb_hnat_set_cdrt(skb, 0);
35 skb_hnat_magic_tag(skb) = HNAT_MAGIC_TAG;
36 skb_hnat_set_tops(skb, 0);
37 skb_hnat_set_is_decap(skb, 0);
38--- a/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c
39+++ b/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c
developer84f378f2023-08-24 18:26:50 +080040@@ -1076,6 +1076,9 @@ static unsigned int hnat_ipv4_get_nextho
developer4f0d2ba2023-08-21 17:33:25 +080041 return 0;
42 }
43
44+ if (!skb_hnat_cdrt(skb) && dst && dst_xfrm(dst))
45+ return 0;
46+
47 rcu_read_lock_bh();
48 nexthop = (__force u32)rt_nexthop(rt, ip_hdr(skb)->daddr);
49 neigh = __ipv4_neigh_lookup_noref(dev, nexthop);
developer84f378f2023-08-24 18:26:50 +080050@@ -1299,6 +1302,9 @@ static inline void hnat_fill_offload_eng
developer4f0d2ba2023-08-21 17:33:25 +080051 */
52 entry->ipv4_hnapt.tport_id = NR_TDMA_QDMA_TPORT;
53 entry->ipv4_hnapt.tops_entry = skb_hnat_tops(skb);
54+ } else if (skb_hnat_cdrt(skb)) {
55+ entry->ipv4_hnapt.tport_id = NR_EIP197_QDMA_TPORT;
56+ entry->ipv4_hnapt.cdrt_id = skb_hnat_cdrt(skb);
57 } else {
58 return;
59 }
developerdca80e32023-10-19 16:24:46 +080060@@ -1308,6 +1314,75 @@ static inline void hnat_fill_offload_eng
61 #endif /* defined(CONFIG_MEDIATEK_NETSYS_V3) */
62 }
developer4f0d2ba2023-08-21 17:33:25 +080063
developerdca80e32023-10-19 16:24:46 +080064+int hnat_bind_crypto_entry(struct sk_buff *skb, const struct net_device *dev) {
65+ struct foe_entry *foe;
66+ struct foe_entry entry = { 0 };
67+ struct ethhdr *eth = eth_hdr(skb);
68+ u32 gmac = NR_DISCARD;
69+
70+ if (skb_hnat_tops(skb) && mtk_tnl_encap_offload)
71+ mtk_tnl_encap_offload(skb);
72+
73+ foe = &hnat_priv->foe_table_cpu[skb_hnat_ppe(skb)][skb_hnat_entry(skb)];
74+
75+ hnat_get_filled_unbind_entry(skb, &entry);
76+ entry.bfib1.cah = 1;
77+ entry.bfib1.time_stamp = (hnat_priv->data->version == MTK_HNAT_V2 ||
78+ hnat_priv->data->version == MTK_HNAT_V3) ?
79+ readl(hnat_priv->fe_base + 0x0010) & (0xFF) :
80+ readl(hnat_priv->fe_base + 0x0010) & (0x7FFF);
81+ entry.ipv4_hnapt.iblk2.port_ag =
82+ (hnat_priv->data->version == MTK_HNAT_V2 ||
83+ hnat_priv->data->version == MTK_HNAT_V3) ? 0xf : 0x3f;
84+
85+ if (IS_LAN(dev)) {
86+ if (IS_BOND_MODE)
87+ gmac = ((skb_hnat_entry(skb) >> 1) % hnat_priv->gmac_num) ?
88+ NR_GMAC2_PORT : NR_GMAC1_PORT;
89+ else
90+ gmac = NR_GMAC1_PORT;
91+ } else if (IS_LAN2(dev)) {
92+ gmac = NR_GMAC2_PORT;
93+ } else if (IS_WAN(dev)) {
94+ gmac = (IS_GMAC1_MODE) ? NR_GMAC1_PORT : NR_GMAC2_PORT;
95+ } else {
96+ pr_notice("Unknown case of dp, iif=%x --> %s\n", skb_hnat_iface(skb), dev->name);
97+ return -1;
98+ }
99+
100+ entry.ipv4_hnapt.iblk2.mibf = 1;
101+ entry.ipv4_hnapt.iblk2.dp = gmac;
102+ entry.ipv4_hnapt.iblk2.port_mg =
103+ (hnat_priv->data->version == MTK_HNAT_V1_1) ? 0x3f : 0;
104+ entry.bfib1.ttl = 1;
105+ entry.bfib1.state = BIND;
106+
107+ hnat_fill_offload_engine_entry(skb, &entry, dev);
108+
109+ if (!skb_hnat_tops(skb)) {
110+ entry.ipv4_hnapt.dmac_hi = swab32(*((u32 *)eth->h_dest));
111+ entry.ipv4_hnapt.dmac_lo = swab16(*((u16 *)&eth->h_dest[4]));
112+ entry.ipv4_hnapt.smac_hi = swab32(*((u32 *)eth->h_source));
113+ entry.ipv4_hnapt.smac_lo = swab16(*((u16 *)&eth->h_source[4]));
114+ }
115+
116+ wmb();
117+
118+ if (entry_hnat_is_bound(foe))
119+ return 0;
120+
121+ memcpy(foe, &entry, sizeof(entry));
122+
123+ if (hnat_priv->data->per_flow_accounting &&
124+ skb_hnat_entry(skb) < hnat_priv->foe_etry_num &&
125+ skb_hnat_ppe(skb) < CFG_PPE_NUM)
126+ memset(&hnat_priv->acct[skb_hnat_ppe(skb)][skb_hnat_entry(skb)],
127+ 0, sizeof(struct mib_entry));
128+
129+ return 0;
130+}
131+EXPORT_SYMBOL(hnat_bind_crypto_entry);
132+
133 static unsigned int skb_to_hnat_info(struct sk_buff *skb,
134 const struct net_device *dev,
135 struct foe_entry *foe,
136@@ -2364,6 +2439,7 @@ int mtk_sw_nat_hook_rx(struct sk_buff *s
developer4f0d2ba2023-08-21 17:33:25 +0800137
138 skb_hnat_alg(skb) = 0;
139 skb_hnat_set_tops(skb, 0);
140+ skb_hnat_set_cdrt(skb, 0);
141 skb_hnat_magic_tag(skb) = HNAT_MAGIC_TAG;
142
143 if (skb_hnat_iface(skb) == FOE_MAGIC_WED0)
developerdca80e32023-10-19 16:24:46 +0800144@@ -2450,7 +2526,8 @@ static unsigned int mtk_hnat_accel_type(
developer4f0d2ba2023-08-21 17:33:25 +0800145 * is from local_out which is also filtered in sanity check.
146 */
147 dst = skb_dst(skb);
148- if (dst && dst_xfrm(dst))
149+ if (dst && dst_xfrm(dst)
150+ && (!mtk_crypto_offloadable || !mtk_crypto_offloadable(skb)))
151 return 0;
152
153 ct = nf_ct_get(skb, &ctinfo);
developerdca80e32023-10-19 16:24:46 +0800154@@ -2847,6 +2924,14 @@ static unsigned int mtk_hnat_nf_post_rou
developer5c851032023-09-04 11:13:18 +0800155 }
156 }
157
158+ /* we are not support protocols other than IPv4 TCP for crypto offload yet */
159+ if (skb_hnat_is_decrypt(skb)
160+ && (ntohs(skb->protocol) != ETH_P_IP
161+ || ip_hdr(skb)->protocol != IPPROTO_TCP)) {
162+ skb_hnat_alg(skb) = 1;
163+ return 0;
164+ }
165+
166 if (!IS_LAN_GRP(out) && !IS_WAN(out) && !IS_EXT(out))
167 is_virt_dev = true;
168
developerdca80e32023-10-19 16:24:46 +0800169@@ -3157,7 +3242,10 @@ mtk_hnat_ipv4_nf_local_out(void *priv, s
developer4f0d2ba2023-08-21 17:33:25 +0800170 if (iph->protocol == IPPROTO_IPV6) {
171 entry->udib1.pkt_type = IPV6_6RD;
172 hnat_set_head_frags(state, skb, 0, hnat_set_alg);
173- } else if (!skb_hnat_tops(skb)) {
174+ } else if (is_magic_tag_valid(skb)
175+ && (skb_hnat_cdrt(skb) || skb_hnat_tops(skb))) {
176+ hnat_set_head_frags(state, skb, 0, hnat_set_alg);
177+ } else {
178 hnat_set_head_frags(state, skb, 1, hnat_set_alg);
179 }
180
181--- a/drivers/net/ethernet/mediatek/mtk_hnat/nf_hnat_mtk.h
182+++ b/drivers/net/ethernet/mediatek/mtk_hnat/nf_hnat_mtk.h
183@@ -46,7 +46,8 @@ struct hnat_desc {
184 u32 amsdu : 1;
185 u32 tops : 6;
186 u32 is_decap : 1;
187- u32 resv3 : 12;
188+ u32 cdrt : 8;
189+ u32 resv3 : 4;
190 u32 magic_tag_protect : 16;
191 } __packed;
192 #elif defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
193@@ -99,12 +100,16 @@ struct hnat_desc {
194 #define skb_hnat_is_encap(skb) (!skb_hnat_is_decap(skb))
195 #define skb_hnat_set_tops(skb, tops) ((skb_hnat_tops(skb)) = (tops))
196 #define skb_hnat_set_is_decap(skb, is_decap) ((skb_hnat_is_decap(skb)) = (is_decap))
197+#define skb_hnat_cdrt(skb) (((struct hnat_desc *)((skb)->head))->cdrt)
198+#define skb_hnat_set_cdrt(skb, cdrt) ((skb_hnat_cdrt(skb)) = (cdrt))
199 #else /* !defined(CONFIG_MEDIATEK_NETSYS_V3) */
200 #define skb_hnat_tops(skb) (0)
201 #define skb_hnat_is_decap(skb) (0)
202 #define skb_hnat_is_encap(skb) (0)
203 #define skb_hnat_set_tops(skb, tops)
204 #define skb_hnat_set_is_decap(skb, is_decap)
205+#define skb_hnat_cdrt(skb) (0)
206+#define skb_hnat_set_cdrt(skb, cdrt)
207 #endif /* defined(CONFIG_MEDIATEK_NETSYS_V3) */
208 #define skb_hnat_magic(skb) (((struct hnat_desc *)(skb->head))->magic)
209 #define skb_hnat_reason(skb) (((struct hnat_desc *)(skb->head))->crsn)
210--- a/drivers/net/ethernet/mediatek/mtk_hnat/hnat.c
211+++ b/drivers/net/ethernet/mediatek/mtk_hnat/hnat.c
212@@ -49,6 +49,8 @@ int (*mtk_tnl_decap_offload)(struct sk_b
213 EXPORT_SYMBOL(mtk_tnl_decap_offload);
214 bool (*mtk_tnl_decap_offloadable)(struct sk_buff *skb) = NULL;
215 EXPORT_SYMBOL(mtk_tnl_decap_offloadable);
216+bool (*mtk_crypto_offloadable)(struct sk_buff *skb) = NULL;
217+EXPORT_SYMBOL(mtk_crypto_offloadable);
218
219 static void hnat_sma_build_entry(struct timer_list *t)
220 {
221--- a/drivers/net/ethernet/mediatek/mtk_hnat/hnat.h
222+++ b/drivers/net/ethernet/mediatek/mtk_hnat/hnat.h
developerdca80e32023-10-19 16:24:46 +0800223@@ -1135,6 +1135,8 @@ enum FoeIpAct {
developer4f0d2ba2023-08-21 17:33:25 +0800224 #define NR_WDMA1_PORT 9
225 #define NR_WDMA2_PORT 13
226 #define NR_GMAC3_PORT 15
227+#define NR_EIP197_TPORT 2
228+#define NR_EIP197_QDMA_TPORT 3
229 #define NR_TDMA_TPORT 4
230 #define NR_TDMA_QDMA_TPORT 5
231 #define LAN_DEV_NAME hnat_priv->lan
developerdca80e32023-10-19 16:24:46 +0800232@@ -1288,6 +1290,8 @@ extern int qos_toggle;
developer4f0d2ba2023-08-21 17:33:25 +0800233 extern int (*mtk_tnl_encap_offload)(struct sk_buff *skb);
234 extern int (*mtk_tnl_decap_offload)(struct sk_buff *skb);
235 extern bool (*mtk_tnl_decap_offloadable)(struct sk_buff *skb);
236+extern bool (*mtk_crypto_offloadable)(struct sk_buff *skb);
developerdca80e32023-10-19 16:24:46 +0800237+extern int hnat_bind_crypto_entry(struct sk_buff *skb, const struct net_device *dev);
developer4f0d2ba2023-08-21 17:33:25 +0800238
239 int ext_if_add(struct extdev_entry *ext_entry);
240 int ext_if_del(struct extdev_entry *ext_entry);
developerdca80e32023-10-19 16:24:46 +0800241--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
242+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
243@@ -551,6 +551,10 @@
244
245 #define MTK_QDMA_GMAC2_QID 8
246
247+/* QDMA V2 descriptor txd8 */
248+#define TX_DMA_CDRT_SHIFT 0
249+#define TX_DMA_CDRT_MASK 0xff
250+
251 /* QDMA V2 descriptor txd6 */
252 #define TX_DMA_INS_VLAN_V2 BIT(16)
253
254@@ -560,6 +564,9 @@
255 #define TX_DMA_SPTAG_V3 BIT(27)
256
257 /* QDMA V2 descriptor txd4 */
258+#define EIP197_QDMA_TPORT 3
259+#define TX_DMA_TPORT_SHIFT 0
260+#define TX_DMA_TPORT_MASK 0xf
261 #define TX_DMA_FPORT_SHIFT_V2 8
262 #define TX_DMA_FPORT_MASK_V2 0xf
263 #define TX_DMA_SWC_V2 BIT(30)