developer | be797a3 | 2021-12-16 16:56:09 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // |
| 3 | // MediaTek ALSA SoC Audio DAI eTDM Control |
| 4 | // |
| 5 | // Copyright (c) 2021 MediaTek Inc. |
| 6 | // Author: Vic Wu <vic.wu@mediatek.com> |
| 7 | |
| 8 | #include <linux/bitops.h> |
| 9 | #include <linux/regmap.h> |
| 10 | #include <sound/pcm_params.h> |
| 11 | #include "mt79xx-afe-clk.h" |
| 12 | #include "mt79xx-afe-common.h" |
| 13 | #include "mt79xx-reg.h" |
| 14 | |
| 15 | enum { |
| 16 | HOPPING_CLK = 0, |
| 17 | APLL_CLK = 1, |
| 18 | }; |
| 19 | |
| 20 | enum { |
| 21 | MTK_DAI_ETDM_FORMAT_I2S = 0, |
| 22 | MTK_DAI_ETDM_FORMAT_DSPA = 4, |
| 23 | MTK_DAI_ETDM_FORMAT_DSPB = 5, |
| 24 | }; |
| 25 | |
| 26 | enum { |
| 27 | ETDM_IN5 = 2, |
| 28 | ETDM_OUT5 = 10, |
| 29 | }; |
| 30 | |
| 31 | enum { |
| 32 | MTK_ETDM_RATE_8K = 0, |
| 33 | MTK_ETDM_RATE_12K = 1, |
| 34 | MTK_ETDM_RATE_16K = 2, |
| 35 | MTK_ETDM_RATE_24K = 3, |
| 36 | MTK_ETDM_RATE_32K = 4, |
| 37 | MTK_ETDM_RATE_48K = 5, |
| 38 | MTK_ETDM_RATE_96K = 7, |
| 39 | MTK_ETDM_RATE_192K = 9, |
| 40 | MTK_ETDM_RATE_11K = 16, |
| 41 | MTK_ETDM_RATE_22K = 17, |
| 42 | MTK_ETDM_RATE_44K = 18, |
| 43 | MTK_ETDM_RATE_88K = 19, |
| 44 | MTK_ETDM_RATE_176K = 20, |
| 45 | }; |
| 46 | |
| 47 | struct mtk_dai_etdm_priv { |
| 48 | bool bck_inv; |
| 49 | bool lrck_inv; |
| 50 | bool slave_mode; |
| 51 | unsigned int format; |
| 52 | }; |
| 53 | |
| 54 | static unsigned int mt79xx_etdm_rate_transform(struct device *dev, |
| 55 | unsigned int rate) |
| 56 | { |
| 57 | switch (rate) { |
| 58 | case 8000: |
| 59 | return MTK_ETDM_RATE_8K; |
| 60 | case 11025: |
| 61 | return MTK_ETDM_RATE_11K; |
| 62 | case 12000: |
| 63 | return MTK_ETDM_RATE_12K; |
| 64 | case 16000: |
| 65 | return MTK_ETDM_RATE_16K; |
| 66 | case 22050: |
| 67 | return MTK_ETDM_RATE_22K; |
| 68 | case 24000: |
| 69 | return MTK_ETDM_RATE_24K; |
| 70 | case 32000: |
| 71 | return MTK_ETDM_RATE_32K; |
| 72 | case 44100: |
| 73 | return MTK_ETDM_RATE_44K; |
| 74 | case 48000: |
| 75 | return MTK_ETDM_RATE_48K; |
| 76 | case 88200: |
| 77 | return MTK_ETDM_RATE_88K; |
| 78 | case 96000: |
| 79 | return MTK_ETDM_RATE_96K; |
| 80 | case 176400: |
| 81 | return MTK_ETDM_RATE_176K; |
| 82 | case 192000: |
| 83 | return MTK_ETDM_RATE_192K; |
| 84 | default: |
| 85 | dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n", |
| 86 | __func__, rate, MTK_ETDM_RATE_48K); |
| 87 | return MTK_ETDM_RATE_48K; |
| 88 | } |
| 89 | } |
| 90 | |
| 91 | static int get_etdm_wlen(unsigned int bitwidth) |
| 92 | { |
| 93 | return bitwidth <= 16 ? 16 : 32; |
| 94 | } |
| 95 | |
| 96 | /* dai component */ |
| 97 | /* interconnection */ |
| 98 | |
| 99 | static const struct snd_kcontrol_new o124_mix[] = { |
| 100 | SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0), |
| 101 | }; |
| 102 | |
| 103 | static const struct snd_kcontrol_new o125_mix[] = { |
| 104 | SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0), |
| 105 | }; |
| 106 | |
| 107 | static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { |
| 108 | |
| 109 | /* DL */ |
| 110 | SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 111 | SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 112 | /* UL */ |
| 113 | SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, |
| 114 | o124_mix, ARRAY_SIZE(o124_mix)), |
| 115 | SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, |
| 116 | o125_mix, ARRAY_SIZE(o125_mix)), |
| 117 | }; |
| 118 | |
| 119 | static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { |
| 120 | {"I150", NULL, "ETDM Capture"}, |
| 121 | {"I151", NULL, "ETDM Capture"}, |
| 122 | {"ETDM Playback", NULL, "O124"}, |
| 123 | {"ETDM Playback", NULL, "O125"}, |
| 124 | {"O124", "I032_Switch", "I032"}, |
| 125 | {"O125", "I033_Switch", "I033"}, |
| 126 | }; |
| 127 | |
| 128 | /* dai ops */ |
| 129 | static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, |
| 130 | struct snd_soc_dai *dai) |
| 131 | { |
| 132 | struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); |
| 133 | |
| 134 | mt79xx_afe_enable_clock(afe); |
| 135 | |
| 136 | regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, |
| 137 | 0); |
| 138 | regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, |
| 139 | 0); |
| 140 | |
| 141 | return 0; |
| 142 | } |
| 143 | |
| 144 | static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, |
| 145 | struct snd_soc_dai *dai) |
| 146 | { |
| 147 | struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); |
| 148 | |
| 149 | regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, |
| 150 | CLK_OUT5_PDN); |
| 151 | regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, |
| 152 | CLK_IN5_PDN); |
| 153 | |
| 154 | mt79xx_afe_disable_clock(afe); |
| 155 | } |
| 156 | |
| 157 | static unsigned int get_etdm_ch_fixup(unsigned int channels) |
| 158 | { |
| 159 | if (channels > 16) |
| 160 | return 24; |
| 161 | else if (channels > 8) |
| 162 | return 16; |
| 163 | else if (channels > 4) |
| 164 | return 8; |
| 165 | else if (channels > 2) |
| 166 | return 4; |
| 167 | else |
| 168 | return 2; |
| 169 | } |
| 170 | |
| 171 | static int mtk_dai_etdm_config(struct mtk_base_afe *afe, |
| 172 | struct snd_pcm_hw_params *params, |
| 173 | struct snd_soc_dai *dai, |
| 174 | int stream) |
| 175 | { |
| 176 | struct mt79xx_afe_private *afe_priv = afe->platform_priv; |
| 177 | struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; |
| 178 | unsigned int rate = params_rate(params); |
| 179 | unsigned int etdm_rate = mt79xx_etdm_rate_transform(afe->dev, rate); |
| 180 | unsigned int afe_rate = mt79xx_afe_rate_transform(afe->dev, rate); |
| 181 | unsigned int channels = params_channels(params); |
| 182 | unsigned int bit_width = params_width(params); |
| 183 | unsigned int wlen = get_etdm_wlen(bit_width); |
| 184 | unsigned int val = 0; |
| 185 | unsigned int mask = 0; |
| 186 | |
| 187 | dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n", |
| 188 | __func__, stream, rate, bit_width); |
| 189 | |
| 190 | /* CON0 */ |
| 191 | mask |= ETDM_BIT_LEN_MASK; |
| 192 | val |= ETDM_BIT_LEN(bit_width); |
| 193 | mask |= ETDM_WRD_LEN_MASK; |
| 194 | val |= ETDM_WRD_LEN(wlen); |
| 195 | mask |= ETDM_FMT_MASK; |
| 196 | val |= ETDM_FMT(etdm_data->format); |
| 197 | mask |= ETDM_CH_NUM_MASK; |
| 198 | val |= ETDM_CH_NUM(get_etdm_ch_fixup(channels)); |
| 199 | mask |= RELATCH_SRC_MASK; |
| 200 | val |= RELATCH_SRC(APLL_CLK); |
| 201 | |
| 202 | switch (stream) { |
| 203 | case SNDRV_PCM_STREAM_PLAYBACK: |
| 204 | /* set ETDM_OUT5_CON0 */ |
| 205 | regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val); |
| 206 | |
| 207 | /* set ETDM_OUT5_CON4 */ |
| 208 | regmap_update_bits(afe->regmap, ETDM_OUT5_CON4, |
| 209 | OUT_RELATCH_MASK, OUT_RELATCH(afe_rate)); |
| 210 | regmap_update_bits(afe->regmap, ETDM_OUT5_CON4, |
| 211 | OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK)); |
| 212 | regmap_update_bits(afe->regmap, ETDM_OUT5_CON4, |
| 213 | OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate)); |
| 214 | |
| 215 | /* set ETDM_OUT5_CON5 */ |
| 216 | regmap_update_bits(afe->regmap, ETDM_OUT5_CON5, |
| 217 | ETDM_CLK_DIV_MASK, ETDM_CLK_DIV); |
| 218 | break; |
| 219 | case SNDRV_PCM_STREAM_CAPTURE: |
| 220 | /* set ETDM_IN5_CON0 */ |
| 221 | regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val); |
| 222 | regmap_update_bits(afe->regmap, ETDM_IN5_CON0, |
| 223 | ETDM_SYNC_MASK, ETDM_SYNC); |
| 224 | |
| 225 | /* set ETDM_IN5_CON2 */ |
| 226 | regmap_update_bits(afe->regmap, ETDM_IN5_CON2, |
| 227 | IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK)); |
| 228 | |
| 229 | /* set ETDM_IN5_CON3 */ |
| 230 | regmap_update_bits(afe->regmap, ETDM_IN5_CON3, |
| 231 | IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate)); |
| 232 | |
| 233 | /* set ETDM_IN5_CON4 */ |
| 234 | regmap_update_bits(afe->regmap, ETDM_IN5_CON4, |
| 235 | IN_RELATCH_MASK, IN_RELATCH(afe_rate)); |
| 236 | break; |
| 237 | default: |
| 238 | break; |
| 239 | } |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, |
| 245 | struct snd_pcm_hw_params *params, |
| 246 | struct snd_soc_dai *dai) |
| 247 | { |
| 248 | struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); |
| 249 | |
| 250 | mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK); |
| 251 | mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE); |
| 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, |
| 257 | struct snd_soc_dai *dai) |
| 258 | { |
| 259 | struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); |
| 260 | |
| 261 | dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); |
| 262 | switch (cmd) { |
| 263 | case SNDRV_PCM_TRIGGER_START: |
| 264 | case SNDRV_PCM_TRIGGER_RESUME: |
| 265 | regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK, |
| 266 | ETDM_EN); |
| 267 | regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK, |
| 268 | ETDM_EN); |
| 269 | break; |
| 270 | case SNDRV_PCM_TRIGGER_STOP: |
| 271 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 272 | regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK, |
| 273 | 0); |
| 274 | regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK, |
| 275 | 0); |
| 276 | break; |
| 277 | default: |
| 278 | break; |
| 279 | } |
| 280 | |
| 281 | return 0; |
| 282 | } |
| 283 | |
| 284 | static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 285 | { |
| 286 | struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); |
| 287 | struct mt79xx_afe_private *afe_priv = afe->platform_priv; |
| 288 | struct mtk_dai_etdm_priv *etdm_data; |
| 289 | void *priv_data; |
| 290 | |
| 291 | switch (dai->id) { |
| 292 | case MT79XX_DAI_ETDM: |
| 293 | break; |
| 294 | default: |
| 295 | dev_warn(afe->dev, "%s(), id %d not support\n", |
| 296 | __func__, dai->id); |
| 297 | return -EINVAL; |
| 298 | } |
| 299 | |
| 300 | priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv), |
| 301 | GFP_KERNEL); |
| 302 | if (!priv_data) |
| 303 | return -ENOMEM; |
| 304 | |
| 305 | afe_priv->dai_priv[dai->id] = priv_data; |
| 306 | etdm_data = afe_priv->dai_priv[dai->id]; |
| 307 | |
| 308 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 309 | case SND_SOC_DAIFMT_I2S: |
| 310 | etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; |
| 311 | break; |
| 312 | case SND_SOC_DAIFMT_DSP_A: |
| 313 | etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; |
| 314 | break; |
| 315 | case SND_SOC_DAIFMT_DSP_B: |
| 316 | etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; |
| 317 | break; |
| 318 | default: |
| 319 | return -EINVAL; |
| 320 | } |
| 321 | |
| 322 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 323 | case SND_SOC_DAIFMT_NB_NF: |
| 324 | etdm_data->bck_inv = false; |
| 325 | etdm_data->lrck_inv = false; |
| 326 | break; |
| 327 | case SND_SOC_DAIFMT_NB_IF: |
| 328 | etdm_data->bck_inv = false; |
| 329 | etdm_data->lrck_inv = true; |
| 330 | break; |
| 331 | case SND_SOC_DAIFMT_IB_NF: |
| 332 | etdm_data->bck_inv = true; |
| 333 | etdm_data->lrck_inv = false; |
| 334 | break; |
| 335 | case SND_SOC_DAIFMT_IB_IF: |
| 336 | etdm_data->bck_inv = true; |
| 337 | etdm_data->lrck_inv = true; |
| 338 | break; |
| 339 | default: |
| 340 | return -EINVAL; |
| 341 | } |
| 342 | |
| 343 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 344 | case SND_SOC_DAIFMT_CBM_CFM: |
| 345 | etdm_data->slave_mode = true; |
| 346 | break; |
| 347 | case SND_SOC_DAIFMT_CBS_CFS: |
| 348 | etdm_data->slave_mode = false; |
| 349 | break; |
| 350 | default: |
| 351 | return -EINVAL; |
| 352 | } |
| 353 | |
| 354 | return 0; |
| 355 | } |
| 356 | |
| 357 | static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { |
| 358 | .startup = mtk_dai_etdm_startup, |
| 359 | .shutdown = mtk_dai_etdm_shutdown, |
| 360 | .hw_params = mtk_dai_etdm_hw_params, |
| 361 | .trigger = mtk_dai_etdm_trigger, |
| 362 | .set_fmt = mtk_dai_etdm_set_fmt, |
| 363 | }; |
| 364 | |
| 365 | /* dai driver */ |
| 366 | #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\ |
| 367 | SNDRV_PCM_RATE_88200 |\ |
| 368 | SNDRV_PCM_RATE_96000 |\ |
| 369 | SNDRV_PCM_RATE_176400 |\ |
| 370 | SNDRV_PCM_RATE_192000) |
| 371 | |
| 372 | #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 373 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 374 | SNDRV_PCM_FMTBIT_S32_LE) |
| 375 | |
| 376 | static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { |
| 377 | { |
| 378 | .name = "ETDM", |
| 379 | .id = MT79XX_DAI_ETDM, |
| 380 | .capture = { |
| 381 | .stream_name = "ETDM Capture", |
| 382 | .channels_min = 1, |
| 383 | .channels_max = 2, |
| 384 | .rates = MTK_ETDM_RATES, |
| 385 | .formats = MTK_ETDM_FORMATS, |
| 386 | }, |
| 387 | .playback = { |
| 388 | .stream_name = "ETDM Playback", |
| 389 | .channels_min = 1, |
| 390 | .channels_max = 2, |
| 391 | .rates = MTK_ETDM_RATES, |
| 392 | .formats = MTK_ETDM_FORMATS, |
| 393 | }, |
| 394 | .ops = &mtk_dai_etdm_ops, |
| 395 | .symmetric_rates = 1, |
| 396 | .symmetric_samplebits = 1, |
| 397 | }, |
| 398 | }; |
| 399 | |
| 400 | int mt79xx_dai_etdm_register(struct mtk_base_afe *afe) |
| 401 | { |
| 402 | struct mtk_base_afe_dai *dai; |
| 403 | |
| 404 | dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); |
| 405 | if (!dai) |
| 406 | return -ENOMEM; |
| 407 | |
| 408 | list_add(&dai->list, &afe->sub_dais); |
| 409 | |
| 410 | dai->dai_drivers = mtk_dai_etdm_driver; |
| 411 | dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); |
| 412 | |
| 413 | dai->dapm_widgets = mtk_dai_etdm_widgets; |
| 414 | dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); |
| 415 | dai->dapm_routes = mtk_dai_etdm_routes; |
| 416 | dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); |
| 417 | |
| 418 | return 0; |
| 419 | } |