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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / d8a2975939a12686c4a95c40db21efdc3f821f63 / . / target / linux / mediatek / files-5.4 / drivers / pinctrl / mediatek / pinctrl-mt7981.c
blob: 279ca6ec9ca54e49073b96ba572cce2241242ced [file] [log] [blame]
developer6747cdd2021-09-29 17:00:51 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * The MT7986 driver based on Linux generic pinctrl binding.
4 *
5 * Copyright (C) 2020 MediaTek Inc.
6 * Author: Sam Shih <sam.shih@mediatek.com>
7 */
8
9#include "pinctrl-moore.h"
10
11#define MT7986_PIN(_number, _name) \
12 MTK_PIN(_number, _name, 0, _number, DRV_GRP1)
13
14#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
15 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
16 _x_bits, 32, 0)
17
18#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
19 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
20 _x_bits, 32, 1)
21
22static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
23 PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
24};
25
26static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
27 PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
28};
29
30static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
31 PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
32};
33
34static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
35 PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
36};
37
38static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
39 PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
40 PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
41 PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
42 PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
43 PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
44 PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
45 PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
46 PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
47 PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
48 PIN_FIELD_BASE(9, 9, 4, 0x20, 0x10, 9, 1),
49
50 PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
51 PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
52 PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
53 PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
54
55 PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
56
57 PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
58 PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
59 PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
60 PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
61 PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
62 PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
63 PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
64 PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
65 PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
66 PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
67 PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
68
69 PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
70 PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
71 PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
72 PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
73 PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
74 PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
75
76 PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
77 PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
78
79 PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
80 PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
81
82 PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
83 PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
84 PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
85 PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
86
87 PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
88 PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
89 PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
90 PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
91 PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
92 PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
93 PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
94 PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
95 PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
96 PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
97
98 PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
99 PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
100 PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
101 PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
102 PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
103 PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
104 PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
105};
106
107static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
108 PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
109 PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
110 PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
111 PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
112 PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
113 PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
114 PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
115 PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
116 PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
117 PIN_FIELD_BASE(9, 9, 4, 0x80, 0x10, 9, 1),
118
119 PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
120 PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
121 PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
122 PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
123
124 PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
125
126 PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
127 PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
128 PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
129 PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
130 PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
131 PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
132 PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
133 PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
134 PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
135 PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
136 PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
137
138 PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
139 PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
140 PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
141 PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
142 PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
143 PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
144
145 PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
146 PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
147
148 PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
149 PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
150
151 PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
152 PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
153 PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
154 PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
155
156 PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
157 PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
158 PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
159 PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
160 PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
161 PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
162 PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
163 PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
164 PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
165 PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
166
167 PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
168 PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
169 PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
170 PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
171 PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
172 PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
173 PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
174};
175
176static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
177 PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
178 PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
179 PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
180 PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
181 PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
182 PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
183 PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
184 PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
185 PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
186 PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
187
188 PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
189 PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
190 PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
191 PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
192 PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
193 PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
194 PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
195};
196
197static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
198 PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
199 PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
200 PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
201 PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
202 PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
203 PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
204 PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
205 PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
206 PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
207 PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
208
209 PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
210 PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
211 PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
212 PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
213 PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
214 PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
215 PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
216};
217
218static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
219 PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
220 PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
221
222 PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
223
224 PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
225 PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
226 PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
227 PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
228 PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
229 PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
230 PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 27, 3),
231
232 PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
233 PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
234 PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
235 PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
236
237 PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
238
239 PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
240 PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
241 PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
242 PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
243 PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
244 PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
245 PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
246 PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
247 PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
248 PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
249 PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
250
251 PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
252 PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
253 PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
254 PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
255 PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
256 PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
257
258 PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
259 PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
260
261 PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
262 PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
263
264 PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
265 PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
266 PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
267 PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
268
269 PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
270 PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
271 PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
272 PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
273 PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
274 PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
275 PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
276 PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
277 PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
278 PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
279
280 PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
281 PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
282 PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
283 PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
284 PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
285 PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
286 PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
287};
288
289static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
290 PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
291 PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
292 PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
293 PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
294 PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
295 PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
296 PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
297 PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
298 PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
299 PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 9, 1),
300
301 PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
302 PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
303 PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
304 PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
305
306 PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
307
308 PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
309 PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
310 PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
311 PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
312 PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
313 PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
314 PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
315 PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
316 PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
317 PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
318 PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
319
320 PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
321 PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
322 PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
323 PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
324 PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
325 PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
326
327 PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
328 PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
329
330 PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
331 PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
332
333 PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
334 PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
335 PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
336 PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
337};
338
339static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
340 PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
341 PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
342 PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
343 PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
344 PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
345 PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
346 PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
347 PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
348 PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
349 PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 9, 1),
350
351 PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
352 PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
353 PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
354 PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
355
356 PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
357
358 PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
359 PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
360 PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
361 PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
362 PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
363 PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
364 PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
365 PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
366 PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
367 PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
368 PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
369
370 PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
371 PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
372 PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
373 PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
374 PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
375 PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
376
377 PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
378 PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
379
380 PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
381 PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
382
383 PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
384 PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
385 PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
386 PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
387};
388
389static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
390 PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
391 PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
392 PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
393 PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
394 PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
395 PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
396 PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
397 PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
398 PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
399 PIN_FIELD_BASE(9, 9, 4, 0x50, 0x10, 9, 1),
400
401 PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
402 PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
403 PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
404 PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
405
406 PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
407
408 PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
409 PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
410 PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
411 PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
412 PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
413 PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
414 PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
415 PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
416 PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
417 PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
418 PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
419
420 PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
421 PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
422 PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
423 PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
424 PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
425 PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
426
427 PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
428 PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
429
430 PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
431 PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
432
433 PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
434 PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
435 PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
436 PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
437};
438
439static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
440 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
441 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
442 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
443 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
444 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
445 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
446 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
447 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
448 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
449 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
450 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
451 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
452};
453
454static const struct mtk_pin_desc mt7981_pins[] = {
455 MT7986_PIN(0, "GPIO_WPS"),
456 MT7986_PIN(1, "GPIO_RESET"),
457 MT7986_PIN(2, "SYS_WATCHDOG"),
458 MT7986_PIN(3, "PCIE_PERESET_N"),
459 MT7986_PIN(4, "JTAG_JTDO"),
460 MT7986_PIN(5, "JTAG_JTDI"),
461 MT7986_PIN(6, "JTAG_JTMS"),
462 MT7986_PIN(7, "JTAG_JTCLK"),
463 MT7986_PIN(8, "JTAG_JTRST_N"),
464 MT7986_PIN(9, "WO_JTAG_JTDO"),
465 MT7986_PIN(10, "WO_JTAG_JTDI"),
466 MT7986_PIN(11, "WO_JTAG_JTMS"),
467 MT7986_PIN(12, "WO_JTAG_JTCLK"),
468 MT7986_PIN(13, "WO_JTAG_JTRST_N"),
469 MT7986_PIN(14, "USB_VBUS"),
470 MT7986_PIN(15, "PWM0"),
471 MT7986_PIN(16, "SPI0_CLK"),
472 MT7986_PIN(17, "SPI0_MOSI"),
473 MT7986_PIN(18, "SPI0_MISO"),
474 MT7986_PIN(19, "SPI0_CS"),
475 MT7986_PIN(20, "SPI0_HOLD"),
476 MT7986_PIN(21, "SPI0_WP"),
477 MT7986_PIN(22, "SPI1_CLK"),
478 MT7986_PIN(23, "SPI1_MOSI"),
479 MT7986_PIN(24, "SPI1_MISO"),
480 MT7986_PIN(25, "SPI1_CS"),
481 MT7986_PIN(26, "SPI2_CLK"),
482 MT7986_PIN(27, "SPI2_MOSI"),
483 MT7986_PIN(28, "SPI2_MISO"),
484 MT7986_PIN(29, "SPI2_CS"),
485 MT7986_PIN(30, "SPI2_HOLD"),
486 MT7986_PIN(31, "SPI2_WP"),
487 MT7986_PIN(32, "UART0_RXD"),
488 MT7986_PIN(33, "UART0_TXD"),
489 MT7986_PIN(34, "PCIE_CLK_REQ"),
490 MT7986_PIN(35, "PCIE_WAKE_N"),
491 MT7986_PIN(36, "SMI_MDC"),
492 MT7986_PIN(37, "SMI_MDIO"),
493 MT7986_PIN(38, "GBE_INT"),
494 MT7986_PIN(39, "GBE_RESET"),
495 MT7986_PIN(40, "WF_DIG_RESETB"),
496 MT7986_PIN(41, "WF_CBA_RESETB"),
497 MT7986_PIN(42, "WF_XO_REQ"),
498 MT7986_PIN(43, "WF_TOP_CLK"),
499 MT7986_PIN(44, "WF_TOP_DATA"),
500 MT7986_PIN(45, "WF_HB1"),
501 MT7986_PIN(46, "WF_HB2"),
502 MT7986_PIN(47, "WF_HB3"),
503 MT7986_PIN(48, "WF_HB4"),
504 MT7986_PIN(49, "WF_HB0"),
505 MT7986_PIN(50, "WF_HB0_B"),
506 MT7986_PIN(51, "WF_HB5"),
507 MT7986_PIN(52, "WF_HB6"),
508 MT7986_PIN(53, "WF_HB7"),
509 MT7986_PIN(54, "WF_HB8"),
510 MT7986_PIN(55, "WF_HB9"),
511 MT7986_PIN(56, "WF_HB10"),
512};
513
514/* List all groups consisting of these pins dedicated to the enablement of
515 * certain hardware block and the corresponding mode for all of the pins.
516 * The hardware probably has multiple combinations of these pinouts.
517 */
518
519/* WA_AICE */
520static int mt7981_wa_aice1_pins[] = { 0, 1, };
521static int mt7981_wa_aice1_funcs[] = { 2, 2, };
522
523static int mt7981_wa_aice2_pins[] = { 0, 1, };
524static int mt7981_wa_aice2_funcs[] = { 3, 3, };
525
526static int mt7981_wa_aice3_pins[] = { 28, 29, };
527static int mt7981_wa_aice3_funcs[] = { 3, 3, };
528
529static int mt7981_wm_aice1_pins[] = { 9, 10, };
530static int mt7981_wm_aice1_funcs[] = { 2, 2, };
531
532static int mt7981_wm_aice2_pins[] = { 30, 31, };
533static int mt7981_wm_aice2_funcs[] = { 5, 5, };
534
535/* WM_UART */
536static int mt7981_wm_uart_0_pins[] = { 0, 1, };
537static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
538
539static int mt7981_wm_uart_1_pins[] = { 20, 21, };
540static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
541
542static int mt7981_wm_uart_2_pins[] = { 30, 31, };
543static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
544
545/* DFD */
546static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
547static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
548
549/* SYS_WATCHDOG */
550static int mt7981_watchdog_pins[] = { 2, };
551static int mt7981_watchdog_funcs[] = { 1, };
552
553static int mt7981_watchdog1_pins[] = { 13, };
554static int mt7981_watchdog1_funcs[] = { 5, };
555
556/* PCIE_PERESET_N */
557static int mt7981_pcie_pereset_pins[] = { 3, };
558static int mt7981_pcie_pereset_funcs[] = { 1, };
559
560/* JTAG */
561static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
562static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
563
564/* WM_JTAG */
565static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
566static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
567
568static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
569static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
570
571/* WO0_JTAG */
572static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
573static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
574
575static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
576static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
577
578/* UART2 */
579static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
580static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
581
582/* GBE_LED0 */
583static int mt7981_gbe_led0_pins[] = { 8, };
584static int mt7981_gbe_led0_funcs[] = { 3, };
585
586/* PTA_EXT */
587static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
588static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
589
590static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
591static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
592
593/* PWM2 */
594static int mt7981_pwm2_pins[] = { 7, };
595static int mt7981_pwm2_funcs[] = { 4, };
596
597/* NET_WO0_UART_TXD */
598static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
599static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
600
601static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
602static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
603
604static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
605static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
606
607/* SPI1 */
608static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
609static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
610
611/* I2C */
612static int mt7981_i2c0_0_pins[] = { 6, 7, };
613static int mt7981_i2c0_0_funcs[] = { 6, 6, };
614
615static int mt7981_i2c0_1_pins[] = { 30, 31, };
616static int mt7981_i2c0_1_funcs[] = { 4, 4, };
617
618static int mt7981_i2c0_2_pins[] = { 36, 37, };
619static int mt7981_i2c0_2_funcs[] = { 2, 2, };
620
621static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
622static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
623
624static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
625static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
626
627static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
628static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
629
630static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
631static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
632
633/* DFD_NTRST */
634static int mt7981_dfd_ntrst_pins[] = { 8, };
635static int mt7981_dfd_ntrst_funcs[] = { 6, };
636
637/* PWM0 */
638static int mt7981_pwm0_0_pins[] = { 13, };
639static int mt7981_pwm0_0_funcs[] = { 2, };
640
641static int mt7981_pwm0_1_pins[] = { 15, };
642static int mt7981_pwm0_1_funcs[] = { 1, };
643
644/* PWM1 */
645static int mt7981_pwm1_0_pins[] = { 14, };
646static int mt7981_pwm1_0_funcs[] = { 2, };
647
648static int mt7981_pwm1_1_pins[] = { 15, };
649static int mt7981_pwm1_1_funcs[] = { 3, };
650
651/* GBE_LED1 */
652static int mt7981_gbe_led1_pins[] = { 13, };
653static int mt7981_gbe_led1_funcs[] = { 3, };
654
655/* PCM */
656static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
657static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
658
659/* UDI */
660static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
661static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
662
663/* DRV_VBUS */
664static int mt7981_drv_vbus_pins[] = { 14, };
665static int mt7981_drv_vbus_funcs[] = { 1, };
666
667/* EMMC */
668static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
669static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
670
671/* SNFI */
672static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
673static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
674
675/* SPI0 */
676static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
677static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
678
679/* SPI0 */
680static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
681static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
682
683/* SPI1 */
684static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
685static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
686
687/* SPI2 */
688static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
689static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
690
691/* SPI2 */
692static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
693static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
694
695/* UART1 */
696static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
697static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
698
699static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
700static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
701
702/* UART2 */
703static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
704static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
705
706/* UART0 */
707static int mt7981_uart0_pins[] = { 32, 33, };
708static int mt7981_uart0_funcs[] = { 1, 1, };
709
710/* PCIE_CLK_REQ */
711static int mt7981_pcie_clk_pins[] = { 34, };
712static int mt7981_pcie_clk_funcs[] = { 2, };
713
714/* PCIE_WAKE_N */
715static int mt7981_pcie_wake_pins[] = { 35, };
716static int mt7981_pcie_wake_funcs[] = { 2, };
717
718/* MDC_MDIO */
719static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
720static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
721
722static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
723static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
724
725/* WF0_MODE1 */
726static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
727static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
728
729/* WF0_MODE3 */
730static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
731static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
732
733/* WF2G_LED */
734static int mt7981_wf2g_led0_pins[] = { 30, };
735static int mt7981_wf2g_led0_funcs[] = { 2, };
736
737static int mt7981_wf2g_led1_pins[] = { 34, };
738static int mt7981_wf2g_led1_funcs[] = { 1, };
739
740/* WF5G_LED */
741static int mt7981_wf5g_led0_pins[] = { 31, };
742static int mt7981_wf5g_led0_funcs[] = { 2, };
743
744static int mt7981_wf5g_led1_pins[] = { 35, };
745static int mt7981_wf5g_led1_funcs[] = { 1, };
746
747/* MT7531_INT */
748static int mt7981_mt7531_int_pins[] = { 38, };
749static int mt7981_mt7531_int_funcs[] = { 1, };
750
751/* ANT_SEL */
752static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
753static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
754
755static const struct group_desc mt7981_groups[] = {
756 /* @GPIO(0,1): WA_AICE(2) */
757 PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
758 /* @GPIO(0,1): WA_AICE(3) */
759 PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
760 /* @GPIO(0,1): WM_UART(5) */
761 PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
762 /* @GPIO(0,1,4,5): DFD(6) */
763 PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
764 /* @GPIO(2): SYS_WATCHDOG(1) */
765 PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
766 /* @GPIO(3): PCIE_PERESET_N(1) */
767 PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
768 /* @GPIO(4,8) JTAG(1) */
769 PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
770 /* @GPIO(4,8) WM_JTAG(2) */
771 PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
772 /* @GPIO(9,13) WO0_JTAG(1) */
773 PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
774 /* @GPIO(4,7) WM_JTAG(3) */
775 PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
776 /* @GPIO(8) GBE_LED0(3) */
777 PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
778 /* @GPIO(4,6) PTA_EXT(4) */
779 PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
780 /* @GPIO(7) PWM2(4) */
781 PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
782 /* @GPIO(8) NET_WO0_UART_TXD(4) */
783 PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
784 /* @GPIO(4,7) SPI1(5) */
785 PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
786 /* @GPIO(6,7) I2C(5) */
787 PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
788 /* @GPIO(0,1,4,5): DFD_NTRST(6) */
789 PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
790 /* @GPIO(9,10): WM_AICE(2) */
791 PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
792 /* @GPIO(13): PWM0(2) */
793 PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
794 /* @GPIO(15): PWM0(1) */
795 PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
796 /* @GPIO(14): PWM1(2) */
797 PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
798 /* @GPIO(15): PWM1(3) */
799 PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
800 /* @GPIO(14) NET_WO0_UART_TXD(3) */
801 PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
802 /* @GPIO(15) NET_WO0_UART_TXD(4) */
803 PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
804 /* @GPIO(13) GBE_LED0(3) */
805 PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
806 /* @GPIO(9,13) PCM(4) */
807 PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
808 /* @GPIO(13): SYS_WATCHDOG1(5) */
809 PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
810 /* @GPIO(9,13) UDI(4) */
811 PINCTRL_PIN_GROUP("udi", mt7981_udi),
812 /* @GPIO(14) DRV_VBUS(1) */
813 PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
814 /* @GPIO(15,25): EMMC(2) */
815 PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
816 /* @GPIO(16,21): SNFI(3) */
817 PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
818 /* @GPIO(16,19): SPI0(1) */
819 PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
820 /* @GPIO(20,21): SPI0(1) */
821 PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
822 /* @GPIO(22,25) SPI1(1) */
823 PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
824 /* @GPIO(26,29): SPI2(1) */
825 PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
826 /* @GPIO(30,31): SPI0(1) */
827 PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
828 /* @GPIO(16,19): UART1(4) */
829 PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
830 /* @GPIO(26,29): UART1(2) */
831 PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
832 /* @GPIO(22,25): UART1(3) */
developere512d662021-11-02 15:41:03 +0800[diff] [blame]833 PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
developer6747cdd2021-09-29 17:00:51 +0800[diff] [blame]834 /* @GPIO(22,24) PTA_EXT(4) */
835 PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
836 /* @GPIO(20,21): WM_UART(4) */
837 PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
838 /* @GPIO(30,31): WM_UART(3) */
839 PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
840 /* @GPIO(20,24) WM_JTAG(5) */
841 PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
842 /* @GPIO(25,29) WO0_JTAG(5) */
843 PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
844 /* @GPIO(28,29): WA_AICE(3) */
845 PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
846 /* @GPIO(30,31): WM_AICE(5) */
847 PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
848 /* @GPIO(30,31): I2C(4) */
849 PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
850 /* @GPIO(30,31): I2C(6) */
851 PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
852 /* @GPIO(32,33): I2C(1) */
853 PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
854 /* @GPIO(32,33): I2C(2) */
855 PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
856 /* @GPIO(32,33): I2C(3) */
857 PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
858 /* @GPIO(32,33): I2C(5) */
859 PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
860 /* @GPIO(34): PCIE_CLK_REQ(2) */
861 PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
862 /* @GPIO(35): PCIE_WAKE_N(2) */
863 PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
864 /* @GPIO(36,37): I2C(2) */
865 PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
866 /* @GPIO(36,37): MDC_MDIO(1) */
867 PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
868 /* @GPIO(36,37): MDC_MDIO(3) */
869 PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
870 /* @GPIO(69,85): WF0_MODE1(1) */
871 PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
872 /* @GPIO(74,80): WF0_MODE3(3) */
873 PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
874 /* @GPIO(30): WF2G_LED(2) */
875 PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
876 /* @GPIO(34): WF2G_LED(1) */
877 PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
878 /* @GPIO(31): WF5G_LED(2) */
879 PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
880 /* @GPIO(35): WF5G_LED(1) */
881 PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
882 /* @GPIO(38): MT7531_INT(1) */
883 PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
884 /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
885 PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
886};
887
888/* Joint those groups owning the same capability in user point of view which
889 * allows that people tend to use through the device tree.
890 */
891static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
892 "wa_aice3", "wm_aice1_2", };
893static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
894 "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
developere512d662021-11-02 15:41:03 +0800[diff] [blame]895 "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
developer6747cdd2021-09-29 17:00:51 +0800[diff] [blame]896static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
897static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
898static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
899static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
900 "wo0_jtag_1", "wm_jtag_1", };
901static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
902 "wf2g_led1", "wf5g_led0", "wf5g_led1", };
903static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
904static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
905 "pwm1_0", "pwm1_1", };
906static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
907 "spi2_wp_hold", };
908static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
909 "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
910static const char *mt7981_pcm_groups[] = { "pcm", };
911static const char *mt7981_udi_groups[] = { "udi", };
912static const char *mt7981_usb_groups[] = { "drv_vbus", };
913static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
914static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
915 "wf0_mode1", "wf0_mode3", "mt7531_int", };
916static const char *mt7981_ant_groups[] = { "ant_sel", };
917
918static const struct function_desc mt7981_functions[] = {
919 {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
920 {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
921 {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
922 {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
923 {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
924 {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
925 {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
926 {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
927 {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
928 {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
929 {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
930 {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
931 {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
932 {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
933 {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
934 {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
935 {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
936};
937
938static const struct mtk_eint_hw mt7981_eint_hw = {
939 .port_mask = 7,
940 .ports = 7,
941 .ap_num = ARRAY_SIZE(mt7981_pins),
942 .db_cnt = 16,
943};
944
945static const char * const mt7981_pinctrl_register_base_names[] = {
946 "gpio_base", "iocfg_rt_base", "iocfg_rm_base", "iocfg_rb_base",
947 "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base",
948};
949
950static struct mtk_pin_soc mt7981_data = {
951 .reg_cal = mt7981_reg_cals,
952 .pins = mt7981_pins,
953 .npins = ARRAY_SIZE(mt7981_pins),
954 .grps = mt7981_groups,
955 .ngrps = ARRAY_SIZE(mt7981_groups),
956 .funcs = mt7981_functions,
957 .nfuncs = ARRAY_SIZE(mt7981_functions),
958 .eint_hw = &mt7981_eint_hw,
959 .gpio_m = 0,
960 .ies_present = false,
961 .base_names = mt7981_pinctrl_register_base_names,
962 .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
963 .bias_disable_set = mtk_pinconf_bias_disable_set,
964 .bias_disable_get = mtk_pinconf_bias_disable_get,
965 .bias_set = mtk_pinconf_bias_set,
966 .bias_get = mtk_pinconf_bias_get,
967 .drive_set = mtk_pinconf_drive_set_rev1,
968 .drive_get = mtk_pinconf_drive_get_rev1,
969 .adv_pull_get = mtk_pinconf_adv_pull_get,
970 .adv_pull_set = mtk_pinconf_adv_pull_set,
971};
972
973static const struct of_device_id mt7981_pinctrl_of_match[] = {
974 { .compatible = "mediatek,mt7981-pinctrl", },
975 {}
976};
977
978static int mt7981_pinctrl_probe(struct platform_device *pdev)
979{
980 return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
981}
982
983static struct platform_driver mt7981_pinctrl_driver = {
984 .driver = {
985 .name = "mt7981-pinctrl",
986 .of_match_table = mt7981_pinctrl_of_match,
987 },
988 .probe = mt7981_pinctrl_probe,
989};
990
991static int __init mt7981_pinctrl_init(void)
992{
993 return platform_driver_register(&mt7981_pinctrl_driver);
994}
995arch_initcall(mt7981_pinctrl_init);