blob: 6524f3e3261131659601009a7b1421df07855114 [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-snfi-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986b RFB";
developerbd0dd0e2022-04-18 18:28:19 +08007 compatible = "mediatek,mt7986b-2500wan-snfi-snand-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16};
17
18&uart0 {
19 status = "okay";
20};
21
22/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
26 status = "disabled";
27};
28
29/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
33 status = "disabled";
34};
35
36&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
53
54 fixed-link {
55 speed = <2500>;
56 full-duplex;
57 pause;
58 };
59 };
60
61 gmac1: mac@1 {
62 compatible = "mediatek,eth-mac";
63 reg = <1>;
64 phy-mode = "2500base-x";
65
66 fixed-link {
67 speed = <2500>;
68 full-duplex;
69 pause;
70 };
71 };
72
73 mdio: mdio-bus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 phy5: phy@5 {
78 compatible = "ethernet-phy-id67c9.de0a";
79 reg = <5>;
80 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +080081 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +080082 reset-deassert-us = <20000>;
83 phy-mode = "2500base-x";
84 };
85
86 phy6: phy@6 {
87 compatible = "ethernet-phy-id67c9.de0a";
88 reg = <6>;
89 phy-mode = "2500base-x";
90 };
91
92 switch@0 {
93 compatible = "mediatek,mt7531";
94 reg = <31>;
95 reset-gpios = <&pio 5 0>;
96
97 ports {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 port@0 {
102 reg = <0>;
103 label = "lan0";
104 };
105
106 port@1 {
107 reg = <1>;
108 label = "lan1";
109 };
110
111 port@2 {
112 reg = <2>;
113 label = "lan2";
114 };
115
116 port@3 {
117 reg = <3>;
118 label = "lan3";
119 };
120
121 port@6 {
122 reg = <6>;
123 label = "cpu";
124 ethernet = <&gmac0>;
125 phy-mode = "2500base-x";
126
127 fixed-link {
128 speed = <2500>;
129 full-duplex;
130 pause;
131 };
132 };
133 };
134 };
135 };
136};
137
138&hnat {
139 mtketh-wan = "eth1";
140 mtketh-lan = "lan";
141 mtketh-max-gmac = <2>;
142 status = "okay";
143};
144
145/* Warning: pins shared with &uart1 */
146&snand {
147 pinctrl-names = "default";
148 pinctrl-0 = <&snfi_pins>;
149 mediatek,quad-spi;
150 status = "okay";
151
152 partitions {
153 compatible = "fixed-partitions";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 };
157};
158
159/* Warning: pins shared with &uart2 */
160&spi1 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&spic_pins>;
163 status = "okay";
164};
165
166&wbsys {
167 mediatek,mtd-eeprom = <&factory 0x0000>;
168 status = "okay";
169};
170
171&pio {
172 snfi_pins: snfi-pins-23-to-28 {
173 mux {
174 function = "flash";
175 groups = "snfi";
176 };
177 conf-clk {
178 pins = "SPI0_CLK";
179 drive-strength = <MTK_DRIVE_8mA>;
180 mediatek,pull-down-adv = <0>; /* bias-disable */
181 };
182 conf-pu {
183 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
184 drive-strength = <MTK_DRIVE_6mA>;
185 mediatek,pull-up-adv = <0>; /* bias-disable */
186 };
187 conf-pd {
188 pins = "SPI0_MOSI", "SPI0_MISO";
189 drive-strength = <MTK_DRIVE_6mA>;
190 mediatek,pull-down-adv = <0>; /* bias-disable */
191 };
192 };
193};