developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* |
| 3 | * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> |
| 4 | * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/kernel.h> |
| 8 | #include <linux/irq.h> |
| 9 | |
| 10 | #include "mt76x02.h" |
| 11 | #include "mt76x02_mcu.h" |
| 12 | #include "trace.h" |
| 13 | |
| 14 | static void mt76x02_pre_tbtt_tasklet(struct tasklet_struct *t) |
| 15 | { |
| 16 | struct mt76x02_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet); |
| 17 | struct mt76_dev *mdev = &dev->mt76; |
| 18 | struct mt76_queue *q = dev->mphy.q_tx[MT_TXQ_PSD]; |
| 19 | struct beacon_bc_data data = {}; |
| 20 | struct sk_buff *skb; |
| 21 | int i; |
| 22 | |
| 23 | if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
| 24 | return; |
| 25 | |
| 26 | mt76x02_resync_beacon_timer(dev); |
| 27 | |
| 28 | /* Prevent corrupt transmissions during update */ |
| 29 | mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff); |
| 30 | dev->beacon_data_count = 0; |
| 31 | |
| 32 | ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), |
| 33 | IEEE80211_IFACE_ITER_RESUME_ALL, |
| 34 | mt76x02_update_beacon_iter, dev); |
| 35 | |
| 36 | mt76_wr(dev, MT_BCN_BYPASS_MASK, |
| 37 | 0xff00 | ~(0xff00 >> dev->beacon_data_count)); |
| 38 | |
| 39 | mt76_csa_check(mdev); |
| 40 | |
| 41 | if (mdev->csa_complete) |
| 42 | return; |
| 43 | |
| 44 | mt76x02_enqueue_buffered_bc(dev, &data, 8); |
| 45 | |
| 46 | if (!skb_queue_len(&data.q)) |
| 47 | return; |
| 48 | |
| 49 | for (i = 0; i < ARRAY_SIZE(data.tail); i++) { |
| 50 | if (!data.tail[i]) |
| 51 | continue; |
| 52 | |
| 53 | mt76_skb_set_moredata(data.tail[i], false); |
| 54 | } |
| 55 | |
| 56 | spin_lock(&q->lock); |
| 57 | while ((skb = __skb_dequeue(&data.q)) != NULL) { |
| 58 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
| 59 | struct ieee80211_vif *vif = info->control.vif; |
| 60 | struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv; |
| 61 | |
| 62 | mt76_tx_queue_skb(dev, q, skb, &mvif->group_wcid, NULL); |
| 63 | } |
| 64 | spin_unlock(&q->lock); |
| 65 | } |
| 66 | |
| 67 | static void mt76x02e_pre_tbtt_enable(struct mt76x02_dev *dev, bool en) |
| 68 | { |
| 69 | if (en) |
| 70 | tasklet_enable(&dev->mt76.pre_tbtt_tasklet); |
| 71 | else |
| 72 | tasklet_disable(&dev->mt76.pre_tbtt_tasklet); |
| 73 | } |
| 74 | |
| 75 | static void mt76x02e_beacon_enable(struct mt76x02_dev *dev, bool en) |
| 76 | { |
| 77 | mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en); |
| 78 | if (en) |
| 79 | mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); |
| 80 | else |
| 81 | mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); |
| 82 | } |
| 83 | |
| 84 | void mt76x02e_init_beacon_config(struct mt76x02_dev *dev) |
| 85 | { |
| 86 | static const struct mt76x02_beacon_ops beacon_ops = { |
| 87 | .nslots = 8, |
| 88 | .slot_size = 1024, |
| 89 | .pre_tbtt_enable = mt76x02e_pre_tbtt_enable, |
| 90 | .beacon_enable = mt76x02e_beacon_enable, |
| 91 | }; |
| 92 | |
| 93 | dev->beacon_ops = &beacon_ops; |
| 94 | |
| 95 | /* Fire a pre-TBTT interrupt 8 ms before TBTT */ |
| 96 | mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT, |
| 97 | 8 << 4); |
| 98 | mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER, |
| 99 | MT_DFS_GP_INTERVAL); |
| 100 | mt76_wr(dev, MT_INT_TIMER_EN, 0); |
| 101 | |
| 102 | mt76x02_init_beacon_config(dev); |
| 103 | } |
| 104 | EXPORT_SYMBOL_GPL(mt76x02e_init_beacon_config); |
| 105 | |
| 106 | static int |
| 107 | mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q, |
| 108 | int idx, int n_desc, int bufsize) |
| 109 | { |
| 110 | int err; |
| 111 | |
| 112 | err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize, |
| 113 | MT_RX_RING_BASE); |
| 114 | if (err < 0) |
| 115 | return err; |
| 116 | |
| 117 | mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx)); |
| 118 | |
| 119 | return 0; |
| 120 | } |
| 121 | |
| 122 | static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev) |
| 123 | { |
| 124 | struct mt76x02_tx_status stat; |
| 125 | u8 update = 1; |
| 126 | |
| 127 | while (kfifo_get(&dev->txstatus_fifo, &stat)) |
| 128 | mt76x02_send_tx_status(dev, &stat, &update); |
| 129 | } |
| 130 | |
| 131 | static void mt76x02_tx_worker(struct mt76_worker *w) |
| 132 | { |
| 133 | struct mt76x02_dev *dev; |
| 134 | |
| 135 | dev = container_of(w, struct mt76x02_dev, mt76.tx_worker); |
| 136 | |
| 137 | mt76x02_mac_poll_tx_status(dev, false); |
| 138 | mt76x02_process_tx_status_fifo(dev); |
| 139 | |
| 140 | mt76_txq_schedule_all(&dev->mphy); |
| 141 | } |
| 142 | |
| 143 | static int mt76x02_poll_tx(struct napi_struct *napi, int budget) |
| 144 | { |
| 145 | struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev, |
| 146 | mt76.tx_napi); |
| 147 | int i; |
| 148 | |
| 149 | mt76x02_mac_poll_tx_status(dev, false); |
| 150 | |
| 151 | mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); |
| 152 | for (i = MT_TXQ_PSD; i >= 0; i--) |
| 153 | mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); |
| 154 | |
| 155 | if (napi_complete_done(napi, 0)) |
| 156 | mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL); |
| 157 | |
| 158 | mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); |
| 159 | for (i = MT_TXQ_PSD; i >= 0; i--) |
| 160 | mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); |
| 161 | |
| 162 | mt76_worker_schedule(&dev->mt76.tx_worker); |
| 163 | |
| 164 | return 0; |
| 165 | } |
| 166 | |
| 167 | int mt76x02_dma_init(struct mt76x02_dev *dev) |
| 168 | { |
| 169 | struct mt76_txwi_cache __maybe_unused *t; |
| 170 | int i, ret, fifo_size; |
| 171 | struct mt76_queue *q; |
| 172 | void *status_fifo; |
| 173 | |
| 174 | BUILD_BUG_ON(sizeof(struct mt76x02_rxwi) > MT_RX_HEADROOM); |
| 175 | |
| 176 | fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x02_tx_status)); |
| 177 | status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL); |
| 178 | if (!status_fifo) |
| 179 | return -ENOMEM; |
| 180 | |
| 181 | dev->mt76.tx_worker.fn = mt76x02_tx_worker; |
| 182 | tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet); |
| 183 | |
| 184 | spin_lock_init(&dev->txstatus_fifo_lock); |
| 185 | kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size); |
| 186 | |
| 187 | mt76_dma_attach(&dev->mt76); |
| 188 | |
| 189 | mt76_wr(dev, MT_WPDMA_RST_IDX, ~0); |
| 190 | |
| 191 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
| 192 | ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i), |
| 193 | MT76x02_TX_RING_SIZE, |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 194 | MT_TX_RING_BASE, 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 195 | if (ret) |
| 196 | return ret; |
| 197 | } |
| 198 | |
| 199 | ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT, |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 200 | MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE, 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 201 | if (ret) |
| 202 | return ret; |
| 203 | |
| 204 | ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT_TX_HW_QUEUE_MCU, |
| 205 | MT_MCU_RING_SIZE, MT_TX_RING_BASE); |
| 206 | if (ret) |
| 207 | return ret; |
| 208 | |
| 209 | mt76x02_irq_enable(dev, |
| 210 | MT_INT_TX_DONE(IEEE80211_AC_VO) | |
| 211 | MT_INT_TX_DONE(IEEE80211_AC_VI) | |
| 212 | MT_INT_TX_DONE(IEEE80211_AC_BE) | |
| 213 | MT_INT_TX_DONE(IEEE80211_AC_BK) | |
| 214 | MT_INT_TX_DONE(MT_TX_HW_QUEUE_MGMT) | |
| 215 | MT_INT_TX_DONE(MT_TX_HW_QUEUE_MCU)); |
| 216 | |
| 217 | ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1, |
| 218 | MT_MCU_RING_SIZE, MT_RX_BUF_SIZE); |
| 219 | if (ret) |
| 220 | return ret; |
| 221 | |
| 222 | q = &dev->mt76.q_rx[MT_RXQ_MAIN]; |
| 223 | q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x02_rxwi); |
| 224 | ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE, |
| 225 | MT_RX_BUF_SIZE); |
| 226 | if (ret) |
| 227 | return ret; |
| 228 | |
| 229 | ret = mt76_init_queues(dev, mt76_dma_rx_poll); |
| 230 | if (ret) |
| 231 | return ret; |
| 232 | |
| 233 | netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, |
| 234 | mt76x02_poll_tx, NAPI_POLL_WEIGHT); |
| 235 | napi_enable(&dev->mt76.tx_napi); |
| 236 | |
| 237 | return 0; |
| 238 | } |
| 239 | EXPORT_SYMBOL_GPL(mt76x02_dma_init); |
| 240 | |
| 241 | void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q) |
| 242 | { |
| 243 | struct mt76x02_dev *dev; |
| 244 | |
| 245 | dev = container_of(mdev, struct mt76x02_dev, mt76); |
| 246 | mt76x02_irq_enable(dev, MT_INT_RX_DONE(q)); |
| 247 | } |
| 248 | EXPORT_SYMBOL_GPL(mt76x02_rx_poll_complete); |
| 249 | |
| 250 | irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance) |
| 251 | { |
| 252 | struct mt76x02_dev *dev = dev_instance; |
| 253 | u32 intr, mask; |
| 254 | |
| 255 | intr = mt76_rr(dev, MT_INT_SOURCE_CSR); |
| 256 | intr &= dev->mt76.mmio.irqmask; |
| 257 | mt76_wr(dev, MT_INT_SOURCE_CSR, intr); |
| 258 | |
| 259 | if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) |
| 260 | return IRQ_NONE; |
| 261 | |
| 262 | trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); |
| 263 | |
| 264 | mask = intr & (MT_INT_RX_DONE_ALL | MT_INT_GPTIMER); |
| 265 | if (intr & (MT_INT_TX_DONE_ALL | MT_INT_TX_STAT)) |
| 266 | mask |= MT_INT_TX_DONE_ALL; |
| 267 | |
| 268 | mt76x02_irq_disable(dev, mask); |
| 269 | |
| 270 | if (intr & MT_INT_RX_DONE(0)) |
| 271 | napi_schedule(&dev->mt76.napi[0]); |
| 272 | |
| 273 | if (intr & MT_INT_RX_DONE(1)) |
| 274 | napi_schedule(&dev->mt76.napi[1]); |
| 275 | |
| 276 | if (intr & MT_INT_PRE_TBTT) |
| 277 | tasklet_schedule(&dev->mt76.pre_tbtt_tasklet); |
| 278 | |
| 279 | /* send buffered multicast frames now */ |
| 280 | if (intr & MT_INT_TBTT) { |
| 281 | if (dev->mt76.csa_complete) |
| 282 | mt76_csa_finish(&dev->mt76); |
| 283 | else |
| 284 | mt76_queue_kick(dev, dev->mphy.q_tx[MT_TXQ_PSD]); |
| 285 | } |
| 286 | |
| 287 | if (intr & MT_INT_TX_STAT) |
| 288 | mt76x02_mac_poll_tx_status(dev, true); |
| 289 | |
| 290 | if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL)) |
| 291 | napi_schedule(&dev->mt76.tx_napi); |
| 292 | |
| 293 | if (intr & MT_INT_GPTIMER) |
| 294 | tasklet_schedule(&dev->dfs_pd.dfs_tasklet); |
| 295 | |
| 296 | return IRQ_HANDLED; |
| 297 | } |
| 298 | EXPORT_SYMBOL_GPL(mt76x02_irq_handler); |
| 299 | |
| 300 | static void mt76x02_dma_enable(struct mt76x02_dev *dev) |
| 301 | { |
| 302 | u32 val; |
| 303 | |
| 304 | mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); |
| 305 | mt76x02_wait_for_wpdma(&dev->mt76, 1000); |
| 306 | usleep_range(50, 100); |
| 307 | |
| 308 | val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) | |
| 309 | MT_WPDMA_GLO_CFG_TX_DMA_EN | |
| 310 | MT_WPDMA_GLO_CFG_RX_DMA_EN; |
| 311 | mt76_set(dev, MT_WPDMA_GLO_CFG, val); |
| 312 | mt76_clear(dev, MT_WPDMA_GLO_CFG, |
| 313 | MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); |
| 314 | } |
| 315 | |
| 316 | void mt76x02_dma_disable(struct mt76x02_dev *dev) |
| 317 | { |
| 318 | u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG); |
| 319 | |
| 320 | val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE | |
| 321 | MT_WPDMA_GLO_CFG_BIG_ENDIAN | |
| 322 | MT_WPDMA_GLO_CFG_HDR_SEG_LEN; |
| 323 | val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE; |
| 324 | mt76_wr(dev, MT_WPDMA_GLO_CFG, val); |
| 325 | } |
| 326 | EXPORT_SYMBOL_GPL(mt76x02_dma_disable); |
| 327 | |
| 328 | void mt76x02_mac_start(struct mt76x02_dev *dev) |
| 329 | { |
| 330 | mt76x02_mac_reset_counters(dev); |
| 331 | mt76x02_dma_enable(dev); |
| 332 | mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter); |
| 333 | mt76_wr(dev, MT_MAC_SYS_CTRL, |
| 334 | MT_MAC_SYS_CTRL_ENABLE_TX | |
| 335 | MT_MAC_SYS_CTRL_ENABLE_RX); |
| 336 | mt76x02_irq_enable(dev, |
| 337 | MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | |
| 338 | MT_INT_TX_STAT); |
| 339 | } |
| 340 | EXPORT_SYMBOL_GPL(mt76x02_mac_start); |
| 341 | |
| 342 | static bool mt76x02_tx_hang(struct mt76x02_dev *dev) |
| 343 | { |
| 344 | u32 dma_idx, prev_dma_idx; |
| 345 | struct mt76_queue *q; |
| 346 | int i; |
| 347 | |
| 348 | for (i = 0; i < 4; i++) { |
| 349 | q = dev->mphy.q_tx[i]; |
| 350 | |
| 351 | prev_dma_idx = dev->mt76.tx_dma_idx[i]; |
| 352 | dma_idx = readl(&q->regs->dma_idx); |
| 353 | dev->mt76.tx_dma_idx[i] = dma_idx; |
| 354 | |
| 355 | if (!q->queued || prev_dma_idx != dma_idx) { |
| 356 | dev->tx_hang_check[i] = 0; |
| 357 | continue; |
| 358 | } |
| 359 | |
| 360 | if (++dev->tx_hang_check[i] >= MT_TX_HANG_TH) |
| 361 | return true; |
| 362 | } |
| 363 | |
| 364 | return false; |
| 365 | } |
| 366 | |
| 367 | static void mt76x02_key_sync(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 368 | struct ieee80211_sta *sta, |
| 369 | struct ieee80211_key_conf *key, void *data) |
| 370 | { |
| 371 | struct mt76x02_dev *dev = hw->priv; |
| 372 | struct mt76_wcid *wcid; |
| 373 | |
| 374 | if (!sta) |
| 375 | return; |
| 376 | |
| 377 | wcid = (struct mt76_wcid *)sta->drv_priv; |
| 378 | |
| 379 | if (wcid->hw_key_idx != key->keyidx || wcid->sw_iv) |
| 380 | return; |
| 381 | |
| 382 | mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key); |
| 383 | } |
| 384 | |
| 385 | static void mt76x02_reset_state(struct mt76x02_dev *dev) |
| 386 | { |
| 387 | int i; |
| 388 | |
| 389 | lockdep_assert_held(&dev->mt76.mutex); |
| 390 | |
| 391 | clear_bit(MT76_STATE_RUNNING, &dev->mphy.state); |
| 392 | |
| 393 | rcu_read_lock(); |
| 394 | ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL); |
| 395 | rcu_read_unlock(); |
| 396 | |
| 397 | for (i = 0; i < MT76x02_N_WCIDS; i++) { |
| 398 | struct ieee80211_sta *sta; |
| 399 | struct ieee80211_vif *vif; |
| 400 | struct mt76x02_sta *msta; |
| 401 | struct mt76_wcid *wcid; |
| 402 | void *priv; |
| 403 | |
| 404 | wcid = rcu_dereference_protected(dev->mt76.wcid[i], |
| 405 | lockdep_is_held(&dev->mt76.mutex)); |
| 406 | if (!wcid) |
| 407 | continue; |
| 408 | |
| 409 | rcu_assign_pointer(dev->mt76.wcid[i], NULL); |
| 410 | |
| 411 | priv = msta = container_of(wcid, struct mt76x02_sta, wcid); |
| 412 | sta = container_of(priv, struct ieee80211_sta, drv_priv); |
| 413 | |
| 414 | priv = msta->vif; |
| 415 | vif = container_of(priv, struct ieee80211_vif, drv_priv); |
| 416 | |
| 417 | __mt76_sta_remove(&dev->mt76, vif, sta); |
| 418 | memset(msta, 0, sizeof(*msta)); |
| 419 | } |
| 420 | |
| 421 | dev->mt76.vif_mask = 0; |
| 422 | dev->mt76.beacon_mask = 0; |
| 423 | } |
| 424 | |
| 425 | static void mt76x02_watchdog_reset(struct mt76x02_dev *dev) |
| 426 | { |
| 427 | u32 mask = dev->mt76.mmio.irqmask; |
| 428 | bool restart = dev->mt76.mcu_ops->mcu_restart; |
| 429 | int i; |
| 430 | |
| 431 | ieee80211_stop_queues(dev->mt76.hw); |
| 432 | set_bit(MT76_RESET, &dev->mphy.state); |
| 433 | |
| 434 | tasklet_disable(&dev->mt76.pre_tbtt_tasklet); |
| 435 | mt76_worker_disable(&dev->mt76.tx_worker); |
| 436 | napi_disable(&dev->mt76.tx_napi); |
| 437 | |
| 438 | mt76_for_each_q_rx(&dev->mt76, i) { |
| 439 | napi_disable(&dev->mt76.napi[i]); |
| 440 | } |
| 441 | |
| 442 | mutex_lock(&dev->mt76.mutex); |
| 443 | |
| 444 | dev->mcu_timeout = 0; |
| 445 | if (restart) |
| 446 | mt76x02_reset_state(dev); |
| 447 | |
| 448 | if (dev->mt76.beacon_mask) |
| 449 | mt76_clear(dev, MT_BEACON_TIME_CFG, |
| 450 | MT_BEACON_TIME_CFG_BEACON_TX | |
| 451 | MT_BEACON_TIME_CFG_TBTT_EN); |
| 452 | |
| 453 | mt76x02_irq_disable(dev, mask); |
| 454 | |
| 455 | /* perform device reset */ |
| 456 | mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); |
| 457 | mt76_wr(dev, MT_MAC_SYS_CTRL, 0); |
| 458 | mt76_clear(dev, MT_WPDMA_GLO_CFG, |
| 459 | MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN); |
| 460 | usleep_range(5000, 10000); |
| 461 | mt76_wr(dev, MT_INT_SOURCE_CSR, 0xffffffff); |
| 462 | |
| 463 | /* let fw reset DMA */ |
| 464 | mt76_set(dev, 0x734, 0x3); |
| 465 | |
| 466 | if (restart) |
| 467 | mt76_mcu_restart(dev); |
| 468 | |
| 469 | mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true); |
| 470 | for (i = 0; i < __MT_TXQ_MAX; i++) |
| 471 | mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); |
| 472 | |
| 473 | mt76_for_each_q_rx(&dev->mt76, i) { |
| 474 | mt76_queue_rx_reset(dev, i); |
| 475 | } |
| 476 | |
| 477 | mt76_tx_status_check(&dev->mt76, true); |
| 478 | |
| 479 | mt76x02_mac_start(dev); |
| 480 | |
| 481 | if (dev->ed_monitor) |
| 482 | mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); |
| 483 | |
| 484 | if (dev->mt76.beacon_mask && !restart) |
| 485 | mt76_set(dev, MT_BEACON_TIME_CFG, |
| 486 | MT_BEACON_TIME_CFG_BEACON_TX | |
| 487 | MT_BEACON_TIME_CFG_TBTT_EN); |
| 488 | |
| 489 | mt76x02_irq_enable(dev, mask); |
| 490 | |
| 491 | mutex_unlock(&dev->mt76.mutex); |
| 492 | |
| 493 | clear_bit(MT76_RESET, &dev->mphy.state); |
| 494 | |
| 495 | mt76_worker_enable(&dev->mt76.tx_worker); |
| 496 | tasklet_enable(&dev->mt76.pre_tbtt_tasklet); |
| 497 | |
| 498 | local_bh_disable(); |
| 499 | napi_enable(&dev->mt76.tx_napi); |
| 500 | napi_schedule(&dev->mt76.tx_napi); |
| 501 | |
| 502 | mt76_for_each_q_rx(&dev->mt76, i) { |
| 503 | napi_enable(&dev->mt76.napi[i]); |
| 504 | napi_schedule(&dev->mt76.napi[i]); |
| 505 | } |
| 506 | local_bh_enable(); |
| 507 | |
| 508 | if (restart) { |
| 509 | set_bit(MT76_RESTART, &dev->mphy.state); |
| 510 | mt76x02_mcu_function_select(dev, Q_SELECT, 1); |
| 511 | ieee80211_restart_hw(dev->mt76.hw); |
| 512 | } else { |
| 513 | ieee80211_wake_queues(dev->mt76.hw); |
| 514 | mt76_txq_schedule_all(&dev->mphy); |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | void mt76x02_reconfig_complete(struct ieee80211_hw *hw, |
| 519 | enum ieee80211_reconfig_type reconfig_type) |
| 520 | { |
| 521 | struct mt76x02_dev *dev = hw->priv; |
| 522 | |
| 523 | if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART) |
| 524 | return; |
| 525 | |
| 526 | clear_bit(MT76_RESTART, &dev->mphy.state); |
| 527 | } |
| 528 | EXPORT_SYMBOL_GPL(mt76x02_reconfig_complete); |
| 529 | |
| 530 | static void mt76x02_check_tx_hang(struct mt76x02_dev *dev) |
| 531 | { |
| 532 | if (test_bit(MT76_RESTART, &dev->mphy.state)) |
| 533 | return; |
| 534 | |
| 535 | if (!mt76x02_tx_hang(dev) && !dev->mcu_timeout) |
| 536 | return; |
| 537 | |
| 538 | mt76x02_watchdog_reset(dev); |
| 539 | |
| 540 | dev->tx_hang_reset++; |
| 541 | memset(dev->tx_hang_check, 0, sizeof(dev->tx_hang_check)); |
| 542 | memset(dev->mt76.tx_dma_idx, 0xff, |
| 543 | sizeof(dev->mt76.tx_dma_idx)); |
| 544 | } |
| 545 | |
| 546 | void mt76x02_wdt_work(struct work_struct *work) |
| 547 | { |
| 548 | struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, |
| 549 | wdt_work.work); |
| 550 | |
| 551 | mt76x02_check_tx_hang(dev); |
| 552 | |
| 553 | ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work, |
| 554 | MT_WATCHDOG_TIME); |
| 555 | } |