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developer5909dd52022-05-09 15:44:17 +08001From 650cb1ed09a37bcb426ec5f27ae0e65f1d65df94 Mon Sep 17 00:00:00 2001
developerb11a5392022-03-31 00:34:47 +08002From: Shayne Chen <shayne.chen@mediatek.com>
developer5909dd52022-05-09 15:44:17 +08003Date: Mon, 9 May 2022 15:12:22 +0800
developer7800b8d2022-06-23 22:15:56 +08004Subject: [PATCH] mt76: besra: add internal debug patch
developerb11a5392022-03-31 00:34:47 +08005
6---
developer7800b8d2022-06-23 22:15:56 +08007 besra/Makefile | 5 +-
8 besra/besra.h | 35 +
9 besra/debugfs.c | 25 +-
10 besra/mac.c | 18 +
11 besra/mcu.c | 4 +
12 besra/mtk_debug.h | 3716 +++++++++++++++++++++++++++++++++++++++++++
13 besra/mtk_debugfs.c | 3576 +++++++++++++++++++++++++++++++++++++++++
developerb11a5392022-03-31 00:34:47 +080014 tools/fwlog.c | 25 +-
15 8 files changed, 7393 insertions(+), 11 deletions(-)
developer7800b8d2022-06-23 22:15:56 +080016 mode change 100755 => 100644 besra/Makefile
17 create mode 100644 besra/mtk_debug.h
18 create mode 100644 besra/mtk_debugfs.c
developerb11a5392022-03-31 00:34:47 +080019
developer7800b8d2022-06-23 22:15:56 +080020diff --git a/besra/Makefile b/besra/Makefile
developerb11a5392022-03-31 00:34:47 +080021old mode 100755
22new mode 100644
developer5909dd52022-05-09 15:44:17 +080023index a51abe0c..edb7800a
developer7800b8d2022-06-23 22:15:56 +080024--- a/besra/Makefile
25+++ b/besra/Makefile
developerb11a5392022-03-31 00:34:47 +080026@@ -1,8 +1,11 @@
27 # SPDX-License-Identifier: ISC
28+EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG
29
developer7800b8d2022-06-23 22:15:56 +080030 obj-$(CONFIG_BESRA) += besra.o
developerb11a5392022-03-31 00:34:47 +080031
developer7800b8d2022-06-23 22:15:56 +080032 besra-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
developerb11a5392022-03-31 00:34:47 +080033 debugfs.o mmio.o
34
developer7800b8d2022-06-23 22:15:56 +080035-besra-$(CONFIG_NL80211_TESTMODE) += testmode.o
developerb11a5392022-03-31 00:34:47 +080036\ No newline at end of file
developer7800b8d2022-06-23 22:15:56 +080037+besra-$(CONFIG_NL80211_TESTMODE) += testmode.o
developerb11a5392022-03-31 00:34:47 +080038+
developer7800b8d2022-06-23 22:15:56 +080039+besra-y += mtk_debugfs.o
40diff --git a/besra/besra.h b/besra/besra.h
developer5909dd52022-05-09 15:44:17 +080041index 63a97363..30c3a79b 100644
developer7800b8d2022-06-23 22:15:56 +080042--- a/besra/besra.h
43+++ b/besra/besra.h
44@@ -301,6 +301,23 @@ struct besra_dev {
developer5909dd52022-05-09 15:44:17 +080045 u8 table_mask;
46 u8 n_agrt;
47 } twt;
developerb11a5392022-03-31 00:34:47 +080048+
49+#ifdef CONFIG_MTK_DEBUG
50+ u16 wlan_idx;
51+ struct {
52+ bool dump_mcu_pkt;
53+ bool dump_txd;
54+ bool dump_tx_pkt;
55+ bool dump_rx_pkt;
56+ bool dump_rx_raw;
57+ u32 fw_dbg_module;
58+ u8 fw_dbg_lv;
59+ u32 bcn_total_cnt[__MT_MAX_BAND];
60+ u32 token_idx;
61+ u32 rxd_read_cnt;
62+ u32 txd_read_cnt;
63+ } dbg;
64+#endif
65 };
66
67 enum {
developer7800b8d2022-06-23 22:15:56 +080068@@ -571,4 +588,22 @@ void besra_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerb11a5392022-03-31 00:34:47 +080069 struct ieee80211_sta *sta, struct dentry *dir);
70 #endif
71
72+#ifdef CONFIG_MTK_DEBUG
developer7800b8d2022-06-23 22:15:56 +080073+void besra_packet_log_to_host(struct besra_dev *dev, const void *data, int len, int type, int des_len);
developerb11a5392022-03-31 00:34:47 +080074+
75+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
76+enum {
77+ PKT_BIN_DEBUG_MCU,
78+ PKT_BIN_DEBUG_TXD,
79+ PKT_BIN_DEBUG_TX,
80+ PKT_BIN_DEBUG_RX,
81+ PKT_BIN_DEBUG_RX_RAW,
82+};
83+
developer7800b8d2022-06-23 22:15:56 +080084+int besra_mtk_init_debugfs(struct besra_phy *phy, struct dentry *dir);
85+void besra_dump_bmac_rxd_info(struct besra_dev *dev, __le32 *rxd);
86+void besra_dump_bmac_txd_info(struct besra_dev *dev, __le32 *txd, bool dump_txp);
87+void besra_dump_bmac_txp_info(struct besra_dev *dev, __le32 *txp);
developerb11a5392022-03-31 00:34:47 +080088+#endif
89+
90 #endif
developer7800b8d2022-06-23 22:15:56 +080091diff --git a/besra/debugfs.c b/besra/debugfs.c
developer5909dd52022-05-09 15:44:17 +080092index 4be253ea..9f3e11a8 100644
developer7800b8d2022-06-23 22:15:56 +080093--- a/besra/debugfs.c
94+++ b/besra/debugfs.c
95@@ -371,6 +371,9 @@ besra_fw_debug_wm_set(void *data, u64 val)
developerb11a5392022-03-31 00:34:47 +080096 int ret;
97
98 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
99+#ifdef CONFIG_MTK_DEBUG
100+ dev->fw_debug_wm = val;
101+#endif
102
103 if (dev->fw_debug_bin)
104 val = MCU_FW_LOG_RELAY;
developer7800b8d2022-06-23 22:15:56 +0800105@@ -494,6 +497,16 @@ besra_fw_debug_bin_set(void *data, u64 val)
developerb11a5392022-03-31 00:34:47 +0800106
107 relay_reset(dev->relay_fwlog);
108
109+#ifdef CONFIG_MTK_DEBUG
110+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
111+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
112+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
113+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
114+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
115+ if (!(val & GENMASK(3, 0)))
116+ return 0;
117+#endif
118+
developer7800b8d2022-06-23 22:15:56 +0800119 return besra_fw_debug_wm_set(dev, dev->fw_debug_wm);
developerb11a5392022-03-31 00:34:47 +0800120 }
121
developer7800b8d2022-06-23 22:15:56 +0800122@@ -942,8 +955,13 @@ int besra_init_debugfs(struct besra_phy *phy)
123 besra_rdd_monitor);
developerb11a5392022-03-31 00:34:47 +0800124 }
125
126- if (phy == &dev->phy)
127+ if (phy == &dev->phy) {
128 dev->debugfs_dir = dir;
129+#ifdef CONFIG_MTK_DEBUG
130+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
developer7800b8d2022-06-23 22:15:56 +0800131+ besra_mtk_init_debugfs(phy, dir);
developerb11a5392022-03-31 00:34:47 +0800132+#endif
133+ }
134
135 return 0;
136 }
developer7800b8d2022-06-23 22:15:56 +0800137@@ -1000,7 +1018,12 @@ void besra_debugfs_rx_fw_monitor(struct besra_dev *dev, const void *data, int le
developerb11a5392022-03-31 00:34:47 +0800138
developer7800b8d2022-06-23 22:15:56 +0800139 bool besra_debugfs_rx_log(struct besra_dev *dev, const void *data, int len)
developerb11a5392022-03-31 00:34:47 +0800140 {
141+#ifdef CONFIG_MTK_DEBUG
142+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
143+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
144+#else
145 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
146+#endif
147 return false;
148
149 if (dev->relay_fwlog)
developer7800b8d2022-06-23 22:15:56 +0800150diff --git a/besra/mac.c b/besra/mac.c
developer5909dd52022-05-09 15:44:17 +0800151index 2d48a1a4..b726e2d8 100644
developer7800b8d2022-06-23 22:15:56 +0800152--- a/besra/mac.c
153+++ b/besra/mac.c
154@@ -589,6 +589,11 @@ besra_mac_fill_rx(struct besra_dev *dev, struct sk_buff *skb)
developerb11a5392022-03-31 00:34:47 +0800155 int idx;
156 u8 band_idx;
157
158+#ifdef CONFIG_MTK_DEBUG
159+ if (dev->dbg.dump_rx_raw)
developer7800b8d2022-06-23 22:15:56 +0800160+ besra_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
161+ besra_dump_bmac_rxd_info(dev, rxd);
developerb11a5392022-03-31 00:34:47 +0800162+#endif
163 memset(status, 0, sizeof(*status));
164
165 band_idx = FIELD_GET(MT_RXD1_NORMAL_BAND_IDX, rxd1);
developer7800b8d2022-06-23 22:15:56 +0800166@@ -763,6 +768,10 @@ besra_mac_fill_rx(struct besra_dev *dev, struct sk_buff *skb)
developerb11a5392022-03-31 00:34:47 +0800167 }
168
169 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
170+#ifdef CONFIG_MTK_DEBUG
171+ if (dev->dbg.dump_rx_pkt)
developer7800b8d2022-06-23 22:15:56 +0800172+ besra_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
developerb11a5392022-03-31 00:34:47 +0800173+#endif
174 if (hdr_trans && ieee80211_has_morefrags(fc)) {
developer7800b8d2022-06-23 22:15:56 +0800175 if (besra_reverse_frag0_hdr_trans(skb, hdr_gap))
developerb11a5392022-03-31 00:34:47 +0800176 return -EINVAL;
developer7800b8d2022-06-23 22:15:56 +0800177@@ -1330,6 +1339,15 @@ int besra_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developerb11a5392022-03-31 00:34:47 +0800178 tx_info->buf[1].skip_unmap = true;
179 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
180
181+#ifdef CONFIG_MTK_DEBUG
developer7800b8d2022-06-23 22:15:56 +0800182+ besra_dump_bmac_txd_info(dev, (__le32 *)txwi, true);
developerb11a5392022-03-31 00:34:47 +0800183+
184+ if (dev->dbg.dump_txd)
developer7800b8d2022-06-23 22:15:56 +0800185+ besra_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
developerb11a5392022-03-31 00:34:47 +0800186+ if (dev->dbg.dump_tx_pkt)
developer7800b8d2022-06-23 22:15:56 +0800187+ besra_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
developerb11a5392022-03-31 00:34:47 +0800188+#endif
189+
190 return 0;
191 }
192
developer7800b8d2022-06-23 22:15:56 +0800193diff --git a/besra/mcu.c b/besra/mcu.c
developer5909dd52022-05-09 15:44:17 +0800194index 5276552c..6fc175c6 100644
developer7800b8d2022-06-23 22:15:56 +0800195--- a/besra/mcu.c
196+++ b/besra/mcu.c
197@@ -299,6 +299,10 @@ besra_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
developerb11a5392022-03-31 00:34:47 +0800198 mcu_txd->s2d_index = MCU_S2D_H2N;
199
200 exit:
201+#ifdef CONFIG_MTK_DEBUG
202+ if (dev->dbg.dump_mcu_pkt)
developer7800b8d2022-06-23 22:15:56 +0800203+ besra_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
developerb11a5392022-03-31 00:34:47 +0800204+#endif
205 if (wait_seq)
206 *wait_seq = seq;
207
developer7800b8d2022-06-23 22:15:56 +0800208diff --git a/besra/mtk_debug.h b/besra/mtk_debug.h
developerb11a5392022-03-31 00:34:47 +0800209new file mode 100644
developer5909dd52022-05-09 15:44:17 +0800210index 00000000..1a797c81
developerb11a5392022-03-31 00:34:47 +0800211--- /dev/null
developer7800b8d2022-06-23 22:15:56 +0800212+++ b/besra/mtk_debug.h
developerb11a5392022-03-31 00:34:47 +0800213@@ -0,0 +1,3716 @@
214+#ifndef __MTK_DEBUG_H
215+#define __MTK_DEBUG_H
216+
217+#ifdef CONFIG_MTK_DEBUG
218+
219+struct bin_debug_hdr {
220+ __le32 magic_num;
221+ __le16 serial_id;
222+ __le16 msg_type;
223+ __le16 len;
224+ __le16 des_len; /* descriptor len for rxd */
225+} __packed;
226+
227+#define NO_SHIFT_DEFINE 0xFFFFFFFF
228+#define BITS(m, n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n)))
229+
230+#define GET_FIELD(_field, _reg) \
231+ ({ \
232+ (((_reg) & (_field##_MASK)) >> (_field##_SHIFT)); \
233+ })
234+
235+struct queue_desc {
236+ u32 hw_desc_base;
237+ u16 ring_size;
238+ char *const ring_info;
239+};
240+
241+enum umac_port {
242+ ENUM_UMAC_HIF_PORT_0 = 0,
243+ ENUM_UMAC_CPU_PORT_1 = 1,
244+ ENUM_UMAC_LMAC_PORT_2 = 2,
245+ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
246+ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
247+};
248+
249+/* N9 MCU QUEUE LIST */
250+enum umac_cpu_port_queue_idx {
251+ ENUM_UMAC_CTX_Q_0 = 0,
252+ ENUM_UMAC_CTX_Q_1 = 1,
253+ ENUM_UMAC_CTX_Q_2 = 2,
254+ ENUM_UMAC_CTX_Q_3 = 3,
255+ ENUM_UMAC_CRX = 0,
256+ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
257+};
258+
259+/* LMAC PLE For PSE Control P3 */
260+enum umac_ple_ctrl_port3_queue_idx {
261+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
262+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
263+ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
264+};
265+
266+/* PSE PLE QUEUE */
267+#define CR_NUM_OF_AC 9
268+#define ALL_CR_NUM_OF_ALL_AC (CR_NUM_OF_AC * 4)
269+struct bmac_queue_info {
270+ char *QueueName;
271+ u32 Portid;
272+ u32 Queueid;
273+ u32 tgid;
274+};
275+
276+struct bmac_queue_info_t {
277+ char *QueueName;
278+ u32 Portid;
279+ u32 Queueid;
280+};
281+
282+/* WTBL */
developer7800b8d2022-06-23 22:15:56 +0800283+enum besra_wtbl_type {
developerb11a5392022-03-31 00:34:47 +0800284+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
285+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
286+ WTBL_TYPE_KEY, /* Key Table */
287+ MAX_NUM_WTBL_TYPE
288+};
289+
290+struct berse_wtbl_parse {
291+ u8 *name;
292+ u32 mask;
293+ u32 shift;
294+ u8 new_line;
295+};
296+
297+enum muar_idx {
298+ MUAR_INDEX_OWN_MAC_ADDR_0 = 0,
299+ MUAR_INDEX_OWN_MAC_ADDR_1,
300+ MUAR_INDEX_OWN_MAC_ADDR_2,
301+ MUAR_INDEX_OWN_MAC_ADDR_3,
302+ MUAR_INDEX_OWN_MAC_ADDR_4,
303+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC = 0xE,
304+ MUAR_INDEX_UNMATCHED = 0xF,
305+ MUAR_INDEX_OWN_MAC_ADDR_11 = 0x11,
306+ MUAR_INDEX_OWN_MAC_ADDR_12,
307+ MUAR_INDEX_OWN_MAC_ADDR_13,
308+ MUAR_INDEX_OWN_MAC_ADDR_14,
309+ MUAR_INDEX_OWN_MAC_ADDR_15,
310+ MUAR_INDEX_OWN_MAC_ADDR_16,
311+ MUAR_INDEX_OWN_MAC_ADDR_17,
312+ MUAR_INDEX_OWN_MAC_ADDR_18,
313+ MUAR_INDEX_OWN_MAC_ADDR_19,
314+ MUAR_INDEX_OWN_MAC_ADDR_1A,
315+ MUAR_INDEX_OWN_MAC_ADDR_1B,
316+ MUAR_INDEX_OWN_MAC_ADDR_1C,
317+ MUAR_INDEX_OWN_MAC_ADDR_1D,
318+ MUAR_INDEX_OWN_MAC_ADDR_1E,
319+ MUAR_INDEX_OWN_MAC_ADDR_1F,
320+ MUAR_INDEX_OWN_MAC_ADDR_20,
321+ MUAR_INDEX_OWN_MAC_ADDR_21,
322+ MUAR_INDEX_OWN_MAC_ADDR_22,
323+ MUAR_INDEX_OWN_MAC_ADDR_23,
324+ MUAR_INDEX_OWN_MAC_ADDR_24,
325+ MUAR_INDEX_OWN_MAC_ADDR_25,
326+ MUAR_INDEX_OWN_MAC_ADDR_26,
327+ MUAR_INDEX_OWN_MAC_ADDR_27,
328+ MUAR_INDEX_OWN_MAC_ADDR_28,
329+ MUAR_INDEX_OWN_MAC_ADDR_29,
330+ MUAR_INDEX_OWN_MAC_ADDR_2A,
331+ MUAR_INDEX_OWN_MAC_ADDR_2B,
332+ MUAR_INDEX_OWN_MAC_ADDR_2C,
333+ MUAR_INDEX_OWN_MAC_ADDR_2D,
334+ MUAR_INDEX_OWN_MAC_ADDR_2E,
335+ MUAR_INDEX_OWN_MAC_ADDR_2F
336+};
337+
338+enum cipher_suit {
339+ IGTK_CIPHER_SUIT_NONE = 0,
340+ IGTK_CIPHER_SUIT_BIP,
341+ IGTK_CIPHER_SUIT_BIP_256
342+};
343+
344+#define LWTBL_LEN_IN_DW 36
345+#define UWTBL_LEN_IN_DW 10
346+
347+#define MT_DBG_WTBL_BASE 0x820D8000
348+
349+#define MT_DBG_WTBLON_TOP_BASE 0x820d4000
350+#define MT_DBG_WTBLON_TOP_WDUCR_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x0370) // 4370
351+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
352+
353+#define MT_DBG_UWTBL_TOP_BASE 0x820c4000
354+#define MT_DBG_UWTBL_TOP_WDUCR_ADDR (MT_DBG_UWTBL_TOP_BASE + 0x0104) // 4104
355+#define MT_DBG_UWTBL_TOP_WDUCR_GROUP GENMASK(5, 0)
356+#define MT_DBG_UWTBL_TOP_WDUCR_TARGET BIT(31)
357+
358+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
359+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
360+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
361+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
362+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
363+
364+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
365+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
366+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
367+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
368+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
369+
370+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
371+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
372+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
373+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
374+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
375+
376+// UMAC WTBL
377+// DW0
378+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__DW 0
379+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__ADDR 0
380+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__MASK 0x0000ffff // 15- 0
381+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__SHIFT 0
382+#define WF_UWTBL_OWN_MLD_ID_DW 0
383+#define WF_UWTBL_OWN_MLD_ID_ADDR 0
384+#define WF_UWTBL_OWN_MLD_ID_MASK 0x003f0000 // 21-16
385+#define WF_UWTBL_OWN_MLD_ID_SHIFT 16
386+// DW1
387+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__DW 1
388+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__ADDR 4
389+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__MASK 0xffffffff // 31- 0
390+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__SHIFT 0
391+// DW2
392+#define WF_UWTBL_PN_31_0__DW 2
393+#define WF_UWTBL_PN_31_0__ADDR 8
394+#define WF_UWTBL_PN_31_0__MASK 0xffffffff // 31- 0
395+#define WF_UWTBL_PN_31_0__SHIFT 0
396+// DW3
397+#define WF_UWTBL_PN_47_32__DW 3
398+#define WF_UWTBL_PN_47_32__ADDR 12
399+#define WF_UWTBL_PN_47_32__MASK 0x0000ffff // 15- 0
400+#define WF_UWTBL_PN_47_32__SHIFT 0
401+#define WF_UWTBL_COM_SN_DW 3
402+#define WF_UWTBL_COM_SN_ADDR 12
403+#define WF_UWTBL_COM_SN_MASK 0x0fff0000 // 27-16
404+#define WF_UWTBL_COM_SN_SHIFT 16
405+// DW4
406+#define WF_UWTBL_TID0_SN_DW 4
407+#define WF_UWTBL_TID0_SN_ADDR 16
408+#define WF_UWTBL_TID0_SN_MASK 0x00000fff // 11- 0
409+#define WF_UWTBL_TID0_SN_SHIFT 0
410+#define WF_UWTBL_RX_BIPN_31_0__DW 4
411+#define WF_UWTBL_RX_BIPN_31_0__ADDR 16
412+#define WF_UWTBL_RX_BIPN_31_0__MASK 0xffffffff // 31- 0
413+#define WF_UWTBL_RX_BIPN_31_0__SHIFT 0
414+#define WF_UWTBL_TID1_SN_DW 4
415+#define WF_UWTBL_TID1_SN_ADDR 16
416+#define WF_UWTBL_TID1_SN_MASK 0x00fff000 // 23-12
417+#define WF_UWTBL_TID1_SN_SHIFT 12
418+#define WF_UWTBL_TID2_SN_7_0__DW 4
419+#define WF_UWTBL_TID2_SN_7_0__ADDR 16
420+#define WF_UWTBL_TID2_SN_7_0__MASK 0xff000000 // 31-24
421+#define WF_UWTBL_TID2_SN_7_0__SHIFT 24
422+// DW5
423+#define WF_UWTBL_TID2_SN_11_8__DW 5
424+#define WF_UWTBL_TID2_SN_11_8__ADDR 20
425+#define WF_UWTBL_TID2_SN_11_8__MASK 0x0000000f // 3- 0
426+#define WF_UWTBL_TID2_SN_11_8__SHIFT 0
427+#define WF_UWTBL_RX_BIPN_47_32__DW 5
428+#define WF_UWTBL_RX_BIPN_47_32__ADDR 20
429+#define WF_UWTBL_RX_BIPN_47_32__MASK 0x0000ffff // 15- 0
430+#define WF_UWTBL_RX_BIPN_47_32__SHIFT 0
431+#define WF_UWTBL_TID3_SN_DW 5
432+#define WF_UWTBL_TID3_SN_ADDR 20
433+#define WF_UWTBL_TID3_SN_MASK 0x0000fff0 // 15- 4
434+#define WF_UWTBL_TID3_SN_SHIFT 4
435+#define WF_UWTBL_TID4_SN_DW 5
436+#define WF_UWTBL_TID4_SN_ADDR 20
437+#define WF_UWTBL_TID4_SN_MASK 0x0fff0000 // 27-16
438+#define WF_UWTBL_TID4_SN_SHIFT 16
439+#define WF_UWTBL_TID5_SN_3_0__DW 5
440+#define WF_UWTBL_TID5_SN_3_0__ADDR 20
441+#define WF_UWTBL_TID5_SN_3_0__MASK 0xf0000000 // 31-28
442+#define WF_UWTBL_TID5_SN_3_0__SHIFT 28
443+// DW6
444+#define WF_UWTBL_TID5_SN_11_4__DW 6
445+#define WF_UWTBL_TID5_SN_11_4__ADDR 24
446+#define WF_UWTBL_TID5_SN_11_4__MASK 0x000000ff // 7- 0
447+#define WF_UWTBL_TID5_SN_11_4__SHIFT 0
448+#define WF_UWTBL_KEY_LOC2_DW 6
449+#define WF_UWTBL_KEY_LOC2_ADDR 24
450+#define WF_UWTBL_KEY_LOC2_MASK 0x00001fff // 12- 0
451+#define WF_UWTBL_KEY_LOC2_SHIFT 0
452+#define WF_UWTBL_TID6_SN_DW 6
453+#define WF_UWTBL_TID6_SN_ADDR 24
454+#define WF_UWTBL_TID6_SN_MASK 0x000fff00 // 19- 8
455+#define WF_UWTBL_TID6_SN_SHIFT 8
456+#define WF_UWTBL_TID7_SN_DW 6
457+#define WF_UWTBL_TID7_SN_ADDR 24
458+#define WF_UWTBL_TID7_SN_MASK 0xfff00000 // 31-20
459+#define WF_UWTBL_TID7_SN_SHIFT 20
460+// DW7
461+#define WF_UWTBL_KEY_LOC0_DW 7
462+#define WF_UWTBL_KEY_LOC0_ADDR 28
463+#define WF_UWTBL_KEY_LOC0_MASK 0x00001fff // 12- 0
464+#define WF_UWTBL_KEY_LOC0_SHIFT 0
465+#define WF_UWTBL_KEY_LOC1_DW 7
466+#define WF_UWTBL_KEY_LOC1_ADDR 28
467+#define WF_UWTBL_KEY_LOC1_MASK 0x1fff0000 // 28-16
468+#define WF_UWTBL_KEY_LOC1_SHIFT 16
469+// DW8
470+#define WF_UWTBL_AMSDU_CFG_DW 8
471+#define WF_UWTBL_AMSDU_CFG_ADDR 32
472+#define WF_UWTBL_AMSDU_CFG_MASK 0x00000fff // 11- 0
473+#define WF_UWTBL_AMSDU_CFG_SHIFT 0
474+#define WF_UWTBL_WMM_Q_DW 8
475+#define WF_UWTBL_WMM_Q_ADDR 32
476+#define WF_UWTBL_WMM_Q_MASK 0x06000000 // 26-25
477+#define WF_UWTBL_WMM_Q_SHIFT 25
478+#define WF_UWTBL_QOS_DW 8
479+#define WF_UWTBL_QOS_ADDR 32
480+#define WF_UWTBL_QOS_MASK 0x08000000 // 27-27
481+#define WF_UWTBL_QOS_SHIFT 27
482+#define WF_UWTBL_HT_DW 8
483+#define WF_UWTBL_HT_ADDR 32
484+#define WF_UWTBL_HT_MASK 0x10000000 // 28-28
485+#define WF_UWTBL_HT_SHIFT 28
486+#define WF_UWTBL_HDRT_MODE_DW 8
487+#define WF_UWTBL_HDRT_MODE_ADDR 32
488+#define WF_UWTBL_HDRT_MODE_MASK 0x20000000 // 29-29
489+#define WF_UWTBL_HDRT_MODE_SHIFT 29
490+// DW9
491+#define WF_UWTBL_RELATED_IDX0_DW 9
492+#define WF_UWTBL_RELATED_IDX0_ADDR 36
493+#define WF_UWTBL_RELATED_IDX0_MASK 0x00000fff // 11- 0
494+#define WF_UWTBL_RELATED_IDX0_SHIFT 0
495+#define WF_UWTBL_RELATED_BAND0_DW 9
496+#define WF_UWTBL_RELATED_BAND0_ADDR 36
497+#define WF_UWTBL_RELATED_BAND0_MASK 0x00003000 // 13-12
498+#define WF_UWTBL_RELATED_BAND0_SHIFT 12
499+#define WF_UWTBL_PRIMARY_MLD_BAND_DW 9
500+#define WF_UWTBL_PRIMARY_MLD_BAND_ADDR 36
501+#define WF_UWTBL_PRIMARY_MLD_BAND_MASK 0x0000c000 // 15-14
502+#define WF_UWTBL_PRIMARY_MLD_BAND_SHIFT 14
503+#define WF_UWTBL_RELATED_IDX1_DW 9
504+#define WF_UWTBL_RELATED_IDX1_ADDR 36
505+#define WF_UWTBL_RELATED_IDX1_MASK 0x0fff0000 // 27-16
506+#define WF_UWTBL_RELATED_IDX1_SHIFT 16
507+#define WF_UWTBL_RELATED_BAND1_DW 9
508+#define WF_UWTBL_RELATED_BAND1_ADDR 36
509+#define WF_UWTBL_RELATED_BAND1_MASK 0x30000000 // 29-28
510+#define WF_UWTBL_RELATED_BAND1_SHIFT 28
511+#define WF_UWTBL_SECONDARY_MLD_BAND_DW 9
512+#define WF_UWTBL_SECONDARY_MLD_BAND_ADDR 36
513+#define WF_UWTBL_SECONDARY_MLD_BAND_MASK 0xc0000000 // 31-30
514+#define WF_UWTBL_SECONDARY_MLD_BAND_SHIFT 30
515+
516+/* LMAC WTBL */
517+// DW0
518+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__DW 0
519+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__ADDR 0
520+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__MASK \
521+ 0x0000ffff // 15- 0
522+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__SHIFT 0
523+#define WF_LWTBL_MUAR_DW 0
524+#define WF_LWTBL_MUAR_ADDR 0
525+#define WF_LWTBL_MUAR_MASK \
526+ 0x003f0000 // 21-16
527+#define WF_LWTBL_MUAR_SHIFT 16
528+#define WF_LWTBL_RCA1_DW 0
529+#define WF_LWTBL_RCA1_ADDR 0
530+#define WF_LWTBL_RCA1_MASK \
531+ 0x00400000 // 22-22
532+#define WF_LWTBL_RCA1_SHIFT 22
533+#define WF_LWTBL_KID_DW 0
534+#define WF_LWTBL_KID_ADDR 0
535+#define WF_LWTBL_KID_MASK \
536+ 0x01800000 // 24-23
537+#define WF_LWTBL_KID_SHIFT 23
538+#define WF_LWTBL_RCID_DW 0
539+#define WF_LWTBL_RCID_ADDR 0
540+#define WF_LWTBL_RCID_MASK \
541+ 0x02000000 // 25-25
542+#define WF_LWTBL_RCID_SHIFT 25
543+#define WF_LWTBL_BAND_DW 0
544+#define WF_LWTBL_BAND_ADDR 0
545+#define WF_LWTBL_BAND_MASK \
546+ 0x0c000000 // 27-26
547+#define WF_LWTBL_BAND_SHIFT 26
548+#define WF_LWTBL_RV_DW 0
549+#define WF_LWTBL_RV_ADDR 0
550+#define WF_LWTBL_RV_MASK \
551+ 0x10000000 // 28-28
552+#define WF_LWTBL_RV_SHIFT 28
553+#define WF_LWTBL_RCA2_DW 0
554+#define WF_LWTBL_RCA2_ADDR 0
555+#define WF_LWTBL_RCA2_MASK \
556+ 0x20000000 // 29-29
557+#define WF_LWTBL_RCA2_SHIFT 29
558+#define WF_LWTBL_WPI_FLAG_DW 0
559+#define WF_LWTBL_WPI_FLAG_ADDR 0
560+#define WF_LWTBL_WPI_FLAG_MASK \
561+ 0x40000000 // 30-30
562+#define WF_LWTBL_WPI_FLAG_SHIFT 30
563+// DW1
564+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__DW 1
565+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__ADDR 4
566+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__MASK \
567+ 0xffffffff // 31- 0
568+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__SHIFT 0
569+// DW2
570+#define WF_LWTBL_AID_DW 2
571+#define WF_LWTBL_AID_ADDR 8
572+#define WF_LWTBL_AID_MASK \
573+ 0x00000fff // 11- 0
574+#define WF_LWTBL_AID_SHIFT 0
575+#define WF_LWTBL_GID_SU_DW 2
576+#define WF_LWTBL_GID_SU_ADDR 8
577+#define WF_LWTBL_GID_SU_MASK \
578+ 0x00001000 // 12-12
579+#define WF_LWTBL_GID_SU_SHIFT 12
580+#define WF_LWTBL_SPP_EN_DW 2
581+#define WF_LWTBL_SPP_EN_ADDR 8
582+#define WF_LWTBL_SPP_EN_MASK \
583+ 0x00002000 // 13-13
584+#define WF_LWTBL_SPP_EN_SHIFT 13
585+#define WF_LWTBL_WPI_EVEN_DW 2
586+#define WF_LWTBL_WPI_EVEN_ADDR 8
587+#define WF_LWTBL_WPI_EVEN_MASK \
588+ 0x00004000 // 14-14
589+#define WF_LWTBL_WPI_EVEN_SHIFT 14
590+#define WF_LWTBL_AAD_OM_DW 2
591+#define WF_LWTBL_AAD_OM_ADDR 8
592+#define WF_LWTBL_AAD_OM_MASK \
593+ 0x00008000 // 15-15
594+#define WF_LWTBL_AAD_OM_SHIFT 15
595+#define WF_LWTBL_CIPHER_SUIT_PGTK_DW 2
596+#define WF_LWTBL_CIPHER_SUIT_PGTK_ADDR 8
597+#define WF_LWTBL_CIPHER_SUIT_PGTK_MASK \
598+ 0x001f0000 // 20-16
599+#define WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT 16
600+#define WF_LWTBL_FD_DW 2
601+#define WF_LWTBL_FD_ADDR 8
602+#define WF_LWTBL_FD_MASK \
603+ 0x00200000 // 21-21
604+#define WF_LWTBL_FD_SHIFT 21
605+#define WF_LWTBL_TD_DW 2
606+#define WF_LWTBL_TD_ADDR 8
607+#define WF_LWTBL_TD_MASK \
608+ 0x00400000 // 22-22
609+#define WF_LWTBL_TD_SHIFT 22
610+#define WF_LWTBL_SW_DW 2
611+#define WF_LWTBL_SW_ADDR 8
612+#define WF_LWTBL_SW_MASK \
613+ 0x00800000 // 23-23
614+#define WF_LWTBL_SW_SHIFT 23
615+#define WF_LWTBL_UL_DW 2
616+#define WF_LWTBL_UL_ADDR 8
617+#define WF_LWTBL_UL_MASK \
618+ 0x01000000 // 24-24
619+#define WF_LWTBL_UL_SHIFT 24
620+#define WF_LWTBL_TX_PS_DW 2
621+#define WF_LWTBL_TX_PS_ADDR 8
622+#define WF_LWTBL_TX_PS_MASK \
623+ 0x02000000 // 25-25
624+#define WF_LWTBL_TX_PS_SHIFT 25
625+#define WF_LWTBL_QOS_DW 2
626+#define WF_LWTBL_QOS_ADDR 8
627+#define WF_LWTBL_QOS_MASK \
628+ 0x04000000 // 26-26
629+#define WF_LWTBL_QOS_SHIFT 26
630+#define WF_LWTBL_HT_DW 2
631+#define WF_LWTBL_HT_ADDR 8
632+#define WF_LWTBL_HT_MASK \
633+ 0x08000000 // 27-27
634+#define WF_LWTBL_HT_SHIFT 27
635+#define WF_LWTBL_VHT_DW 2
636+#define WF_LWTBL_VHT_ADDR 8
637+#define WF_LWTBL_VHT_MASK \
638+ 0x10000000 // 28-28
639+#define WF_LWTBL_VHT_SHIFT 28
640+#define WF_LWTBL_HE_DW 2
641+#define WF_LWTBL_HE_ADDR 8
642+#define WF_LWTBL_HE_MASK \
643+ 0x20000000 // 29-29
644+#define WF_LWTBL_HE_SHIFT 29
645+#define WF_LWTBL_EHT_DW 2
646+#define WF_LWTBL_EHT_ADDR 8
647+#define WF_LWTBL_EHT_MASK \
648+ 0x40000000 // 30-30
649+#define WF_LWTBL_EHT_SHIFT 30
650+#define WF_LWTBL_MESH_DW 2
651+#define WF_LWTBL_MESH_ADDR 8
652+#define WF_LWTBL_MESH_MASK \
653+ 0x80000000 // 31-31
654+#define WF_LWTBL_MESH_SHIFT 31
655+// DW3
656+#define WF_LWTBL_WMM_Q_DW 3
657+#define WF_LWTBL_WMM_Q_ADDR 12
658+#define WF_LWTBL_WMM_Q_MASK \
659+ 0x00000003 // 1- 0
660+#define WF_LWTBL_WMM_Q_SHIFT 0
661+#define WF_LWTBL_EHT_SIG_MCS_DW 3
662+#define WF_LWTBL_EHT_SIG_MCS_ADDR 12
663+#define WF_LWTBL_EHT_SIG_MCS_MASK \
664+ 0x0000000c // 3- 2
665+#define WF_LWTBL_EHT_SIG_MCS_SHIFT 2
666+#define WF_LWTBL_HDRT_MODE_DW 3
667+#define WF_LWTBL_HDRT_MODE_ADDR 12
668+#define WF_LWTBL_HDRT_MODE_MASK \
669+ 0x00000010 // 4- 4
670+#define WF_LWTBL_HDRT_MODE_SHIFT 4
671+#define WF_LWTBL_BEAM_CHG_DW 3
672+#define WF_LWTBL_BEAM_CHG_ADDR 12
673+#define WF_LWTBL_BEAM_CHG_MASK \
674+ 0x00000020 // 5- 5
675+#define WF_LWTBL_BEAM_CHG_SHIFT 5
676+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_DW 3
677+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_ADDR 12
678+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK \
679+ 0x000000c0 // 7- 6
680+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT 6
681+#define WF_LWTBL_PFMU_IDX_DW 3
682+#define WF_LWTBL_PFMU_IDX_ADDR 12
683+#define WF_LWTBL_PFMU_IDX_MASK \
684+ 0x0000ff00 // 15- 8
685+#define WF_LWTBL_PFMU_IDX_SHIFT 8
686+#define WF_LWTBL_ULPF_IDX_DW 3
687+#define WF_LWTBL_ULPF_IDX_ADDR 12
688+#define WF_LWTBL_ULPF_IDX_MASK \
689+ 0x00ff0000 // 23-16
690+#define WF_LWTBL_ULPF_IDX_SHIFT 16
691+#define WF_LWTBL_RIBF_DW 3
692+#define WF_LWTBL_RIBF_ADDR 12
693+#define WF_LWTBL_RIBF_MASK \
694+ 0x01000000 // 24-24
695+#define WF_LWTBL_RIBF_SHIFT 24
696+#define WF_LWTBL_ULPF_DW 3
697+#define WF_LWTBL_ULPF_ADDR 12
698+#define WF_LWTBL_ULPF_MASK \
699+ 0x02000000 // 25-25
700+#define WF_LWTBL_ULPF_SHIFT 25
701+#define WF_LWTBL_TBF_HT_DW 3
702+#define WF_LWTBL_TBF_HT_ADDR 12
703+#define WF_LWTBL_TBF_HT_MASK \
704+ 0x08000000 // 27-27
705+#define WF_LWTBL_TBF_HT_SHIFT 27
706+#define WF_LWTBL_TBF_VHT_DW 3
707+#define WF_LWTBL_TBF_VHT_ADDR 12
708+#define WF_LWTBL_TBF_VHT_MASK \
709+ 0x10000000 // 28-28
710+#define WF_LWTBL_TBF_VHT_SHIFT 28
711+#define WF_LWTBL_TBF_HE_DW 3
712+#define WF_LWTBL_TBF_HE_ADDR 12
713+#define WF_LWTBL_TBF_HE_MASK \
714+ 0x20000000 // 29-29
715+#define WF_LWTBL_TBF_HE_SHIFT 29
716+#define WF_LWTBL_TBF_EHT_DW 3
717+#define WF_LWTBL_TBF_EHT_ADDR 12
718+#define WF_LWTBL_TBF_EHT_MASK \
719+ 0x40000000 // 30-30
720+#define WF_LWTBL_TBF_EHT_SHIFT 30
721+#define WF_LWTBL_IGN_FBK_DW 3
722+#define WF_LWTBL_IGN_FBK_ADDR 12
723+#define WF_LWTBL_IGN_FBK_MASK \
724+ 0x80000000 // 31-31
725+#define WF_LWTBL_IGN_FBK_SHIFT 31
726+// DW4
727+#define WF_LWTBL_ANT_ID0_DW 4
728+#define WF_LWTBL_ANT_ID0_ADDR 16
729+#define WF_LWTBL_ANT_ID0_MASK \
730+ 0x00000007 // 2- 0
731+#define WF_LWTBL_ANT_ID0_SHIFT 0
732+#define WF_LWTBL_ANT_ID1_DW 4
733+#define WF_LWTBL_ANT_ID1_ADDR 16
734+#define WF_LWTBL_ANT_ID1_MASK \
735+ 0x00000038 // 5- 3
736+#define WF_LWTBL_ANT_ID1_SHIFT 3
737+#define WF_LWTBL_ANT_ID2_DW 4
738+#define WF_LWTBL_ANT_ID2_ADDR 16
739+#define WF_LWTBL_ANT_ID2_MASK \
740+ 0x000001c0 // 8- 6
741+#define WF_LWTBL_ANT_ID2_SHIFT 6
742+#define WF_LWTBL_ANT_ID3_DW 4
743+#define WF_LWTBL_ANT_ID3_ADDR 16
744+#define WF_LWTBL_ANT_ID3_MASK \
745+ 0x00000e00 // 11- 9
746+#define WF_LWTBL_ANT_ID3_SHIFT 9
747+#define WF_LWTBL_ANT_ID4_DW 4
748+#define WF_LWTBL_ANT_ID4_ADDR 16
749+#define WF_LWTBL_ANT_ID4_MASK \
750+ 0x00007000 // 14-12
751+#define WF_LWTBL_ANT_ID4_SHIFT 12
752+#define WF_LWTBL_ANT_ID5_DW 4
753+#define WF_LWTBL_ANT_ID5_ADDR 16
754+#define WF_LWTBL_ANT_ID5_MASK \
755+ 0x00038000 // 17-15
756+#define WF_LWTBL_ANT_ID5_SHIFT 15
757+#define WF_LWTBL_ANT_ID6_DW 4
758+#define WF_LWTBL_ANT_ID6_ADDR 16
759+#define WF_LWTBL_ANT_ID6_MASK \
760+ 0x001c0000 // 20-18
761+#define WF_LWTBL_ANT_ID6_SHIFT 18
762+#define WF_LWTBL_ANT_ID7_DW 4
763+#define WF_LWTBL_ANT_ID7_ADDR 16
764+#define WF_LWTBL_ANT_ID7_MASK \
765+ 0x00e00000 // 23-21
766+#define WF_LWTBL_ANT_ID7_SHIFT 21
767+#define WF_LWTBL_PE_DW 4
768+#define WF_LWTBL_PE_ADDR 16
769+#define WF_LWTBL_PE_MASK \
770+ 0x03000000 // 25-24
771+#define WF_LWTBL_PE_SHIFT 24
772+#define WF_LWTBL_DIS_RHTR_DW 4
773+#define WF_LWTBL_DIS_RHTR_ADDR 16
774+#define WF_LWTBL_DIS_RHTR_MASK \
775+ 0x04000000 // 26-26
776+#define WF_LWTBL_DIS_RHTR_SHIFT 26
777+#define WF_LWTBL_LDPC_HT_DW 4
778+#define WF_LWTBL_LDPC_HT_ADDR 16
779+#define WF_LWTBL_LDPC_HT_MASK \
780+ 0x08000000 // 27-27
781+#define WF_LWTBL_LDPC_HT_SHIFT 27
782+#define WF_LWTBL_LDPC_VHT_DW 4
783+#define WF_LWTBL_LDPC_VHT_ADDR 16
784+#define WF_LWTBL_LDPC_VHT_MASK \
785+ 0x10000000 // 28-28
786+#define WF_LWTBL_LDPC_VHT_SHIFT 28
787+#define WF_LWTBL_LDPC_HE_DW 4
788+#define WF_LWTBL_LDPC_HE_ADDR 16
789+#define WF_LWTBL_LDPC_HE_MASK \
790+ 0x20000000 // 29-29
791+#define WF_LWTBL_LDPC_HE_SHIFT 29
792+#define WF_LWTBL_LDPC_EHT_DW 4
793+#define WF_LWTBL_LDPC_EHT_ADDR 16
794+#define WF_LWTBL_LDPC_EHT_MASK \
795+ 0x40000000 // 30-30
796+#define WF_LWTBL_LDPC_EHT_SHIFT 30
797+// DW5
798+#define WF_LWTBL_AF_DW 5
799+#define WF_LWTBL_AF_ADDR 20
800+#define WF_LWTBL_AF_MASK \
801+ 0x00000007 // 2- 0
802+#define WF_LWTBL_AF_SHIFT 0
803+#define WF_LWTBL_AF_HE_DW 5
804+#define WF_LWTBL_AF_HE_ADDR 20
805+#define WF_LWTBL_AF_HE_MASK \
806+ 0x00000018 // 4- 3
807+#define WF_LWTBL_AF_HE_SHIFT 3
808+#define WF_LWTBL_RTS_DW 5
809+#define WF_LWTBL_RTS_ADDR 20
810+#define WF_LWTBL_RTS_MASK \
811+ 0x00000020 // 5- 5
812+#define WF_LWTBL_RTS_SHIFT 5
813+#define WF_LWTBL_SMPS_DW 5
814+#define WF_LWTBL_SMPS_ADDR 20
815+#define WF_LWTBL_SMPS_MASK \
816+ 0x00000040 // 6- 6
817+#define WF_LWTBL_SMPS_SHIFT 6
818+#define WF_LWTBL_DYN_BW_DW 5
819+#define WF_LWTBL_DYN_BW_ADDR 20
820+#define WF_LWTBL_DYN_BW_MASK \
821+ 0x00000080 // 7- 7
822+#define WF_LWTBL_DYN_BW_SHIFT 7
823+#define WF_LWTBL_MMSS_DW 5
824+#define WF_LWTBL_MMSS_ADDR 20
825+#define WF_LWTBL_MMSS_MASK \
826+ 0x00000700 // 10- 8
827+#define WF_LWTBL_MMSS_SHIFT 8
828+#define WF_LWTBL_USR_DW 5
829+#define WF_LWTBL_USR_ADDR 20
830+#define WF_LWTBL_USR_MASK \
831+ 0x00000800 // 11-11
832+#define WF_LWTBL_USR_SHIFT 11
833+#define WF_LWTBL_SR_R_DW 5
834+#define WF_LWTBL_SR_R_ADDR 20
835+#define WF_LWTBL_SR_R_MASK \
836+ 0x00007000 // 14-12
837+#define WF_LWTBL_SR_R_SHIFT 12
838+#define WF_LWTBL_SR_ABORT_DW 5
839+#define WF_LWTBL_SR_ABORT_ADDR 20
840+#define WF_LWTBL_SR_ABORT_MASK \
841+ 0x00008000 // 15-15
842+#define WF_LWTBL_SR_ABORT_SHIFT 15
843+#define WF_LWTBL_TX_POWER_OFFSET_DW 5
844+#define WF_LWTBL_TX_POWER_OFFSET_ADDR 20
845+#define WF_LWTBL_TX_POWER_OFFSET_MASK \
846+ 0x003f0000 // 21-16
847+#define WF_LWTBL_TX_POWER_OFFSET_SHIFT 16
848+#define WF_LWTBL_LTF_EHT_DW 5
849+#define WF_LWTBL_LTF_EHT_ADDR 20
850+#define WF_LWTBL_LTF_EHT_MASK \
851+ 0x00c00000 // 23-22
852+#define WF_LWTBL_LTF_EHT_SHIFT 22
853+#define WF_LWTBL_GI_EHT_DW 5
854+#define WF_LWTBL_GI_EHT_ADDR 20
855+#define WF_LWTBL_GI_EHT_MASK \
856+ 0x03000000 // 25-24
857+#define WF_LWTBL_GI_EHT_SHIFT 24
858+#define WF_LWTBL_DOPPL_DW 5
859+#define WF_LWTBL_DOPPL_ADDR 20
860+#define WF_LWTBL_DOPPL_MASK \
861+ 0x04000000 // 26-26
862+#define WF_LWTBL_DOPPL_SHIFT 26
863+#define WF_LWTBL_TXOP_PS_CAP_DW 5
864+#define WF_LWTBL_TXOP_PS_CAP_ADDR 20
865+#define WF_LWTBL_TXOP_PS_CAP_MASK \
866+ 0x08000000 // 27-27
867+#define WF_LWTBL_TXOP_PS_CAP_SHIFT 27
868+#define WF_LWTBL_DU_I_PSM_DW 5
869+#define WF_LWTBL_DU_I_PSM_ADDR 20
870+#define WF_LWTBL_DU_I_PSM_MASK \
871+ 0x10000000 // 28-28
872+#define WF_LWTBL_DU_I_PSM_SHIFT 28
873+#define WF_LWTBL_I_PSM_DW 5
874+#define WF_LWTBL_I_PSM_ADDR 20
875+#define WF_LWTBL_I_PSM_MASK \
876+ 0x20000000 // 29-29
877+#define WF_LWTBL_I_PSM_SHIFT 29
878+#define WF_LWTBL_PSM_DW 5
879+#define WF_LWTBL_PSM_ADDR 20
880+#define WF_LWTBL_PSM_MASK \
881+ 0x40000000 // 30-30
882+#define WF_LWTBL_PSM_SHIFT 30
883+#define WF_LWTBL_SKIP_TX_DW 5
884+#define WF_LWTBL_SKIP_TX_ADDR 20
885+#define WF_LWTBL_SKIP_TX_MASK \
886+ 0x80000000 // 31-31
887+#define WF_LWTBL_SKIP_TX_SHIFT 31
888+// DW6
889+#define WF_LWTBL_CBRN_DW 6
890+#define WF_LWTBL_CBRN_ADDR 24
891+#define WF_LWTBL_CBRN_MASK \
892+ 0x00000007 // 2- 0
893+#define WF_LWTBL_CBRN_SHIFT 0
894+#define WF_LWTBL_DBNSS_EN_DW 6
895+#define WF_LWTBL_DBNSS_EN_ADDR 24
896+#define WF_LWTBL_DBNSS_EN_MASK \
897+ 0x00000008 // 3- 3
898+#define WF_LWTBL_DBNSS_EN_SHIFT 3
899+#define WF_LWTBL_BAF_EN_DW 6
900+#define WF_LWTBL_BAF_EN_ADDR 24
901+#define WF_LWTBL_BAF_EN_MASK \
902+ 0x00000010 // 4- 4
903+#define WF_LWTBL_BAF_EN_SHIFT 4
904+#define WF_LWTBL_RDGBA_DW 6
905+#define WF_LWTBL_RDGBA_ADDR 24
906+#define WF_LWTBL_RDGBA_MASK \
907+ 0x00000020 // 5- 5
908+#define WF_LWTBL_RDGBA_SHIFT 5
909+#define WF_LWTBL_R_DW 6
910+#define WF_LWTBL_R_ADDR 24
911+#define WF_LWTBL_R_MASK \
912+ 0x00000040 // 6- 6
913+#define WF_LWTBL_R_SHIFT 6
914+#define WF_LWTBL_SPE_IDX_DW 6
915+#define WF_LWTBL_SPE_IDX_ADDR 24
916+#define WF_LWTBL_SPE_IDX_MASK \
917+ 0x00000f80 // 11- 7
918+#define WF_LWTBL_SPE_IDX_SHIFT 7
919+#define WF_LWTBL_G2_DW 6
920+#define WF_LWTBL_G2_ADDR 24
921+#define WF_LWTBL_G2_MASK \
922+ 0x00001000 // 12-12
923+#define WF_LWTBL_G2_SHIFT 12
924+#define WF_LWTBL_G4_DW 6
925+#define WF_LWTBL_G4_ADDR 24
926+#define WF_LWTBL_G4_MASK \
927+ 0x00002000 // 13-13
928+#define WF_LWTBL_G4_SHIFT 13
929+#define WF_LWTBL_G8_DW 6
930+#define WF_LWTBL_G8_ADDR 24
931+#define WF_LWTBL_G8_MASK \
932+ 0x00004000 // 14-14
933+#define WF_LWTBL_G8_SHIFT 14
934+#define WF_LWTBL_G16_DW 6
935+#define WF_LWTBL_G16_ADDR 24
936+#define WF_LWTBL_G16_MASK \
937+ 0x00008000 // 15-15
938+#define WF_LWTBL_G16_SHIFT 15
939+#define WF_LWTBL_G2_LTF_DW 6
940+#define WF_LWTBL_G2_LTF_ADDR 24
941+#define WF_LWTBL_G2_LTF_MASK \
942+ 0x00030000 // 17-16
943+#define WF_LWTBL_G2_LTF_SHIFT 16
944+#define WF_LWTBL_G4_LTF_DW 6
945+#define WF_LWTBL_G4_LTF_ADDR 24
946+#define WF_LWTBL_G4_LTF_MASK \
947+ 0x000c0000 // 19-18
948+#define WF_LWTBL_G4_LTF_SHIFT 18
949+#define WF_LWTBL_G8_LTF_DW 6
950+#define WF_LWTBL_G8_LTF_ADDR 24
951+#define WF_LWTBL_G8_LTF_MASK \
952+ 0x00300000 // 21-20
953+#define WF_LWTBL_G8_LTF_SHIFT 20
954+#define WF_LWTBL_G16_LTF_DW 6
955+#define WF_LWTBL_G16_LTF_ADDR 24
956+#define WF_LWTBL_G16_LTF_MASK \
957+ 0x00c00000 // 23-22
958+#define WF_LWTBL_G16_LTF_SHIFT 22
959+#define WF_LWTBL_G2_HE_DW 6
960+#define WF_LWTBL_G2_HE_ADDR 24
961+#define WF_LWTBL_G2_HE_MASK \
962+ 0x03000000 // 25-24
963+#define WF_LWTBL_G2_HE_SHIFT 24
964+#define WF_LWTBL_G4_HE_DW 6
965+#define WF_LWTBL_G4_HE_ADDR 24
966+#define WF_LWTBL_G4_HE_MASK \
967+ 0x0c000000 // 27-26
968+#define WF_LWTBL_G4_HE_SHIFT 26
969+#define WF_LWTBL_G8_HE_DW 6
970+#define WF_LWTBL_G8_HE_ADDR 24
971+#define WF_LWTBL_G8_HE_MASK \
972+ 0x30000000 // 29-28
973+#define WF_LWTBL_G8_HE_SHIFT 28
974+#define WF_LWTBL_G16_HE_DW 6
975+#define WF_LWTBL_G16_HE_ADDR 24
976+#define WF_LWTBL_G16_HE_MASK \
977+ 0xc0000000 // 31-30
978+#define WF_LWTBL_G16_HE_SHIFT 30
979+// DW7
980+#define WF_LWTBL_BA_WIN_SIZE0_DW 7
981+#define WF_LWTBL_BA_WIN_SIZE0_ADDR 28
982+#define WF_LWTBL_BA_WIN_SIZE0_MASK \
983+ 0x0000000f // 3- 0
984+#define WF_LWTBL_BA_WIN_SIZE0_SHIFT 0
985+#define WF_LWTBL_BA_WIN_SIZE1_DW 7
986+#define WF_LWTBL_BA_WIN_SIZE1_ADDR 28
987+#define WF_LWTBL_BA_WIN_SIZE1_MASK \
988+ 0x000000f0 // 7- 4
989+#define WF_LWTBL_BA_WIN_SIZE1_SHIFT 4
990+#define WF_LWTBL_BA_WIN_SIZE2_DW 7
991+#define WF_LWTBL_BA_WIN_SIZE2_ADDR 28
992+#define WF_LWTBL_BA_WIN_SIZE2_MASK \
993+ 0x00000f00 // 11- 8
994+#define WF_LWTBL_BA_WIN_SIZE2_SHIFT 8
995+#define WF_LWTBL_BA_WIN_SIZE3_DW 7
996+#define WF_LWTBL_BA_WIN_SIZE3_ADDR 28
997+#define WF_LWTBL_BA_WIN_SIZE3_MASK \
998+ 0x0000f000 // 15-12
999+#define WF_LWTBL_BA_WIN_SIZE3_SHIFT 12
1000+#define WF_LWTBL_BA_WIN_SIZE4_DW 7
1001+#define WF_LWTBL_BA_WIN_SIZE4_ADDR 28
1002+#define WF_LWTBL_BA_WIN_SIZE4_MASK \
1003+ 0x000f0000 // 19-16
1004+#define WF_LWTBL_BA_WIN_SIZE4_SHIFT 16
1005+#define WF_LWTBL_BA_WIN_SIZE5_DW 7
1006+#define WF_LWTBL_BA_WIN_SIZE5_ADDR 28
1007+#define WF_LWTBL_BA_WIN_SIZE5_MASK \
1008+ 0x00f00000 // 23-20
1009+#define WF_LWTBL_BA_WIN_SIZE5_SHIFT 20
1010+#define WF_LWTBL_BA_WIN_SIZE6_DW 7
1011+#define WF_LWTBL_BA_WIN_SIZE6_ADDR 28
1012+#define WF_LWTBL_BA_WIN_SIZE6_MASK \
1013+ 0x0f000000 // 27-24
1014+#define WF_LWTBL_BA_WIN_SIZE6_SHIFT 24
1015+#define WF_LWTBL_BA_WIN_SIZE7_DW 7
1016+#define WF_LWTBL_BA_WIN_SIZE7_ADDR 28
1017+#define WF_LWTBL_BA_WIN_SIZE7_MASK \
1018+ 0xf0000000 // 31-28
1019+#define WF_LWTBL_BA_WIN_SIZE7_SHIFT 28
1020+// DW8
1021+#define WF_LWTBL_AC0_RTS_FAIL_CNT_DW 8
1022+#define WF_LWTBL_AC0_RTS_FAIL_CNT_ADDR 32
1023+#define WF_LWTBL_AC0_RTS_FAIL_CNT_MASK \
1024+ 0x0000001f // 4- 0
1025+#define WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT 0
1026+#define WF_LWTBL_AC1_RTS_FAIL_CNT_DW 8
1027+#define WF_LWTBL_AC1_RTS_FAIL_CNT_ADDR 32
1028+#define WF_LWTBL_AC1_RTS_FAIL_CNT_MASK \
1029+ 0x000003e0 // 9- 5
1030+#define WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT 5
1031+#define WF_LWTBL_AC2_RTS_FAIL_CNT_DW 8
1032+#define WF_LWTBL_AC2_RTS_FAIL_CNT_ADDR 32
1033+#define WF_LWTBL_AC2_RTS_FAIL_CNT_MASK \
1034+ 0x00007c00 // 14-10
1035+#define WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT 10
1036+#define WF_LWTBL_AC3_RTS_FAIL_CNT_DW 8
1037+#define WF_LWTBL_AC3_RTS_FAIL_CNT_ADDR 32
1038+#define WF_LWTBL_AC3_RTS_FAIL_CNT_MASK \
1039+ 0x000f8000 // 19-15
1040+#define WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT 15
1041+#define WF_LWTBL_PARTIAL_AID_DW 8
1042+#define WF_LWTBL_PARTIAL_AID_ADDR 32
1043+#define WF_LWTBL_PARTIAL_AID_MASK \
1044+ 0x1ff00000 // 28-20
1045+#define WF_LWTBL_PARTIAL_AID_SHIFT 20
1046+#define WF_LWTBL_CHK_PER_DW 8
1047+#define WF_LWTBL_CHK_PER_ADDR 32
1048+#define WF_LWTBL_CHK_PER_MASK \
1049+ 0x80000000 // 31-31
1050+#define WF_LWTBL_CHK_PER_SHIFT 31
1051+// DW9
1052+#define WF_LWTBL_RX_AVG_MPDU_SIZE_DW 9
1053+#define WF_LWTBL_RX_AVG_MPDU_SIZE_ADDR 36
1054+#define WF_LWTBL_RX_AVG_MPDU_SIZE_MASK \
1055+ 0x00003fff // 13- 0
1056+#define WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT 0
1057+#define WF_LWTBL_PRITX_SW_MODE_DW 9
1058+#define WF_LWTBL_PRITX_SW_MODE_ADDR 36
1059+#define WF_LWTBL_PRITX_SW_MODE_MASK \
1060+ 0x00008000 // 15-15
1061+#define WF_LWTBL_PRITX_SW_MODE_SHIFT 15
1062+#define WF_LWTBL_PRITX_ERSU_DW 9
1063+#define WF_LWTBL_PRITX_ERSU_ADDR 36
1064+#define WF_LWTBL_PRITX_ERSU_MASK \
1065+ 0x00010000 // 16-16
1066+#define WF_LWTBL_PRITX_ERSU_SHIFT 16
1067+#define WF_LWTBL_PRITX_PLR_DW 9
1068+#define WF_LWTBL_PRITX_PLR_ADDR 36
1069+#define WF_LWTBL_PRITX_PLR_MASK \
1070+ 0x00020000 // 17-17
1071+#define WF_LWTBL_PRITX_PLR_SHIFT 17
1072+#define WF_LWTBL_PRITX_DCM_DW 9
1073+#define WF_LWTBL_PRITX_DCM_ADDR 36
1074+#define WF_LWTBL_PRITX_DCM_MASK \
1075+ 0x00040000 // 18-18
1076+#define WF_LWTBL_PRITX_DCM_SHIFT 18
1077+#define WF_LWTBL_PRITX_ER106T_DW 9
1078+#define WF_LWTBL_PRITX_ER106T_ADDR 36
1079+#define WF_LWTBL_PRITX_ER106T_MASK \
1080+ 0x00080000 // 19-19
1081+#define WF_LWTBL_PRITX_ER106T_SHIFT 19
1082+#define WF_LWTBL_FCAP_DW 9
1083+#define WF_LWTBL_FCAP_ADDR 36
1084+#define WF_LWTBL_FCAP_MASK \
1085+ 0x00700000 // 22-20
1086+#define WF_LWTBL_FCAP_SHIFT 20
1087+#define WF_LWTBL_MPDU_FAIL_CNT_DW 9
1088+#define WF_LWTBL_MPDU_FAIL_CNT_ADDR 36
1089+#define WF_LWTBL_MPDU_FAIL_CNT_MASK \
1090+ 0x03800000 // 25-23
1091+#define WF_LWTBL_MPDU_FAIL_CNT_SHIFT 23
1092+#define WF_LWTBL_MPDU_OK_CNT_DW 9
1093+#define WF_LWTBL_MPDU_OK_CNT_ADDR 36
1094+#define WF_LWTBL_MPDU_OK_CNT_MASK \
1095+ 0x1c000000 // 28-26
1096+#define WF_LWTBL_MPDU_OK_CNT_SHIFT 26
1097+#define WF_LWTBL_RATE_IDX_DW 9
1098+#define WF_LWTBL_RATE_IDX_ADDR 36
1099+#define WF_LWTBL_RATE_IDX_MASK \
1100+ 0xe0000000 // 31-29
1101+#define WF_LWTBL_RATE_IDX_SHIFT 29
1102+// DW10
1103+#define WF_LWTBL_RATE1_DW 10
1104+#define WF_LWTBL_RATE1_ADDR 40
1105+#define WF_LWTBL_RATE1_MASK \
1106+ 0x00007fff // 14- 0
1107+#define WF_LWTBL_RATE1_SHIFT 0
1108+#define WF_LWTBL_RATE2_DW 10
1109+#define WF_LWTBL_RATE2_ADDR 40
1110+#define WF_LWTBL_RATE2_MASK \
1111+ 0x7fff0000 // 30-16
1112+#define WF_LWTBL_RATE2_SHIFT 16
1113+// DW11
1114+#define WF_LWTBL_RATE3_DW 11
1115+#define WF_LWTBL_RATE3_ADDR 44
1116+#define WF_LWTBL_RATE3_MASK \
1117+ 0x00007fff // 14- 0
1118+#define WF_LWTBL_RATE3_SHIFT 0
1119+#define WF_LWTBL_RATE4_DW 11
1120+#define WF_LWTBL_RATE4_ADDR 44
1121+#define WF_LWTBL_RATE4_MASK \
1122+ 0x7fff0000 // 30-16
1123+#define WF_LWTBL_RATE4_SHIFT 16
1124+// DW12
1125+#define WF_LWTBL_RATE5_DW 12
1126+#define WF_LWTBL_RATE5_ADDR 48
1127+#define WF_LWTBL_RATE5_MASK \
1128+ 0x00007fff // 14- 0
1129+#define WF_LWTBL_RATE5_SHIFT 0
1130+#define WF_LWTBL_RATE6_DW 12
1131+#define WF_LWTBL_RATE6_ADDR 48
1132+#define WF_LWTBL_RATE6_MASK \
1133+ 0x7fff0000 // 30-16
1134+#define WF_LWTBL_RATE6_SHIFT 16
1135+// DW13
1136+#define WF_LWTBL_RATE7_DW 13
1137+#define WF_LWTBL_RATE7_ADDR 52
1138+#define WF_LWTBL_RATE7_MASK \
1139+ 0x00007fff // 14- 0
1140+#define WF_LWTBL_RATE7_SHIFT 0
1141+#define WF_LWTBL_RATE8_DW 13
1142+#define WF_LWTBL_RATE8_ADDR 52
1143+#define WF_LWTBL_RATE8_MASK \
1144+ 0x7fff0000 // 30-16
1145+#define WF_LWTBL_RATE8_SHIFT 16
1146+// DW14
1147+#define WF_LWTBL_RATE1_TX_CNT_DW 14
1148+#define WF_LWTBL_RATE1_TX_CNT_ADDR 56
1149+#define WF_LWTBL_RATE1_TX_CNT_MASK \
1150+ 0x0000ffff // 15- 0
1151+#define WF_LWTBL_RATE1_TX_CNT_SHIFT 0
1152+#define WF_LWTBL_CIPHER_SUIT_IGTK_DW 14
1153+#define WF_LWTBL_CIPHER_SUIT_IGTK_ADDR 56
1154+#define WF_LWTBL_CIPHER_SUIT_IGTK_MASK \
1155+ 0x00003000 // 13-12
1156+#define WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT 12
1157+#define WF_LWTBL_CIPHER_SUIT_BIGTK_DW 14
1158+#define WF_LWTBL_CIPHER_SUIT_BIGTK_ADDR 56
1159+#define WF_LWTBL_CIPHER_SUIT_BIGTK_MASK \
1160+ 0x0000c000 // 15-14
1161+#define WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT 14
1162+#define WF_LWTBL_RATE1_FAIL_CNT_DW 14
1163+#define WF_LWTBL_RATE1_FAIL_CNT_ADDR 56
1164+#define WF_LWTBL_RATE1_FAIL_CNT_MASK \
1165+ 0xffff0000 // 31-16
1166+#define WF_LWTBL_RATE1_FAIL_CNT_SHIFT 16
1167+// DW15
1168+#define WF_LWTBL_RATE2_OK_CNT_DW 15
1169+#define WF_LWTBL_RATE2_OK_CNT_ADDR 60
1170+#define WF_LWTBL_RATE2_OK_CNT_MASK \
1171+ 0x0000ffff // 15- 0
1172+#define WF_LWTBL_RATE2_OK_CNT_SHIFT 0
1173+#define WF_LWTBL_RATE3_OK_CNT_DW 15
1174+#define WF_LWTBL_RATE3_OK_CNT_ADDR 60
1175+#define WF_LWTBL_RATE3_OK_CNT_MASK \
1176+ 0xffff0000 // 31-16
1177+#define WF_LWTBL_RATE3_OK_CNT_SHIFT 16
1178+// DW16
1179+#define WF_LWTBL_CURRENT_BW_TX_CNT_DW 16
1180+#define WF_LWTBL_CURRENT_BW_TX_CNT_ADDR 64
1181+#define WF_LWTBL_CURRENT_BW_TX_CNT_MASK \
1182+ 0x0000ffff // 15- 0
1183+#define WF_LWTBL_CURRENT_BW_TX_CNT_SHIFT 0
1184+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_DW 16
1185+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_ADDR 64
1186+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_MASK \
1187+ 0xffff0000 // 31-16
1188+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_SHIFT 16
1189+// DW17
1190+#define WF_LWTBL_OTHER_BW_TX_CNT_DW 17
1191+#define WF_LWTBL_OTHER_BW_TX_CNT_ADDR 68
1192+#define WF_LWTBL_OTHER_BW_TX_CNT_MASK \
1193+ 0x0000ffff // 15- 0
1194+#define WF_LWTBL_OTHER_BW_TX_CNT_SHIFT 0
1195+#define WF_LWTBL_OTHER_BW_FAIL_CNT_DW 17
1196+#define WF_LWTBL_OTHER_BW_FAIL_CNT_ADDR 68
1197+#define WF_LWTBL_OTHER_BW_FAIL_CNT_MASK \
1198+ 0xffff0000 // 31-16
1199+#define WF_LWTBL_OTHER_BW_FAIL_CNT_SHIFT 16
1200+// DW18
1201+#define WF_LWTBL_RTS_OK_CNT_DW 18
1202+#define WF_LWTBL_RTS_OK_CNT_ADDR 72
1203+#define WF_LWTBL_RTS_OK_CNT_MASK \
1204+ 0x0000ffff // 15- 0
1205+#define WF_LWTBL_RTS_OK_CNT_SHIFT 0
1206+#define WF_LWTBL_RTS_FAIL_CNT_DW 18
1207+#define WF_LWTBL_RTS_FAIL_CNT_ADDR 72
1208+#define WF_LWTBL_RTS_FAIL_CNT_MASK \
1209+ 0xffff0000 // 31-16
1210+#define WF_LWTBL_RTS_FAIL_CNT_SHIFT 16
1211+// DW19
1212+#define WF_LWTBL_DATA_RETRY_CNT_DW 19
1213+#define WF_LWTBL_DATA_RETRY_CNT_ADDR 76
1214+#define WF_LWTBL_DATA_RETRY_CNT_MASK \
1215+ 0x0000ffff // 15- 0
1216+#define WF_LWTBL_DATA_RETRY_CNT_SHIFT 0
1217+#define WF_LWTBL_MGNT_RETRY_CNT_DW 19
1218+#define WF_LWTBL_MGNT_RETRY_CNT_ADDR 76
1219+#define WF_LWTBL_MGNT_RETRY_CNT_MASK \
1220+ 0xffff0000 // 31-16
1221+#define WF_LWTBL_MGNT_RETRY_CNT_SHIFT 16
1222+// DW20
1223+#define WF_LWTBL_AC0_CTT_CDT_CRB_DW 20
1224+#define WF_LWTBL_AC0_CTT_CDT_CRB_ADDR 80
1225+#define WF_LWTBL_AC0_CTT_CDT_CRB_MASK \
1226+ 0xffffffff // 31- 0
1227+#define WF_LWTBL_AC0_CTT_CDT_CRB_SHIFT 0
1228+// DW21
1229+// DO NOT process repeat field(adm[0])
1230+// DW22
1231+#define WF_LWTBL_AC1_CTT_CDT_CRB_DW 22
1232+#define WF_LWTBL_AC1_CTT_CDT_CRB_ADDR 88
1233+#define WF_LWTBL_AC1_CTT_CDT_CRB_MASK \
1234+ 0xffffffff // 31- 0
1235+#define WF_LWTBL_AC1_CTT_CDT_CRB_SHIFT 0
1236+// DW23
1237+// DO NOT process repeat field(adm[1])
1238+// DW24
1239+#define WF_LWTBL_AC2_CTT_CDT_CRB_DW 24
1240+#define WF_LWTBL_AC2_CTT_CDT_CRB_ADDR 96
1241+#define WF_LWTBL_AC2_CTT_CDT_CRB_MASK \
1242+ 0xffffffff // 31- 0
1243+#define WF_LWTBL_AC2_CTT_CDT_CRB_SHIFT 0
1244+// DW25
1245+// DO NOT process repeat field(adm[2])
1246+// DW26
1247+#define WF_LWTBL_AC3_CTT_CDT_CRB_DW 26
1248+#define WF_LWTBL_AC3_CTT_CDT_CRB_ADDR 104
1249+#define WF_LWTBL_AC3_CTT_CDT_CRB_MASK \
1250+ 0xffffffff // 31- 0
1251+#define WF_LWTBL_AC3_CTT_CDT_CRB_SHIFT 0
1252+// DW27
1253+// DO NOT process repeat field(adm[3])
1254+// DW28
1255+#define WF_LWTBL_RELATED_IDX0_DW 28
1256+#define WF_LWTBL_RELATED_IDX0_ADDR 112
1257+#define WF_LWTBL_RELATED_IDX0_MASK \
1258+ 0x00000fff // 11- 0
1259+#define WF_LWTBL_RELATED_IDX0_SHIFT 0
1260+#define WF_LWTBL_RELATED_BAND0_DW 28
1261+#define WF_LWTBL_RELATED_BAND0_ADDR 112
1262+#define WF_LWTBL_RELATED_BAND0_MASK \
1263+ 0x00003000 // 13-12
1264+#define WF_LWTBL_RELATED_BAND0_SHIFT 12
1265+#define WF_LWTBL_PRIMARY_MLD_BAND_DW 28
1266+#define WF_LWTBL_PRIMARY_MLD_BAND_ADDR 112
1267+#define WF_LWTBL_PRIMARY_MLD_BAND_MASK \
1268+ 0x0000c000 // 15-14
1269+#define WF_LWTBL_PRIMARY_MLD_BAND_SHIFT 14
1270+#define WF_LWTBL_RELATED_IDX1_DW 28
1271+#define WF_LWTBL_RELATED_IDX1_ADDR 112
1272+#define WF_LWTBL_RELATED_IDX1_MASK \
1273+ 0x0fff0000 // 27-16
1274+#define WF_LWTBL_RELATED_IDX1_SHIFT 16
1275+#define WF_LWTBL_RELATED_BAND1_DW 28
1276+#define WF_LWTBL_RELATED_BAND1_ADDR 112
1277+#define WF_LWTBL_RELATED_BAND1_MASK \
1278+ 0x30000000 // 29-28
1279+#define WF_LWTBL_RELATED_BAND1_SHIFT 28
1280+#define WF_LWTBL_SECONDARY_MLD_BAND_DW 28
1281+#define WF_LWTBL_SECONDARY_MLD_BAND_ADDR 112
1282+#define WF_LWTBL_SECONDARY_MLD_BAND_MASK \
1283+ 0xc0000000 // 31-30
1284+#define WF_LWTBL_SECONDARY_MLD_BAND_SHIFT 30
1285+// DW29
1286+#define WF_LWTBL_DISPATCH_POLICY0_DW 29
1287+#define WF_LWTBL_DISPATCH_POLICY0_ADDR 116
1288+#define WF_LWTBL_DISPATCH_POLICY0_MASK \
1289+ 0x00000003 // 1- 0
1290+#define WF_LWTBL_DISPATCH_POLICY0_SHIFT 0
1291+#define WF_LWTBL_DISPATCH_POLICY1_DW 29
1292+#define WF_LWTBL_DISPATCH_POLICY1_ADDR 116
1293+#define WF_LWTBL_DISPATCH_POLICY1_MASK \
1294+ 0x0000000c // 3- 2
1295+#define WF_LWTBL_DISPATCH_POLICY1_SHIFT 2
1296+#define WF_LWTBL_DISPATCH_POLICY2_DW 29
1297+#define WF_LWTBL_DISPATCH_POLICY2_ADDR 116
1298+#define WF_LWTBL_DISPATCH_POLICY2_MASK \
1299+ 0x00000030 // 5- 4
1300+#define WF_LWTBL_DISPATCH_POLICY2_SHIFT 4
1301+#define WF_LWTBL_DISPATCH_POLICY3_DW 29
1302+#define WF_LWTBL_DISPATCH_POLICY3_ADDR 116
1303+#define WF_LWTBL_DISPATCH_POLICY3_MASK \
1304+ 0x000000c0 // 7- 6
1305+#define WF_LWTBL_DISPATCH_POLICY3_SHIFT 6
1306+#define WF_LWTBL_DISPATCH_POLICY4_DW 29
1307+#define WF_LWTBL_DISPATCH_POLICY4_ADDR 116
1308+#define WF_LWTBL_DISPATCH_POLICY4_MASK \
1309+ 0x00000300 // 9- 8
1310+#define WF_LWTBL_DISPATCH_POLICY4_SHIFT 8
1311+#define WF_LWTBL_DISPATCH_POLICY5_DW 29
1312+#define WF_LWTBL_DISPATCH_POLICY5_ADDR 116
1313+#define WF_LWTBL_DISPATCH_POLICY5_MASK \
1314+ 0x00000c00 // 11-10
1315+#define WF_LWTBL_DISPATCH_POLICY5_SHIFT 10
1316+#define WF_LWTBL_DISPATCH_POLICY6_DW 29
1317+#define WF_LWTBL_DISPATCH_POLICY6_ADDR 116
1318+#define WF_LWTBL_DISPATCH_POLICY6_MASK \
1319+ 0x00003000 // 13-12
1320+#define WF_LWTBL_DISPATCH_POLICY6_SHIFT 12
1321+#define WF_LWTBL_DISPATCH_POLICY7_DW 29
1322+#define WF_LWTBL_DISPATCH_POLICY7_ADDR 116
1323+#define WF_LWTBL_DISPATCH_POLICY7_MASK \
1324+ 0x0000c000 // 15-14
1325+#define WF_LWTBL_DISPATCH_POLICY7_SHIFT 14
1326+#define WF_LWTBL_OWN_MLD_ID_DW 29
1327+#define WF_LWTBL_OWN_MLD_ID_ADDR 116
1328+#define WF_LWTBL_OWN_MLD_ID_MASK \
1329+ 0x003f0000 // 21-16
1330+#define WF_LWTBL_OWN_MLD_ID_SHIFT 16
1331+#define WF_LWTBL_EMLSR0_DW 29
1332+#define WF_LWTBL_EMLSR0_ADDR 116
1333+#define WF_LWTBL_EMLSR0_MASK \
1334+ 0x00400000 // 22-22
1335+#define WF_LWTBL_EMLSR0_SHIFT 22
1336+#define WF_LWTBL_EMLMR0_DW 29
1337+#define WF_LWTBL_EMLMR0_ADDR 116
1338+#define WF_LWTBL_EMLMR0_MASK \
1339+ 0x00800000 // 23-23
1340+#define WF_LWTBL_EMLMR0_SHIFT 23
1341+#define WF_LWTBL_EMLSR1_DW 29
1342+#define WF_LWTBL_EMLSR1_ADDR 116
1343+#define WF_LWTBL_EMLSR1_MASK \
1344+ 0x01000000 // 24-24
1345+#define WF_LWTBL_EMLSR1_SHIFT 24
1346+#define WF_LWTBL_EMLMR1_DW 29
1347+#define WF_LWTBL_EMLMR1_ADDR 116
1348+#define WF_LWTBL_EMLMR1_MASK \
1349+ 0x02000000 // 25-25
1350+#define WF_LWTBL_EMLMR1_SHIFT 25
1351+#define WF_LWTBL_EMLSR2_DW 29
1352+#define WF_LWTBL_EMLSR2_ADDR 116
1353+#define WF_LWTBL_EMLSR2_MASK \
1354+ 0x04000000 // 26-26
1355+#define WF_LWTBL_EMLSR2_SHIFT 26
1356+#define WF_LWTBL_EMLMR2_DW 29
1357+#define WF_LWTBL_EMLMR2_ADDR 116
1358+#define WF_LWTBL_EMLMR2_MASK \
1359+ 0x08000000 // 27-27
1360+#define WF_LWTBL_EMLMR2_SHIFT 27
1361+#define WF_LWTBL_STR_BITMAP_DW 29
1362+#define WF_LWTBL_STR_BITMAP_ADDR 116
1363+#define WF_LWTBL_STR_BITMAP_MASK \
1364+ 0xe0000000 // 31-29
1365+#define WF_LWTBL_STR_BITMAP_SHIFT 29
1366+// DW30
1367+#define WF_LWTBL_DISPATCH_ORDER_DW 30
1368+#define WF_LWTBL_DISPATCH_ORDER_ADDR 120
1369+#define WF_LWTBL_DISPATCH_ORDER_MASK \
1370+ 0x0000007f // 6- 0
1371+#define WF_LWTBL_DISPATCH_ORDER_SHIFT 0
1372+#define WF_LWTBL_DISPATCH_RATIO_DW 30
1373+#define WF_LWTBL_DISPATCH_RATIO_ADDR 120
1374+#define WF_LWTBL_DISPATCH_RATIO_MASK \
1375+ 0x00003f80 // 13- 7
1376+#define WF_LWTBL_DISPATCH_RATIO_SHIFT 7
1377+#define WF_LWTBL_LINK_MGF_DW 30
1378+#define WF_LWTBL_LINK_MGF_ADDR 120
1379+#define WF_LWTBL_LINK_MGF_MASK \
1380+ 0xffff0000 // 31-16
1381+#define WF_LWTBL_LINK_MGF_SHIFT 16
1382+// DW31
1383+#define WF_LWTBL_NEGOTIATED_WINSIZE0_DW 31
1384+#define WF_LWTBL_NEGOTIATED_WINSIZE0_ADDR 124
1385+#define WF_LWTBL_NEGOTIATED_WINSIZE0_MASK \
1386+ 0x00000007 // 2- 0
1387+#define WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT 0
1388+#define WF_LWTBL_NEGOTIATED_WINSIZE1_DW 31
1389+#define WF_LWTBL_NEGOTIATED_WINSIZE1_ADDR 124
1390+#define WF_LWTBL_NEGOTIATED_WINSIZE1_MASK \
1391+ 0x00000038 // 5- 3
1392+#define WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT 3
1393+#define WF_LWTBL_NEGOTIATED_WINSIZE2_DW 31
1394+#define WF_LWTBL_NEGOTIATED_WINSIZE2_ADDR 124
1395+#define WF_LWTBL_NEGOTIATED_WINSIZE2_MASK \
1396+ 0x000001c0 // 8- 6
1397+#define WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT 6
1398+#define WF_LWTBL_NEGOTIATED_WINSIZE3_DW 31
1399+#define WF_LWTBL_NEGOTIATED_WINSIZE3_ADDR 124
1400+#define WF_LWTBL_NEGOTIATED_WINSIZE3_MASK \
1401+ 0x00000e00 // 11- 9
1402+#define WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT 9
1403+#define WF_LWTBL_NEGOTIATED_WINSIZE4_DW 31
1404+#define WF_LWTBL_NEGOTIATED_WINSIZE4_ADDR 124
1405+#define WF_LWTBL_NEGOTIATED_WINSIZE4_MASK \
1406+ 0x00007000 // 14-12
1407+#define WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT 12
1408+#define WF_LWTBL_NEGOTIATED_WINSIZE5_DW 31
1409+#define WF_LWTBL_NEGOTIATED_WINSIZE5_ADDR 124
1410+#define WF_LWTBL_NEGOTIATED_WINSIZE5_MASK \
1411+ 0x00038000 // 17-15
1412+#define WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT 15
1413+#define WF_LWTBL_NEGOTIATED_WINSIZE6_DW 31
1414+#define WF_LWTBL_NEGOTIATED_WINSIZE6_ADDR 124
1415+#define WF_LWTBL_NEGOTIATED_WINSIZE6_MASK \
1416+ 0x001c0000 // 20-18
1417+#define WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT 18
1418+#define WF_LWTBL_NEGOTIATED_WINSIZE7_DW 31
1419+#define WF_LWTBL_NEGOTIATED_WINSIZE7_ADDR 124
1420+#define WF_LWTBL_NEGOTIATED_WINSIZE7_MASK \
1421+ 0x00e00000 // 23-21
1422+#define WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT 21
1423+#define WF_LWTBL_CASCAD_DW 31
1424+#define WF_LWTBL_CASCAD_ADDR 124
1425+#define WF_LWTBL_CASCAD_MASK \
1426+ 0x02000000 // 25-25
1427+#define WF_LWTBL_CASCAD_SHIFT 25
1428+#define WF_LWTBL_ALL_ACK_DW 31
1429+#define WF_LWTBL_ALL_ACK_ADDR 124
1430+#define WF_LWTBL_ALL_ACK_MASK \
1431+ 0x04000000 // 26-26
1432+#define WF_LWTBL_ALL_ACK_SHIFT 26
1433+#define WF_LWTBL_MPDU_SIZE_DW 31
1434+#define WF_LWTBL_MPDU_SIZE_ADDR 124
1435+#define WF_LWTBL_MPDU_SIZE_MASK \
1436+ 0x18000000 // 28-27
1437+#define WF_LWTBL_MPDU_SIZE_SHIFT 27
1438+#define WF_LWTBL_BA_MODE_DW 31
1439+#define WF_LWTBL_BA_MODE_ADDR 124
1440+#define WF_LWTBL_BA_MODE_MASK \
1441+ 0xe0000000 // 31-29
1442+#define WF_LWTBL_BA_MODE_SHIFT 29
1443+// DW32
1444+#define WF_LWTBL_OM_INFO_DW 32
1445+#define WF_LWTBL_OM_INFO_ADDR 128
1446+#define WF_LWTBL_OM_INFO_MASK \
1447+ 0x00000fff // 11- 0
1448+#define WF_LWTBL_OM_INFO_SHIFT 0
1449+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_DW 32
1450+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_ADDR 128
1451+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK \
1452+ 0x00001000 // 12-12
1453+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_SHIFT 12
1454+#define WF_LWTBL_RXD_DUP_WHITE_LIST_DW 32
1455+#define WF_LWTBL_RXD_DUP_WHITE_LIST_ADDR 128
1456+#define WF_LWTBL_RXD_DUP_WHITE_LIST_MASK \
1457+ 0x01ffe000 // 24-13
1458+#define WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT 13
1459+#define WF_LWTBL_RXD_DUP_MODE_DW 32
1460+#define WF_LWTBL_RXD_DUP_MODE_ADDR 128
1461+#define WF_LWTBL_RXD_DUP_MODE_MASK \
1462+ 0x06000000 // 26-25
1463+#define WF_LWTBL_RXD_DUP_MODE_SHIFT 25
1464+#define WF_LWTBL_DROP_DW 32
1465+#define WF_LWTBL_DROP_ADDR 128
1466+#define WF_LWTBL_DROP_MASK \
1467+ 0x40000000 // 30-30
1468+#define WF_LWTBL_DROP_SHIFT 30
1469+#define WF_LWTBL_ACK_EN_DW 32
1470+#define WF_LWTBL_ACK_EN_ADDR 128
1471+#define WF_LWTBL_ACK_EN_MASK \
1472+ 0x80000000 // 31-31
1473+#define WF_LWTBL_ACK_EN_SHIFT 31
1474+// DW33
1475+#define WF_LWTBL_USER_RSSI_DW 33
1476+#define WF_LWTBL_USER_RSSI_ADDR 132
1477+#define WF_LWTBL_USER_RSSI_MASK \
1478+ 0x000001ff // 8- 0
1479+#define WF_LWTBL_USER_RSSI_SHIFT 0
1480+#define WF_LWTBL_USER_SNR_DW 33
1481+#define WF_LWTBL_USER_SNR_ADDR 132
1482+#define WF_LWTBL_USER_SNR_MASK \
1483+ 0x00007e00 // 14- 9
1484+#define WF_LWTBL_USER_SNR_SHIFT 9
1485+#define WF_LWTBL_RAPID_REACTION_RATE_DW 33
1486+#define WF_LWTBL_RAPID_REACTION_RATE_ADDR 132
1487+#define WF_LWTBL_RAPID_REACTION_RATE_MASK \
1488+ 0x0fff0000 // 27-16
1489+#define WF_LWTBL_RAPID_REACTION_RATE_SHIFT 16
1490+#define WF_LWTBL_HT_AMSDU_DW 33
1491+#define WF_LWTBL_HT_AMSDU_ADDR 132
1492+#define WF_LWTBL_HT_AMSDU_MASK \
1493+ 0x40000000 // 30-30
1494+#define WF_LWTBL_HT_AMSDU_SHIFT 30
1495+#define WF_LWTBL_AMSDU_CROSS_LG_DW 33
1496+#define WF_LWTBL_AMSDU_CROSS_LG_ADDR 132
1497+#define WF_LWTBL_AMSDU_CROSS_LG_MASK \
1498+ 0x80000000 // 31-31
1499+#define WF_LWTBL_AMSDU_CROSS_LG_SHIFT 31
1500+// DW34
1501+#define WF_LWTBL_RESP_RCPI0_DW 34
1502+#define WF_LWTBL_RESP_RCPI0_ADDR 136
1503+#define WF_LWTBL_RESP_RCPI0_MASK \
1504+ 0x000000ff // 7- 0
1505+#define WF_LWTBL_RESP_RCPI0_SHIFT 0
1506+#define WF_LWTBL_RESP_RCPI1_DW 34
1507+#define WF_LWTBL_RESP_RCPI1_ADDR 136
1508+#define WF_LWTBL_RESP_RCPI1_MASK \
1509+ 0x0000ff00 // 15- 8
1510+#define WF_LWTBL_RESP_RCPI1_SHIFT 8
1511+#define WF_LWTBL_RESP_RCPI2_DW 34
1512+#define WF_LWTBL_RESP_RCPI2_ADDR 136
1513+#define WF_LWTBL_RESP_RCPI2_MASK \
1514+ 0x00ff0000 // 23-16
1515+#define WF_LWTBL_RESP_RCPI2_SHIFT 16
1516+#define WF_LWTBL_RESP_RCPI3_DW 34
1517+#define WF_LWTBL_RESP_RCPI3_ADDR 136
1518+#define WF_LWTBL_RESP_RCPI3_MASK \
1519+ 0xff000000 // 31-24
1520+#define WF_LWTBL_RESP_RCPI3_SHIFT 24
1521+// DW35
1522+#define WF_LWTBL_SNR_RX0_DW 35
1523+#define WF_LWTBL_SNR_RX0_ADDR 140
1524+#define WF_LWTBL_SNR_RX0_MASK \
1525+ 0x0000003f // 5- 0
1526+#define WF_LWTBL_SNR_RX0_SHIFT 0
1527+#define WF_LWTBL_SNR_RX1_DW 35
1528+#define WF_LWTBL_SNR_RX1_ADDR 140
1529+#define WF_LWTBL_SNR_RX1_MASK \
1530+ 0x00000fc0 // 11- 6
1531+#define WF_LWTBL_SNR_RX1_SHIFT 6
1532+#define WF_LWTBL_SNR_RX2_DW 35
1533+#define WF_LWTBL_SNR_RX2_ADDR 140
1534+#define WF_LWTBL_SNR_RX2_MASK \
1535+ 0x0003f000 // 17-12
1536+#define WF_LWTBL_SNR_RX2_SHIFT 12
1537+#define WF_LWTBL_SNR_RX3_DW 35
1538+#define WF_LWTBL_SNR_RX3_ADDR 140
1539+#define WF_LWTBL_SNR_RX3_MASK \
1540+ 0x00fc0000 // 23-18
1541+#define WF_LWTBL_SNR_RX3_SHIFT 18
1542+
1543+/* WTBL Group - Packet Number */
1544+/* DW 2 */
1545+#define WTBL_PN0_MASK BITS(0, 7)
1546+#define WTBL_PN0_OFFSET 0
1547+#define WTBL_PN1_MASK BITS(8, 15)
1548+#define WTBL_PN1_OFFSET 8
1549+#define WTBL_PN2_MASK BITS(16, 23)
1550+#define WTBL_PN2_OFFSET 16
1551+#define WTBL_PN3_MASK BITS(24, 31)
1552+#define WTBL_PN3_OFFSET 24
1553+
1554+/* DW 3 */
1555+#define WTBL_PN4_MASK BITS(0, 7)
1556+#define WTBL_PN4_OFFSET 0
1557+#define WTBL_PN5_MASK BITS(8, 15)
1558+#define WTBL_PN5_OFFSET 8
1559+
1560+/* DW 4 */
1561+#define WTBL_BIPN0_MASK BITS(0, 7)
1562+#define WTBL_BIPN0_OFFSET 0
1563+#define WTBL_BIPN1_MASK BITS(8, 15)
1564+#define WTBL_BIPN1_OFFSET 8
1565+#define WTBL_BIPN2_MASK BITS(16, 23)
1566+#define WTBL_BIPN2_OFFSET 16
1567+#define WTBL_BIPN3_MASK BITS(24, 31)
1568+#define WTBL_BIPN3_OFFSET 24
1569+
1570+/* DW 5 */
1571+#define WTBL_BIPN4_MASK BITS(0, 7)
1572+#define WTBL_BIPN4_OFFSET 0
1573+#define WTBL_BIPN5_MASK BITS(8, 15)
1574+#define WTBL_BIPN5_OFFSET 8
1575+
1576+/* UWTBL DW 6 */
1577+#define WTBL_AMSDU_LEN_MASK BITS(0, 5)
1578+#define WTBL_AMSDU_LEN_OFFSET 0
1579+#define WTBL_AMSDU_NUM_MASK BITS(6, 10)
1580+#define WTBL_AMSDU_NUM_OFFSET 6
1581+#define WTBL_AMSDU_EN_MASK BIT(11)
1582+#define WTBL_AMSDU_EN_OFFSET 11
1583+
1584+/* LWTBL Rate field */
1585+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
1586+#define WTBL_RATE_TX_RATE_OFFSET 0
1587+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
1588+#define WTBL_RATE_TX_MODE_OFFSET 6
1589+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
1590+#define WTBL_RATE_NSTS_OFFSET 10
1591+#define WTBL_RATE_STBC_MASK BIT(14)
1592+#define WTBL_RATE_STBC_OFFSET 14
1593+
1594+/***** WTBL(LMAC) DW Offset *****/
1595+/* LMAC WTBL Group - Peer Unique Information */
1596+#define WTBL_GROUP_PEER_INFO_DW_0 0
1597+#define WTBL_GROUP_PEER_INFO_DW_1 1
1598+
1599+/* WTBL Group - TxRx Capability/Information */
1600+#define WTBL_GROUP_TRX_CAP_DW_2 2
1601+#define WTBL_GROUP_TRX_CAP_DW_3 3
1602+#define WTBL_GROUP_TRX_CAP_DW_4 4
1603+#define WTBL_GROUP_TRX_CAP_DW_5 5
1604+#define WTBL_GROUP_TRX_CAP_DW_6 6
1605+#define WTBL_GROUP_TRX_CAP_DW_7 7
1606+#define WTBL_GROUP_TRX_CAP_DW_8 8
1607+#define WTBL_GROUP_TRX_CAP_DW_9 9
1608+
1609+/* WTBL Group - Auto Rate Table*/
1610+#define WTBL_GROUP_AUTO_RATE_1_2 10
1611+#define WTBL_GROUP_AUTO_RATE_3_4 11
1612+#define WTBL_GROUP_AUTO_RATE_5_6 12
1613+#define WTBL_GROUP_AUTO_RATE_7_8 13
1614+
1615+/* WTBL Group - Tx Counter */
1616+#define WTBL_GROUP_TX_CNT_LINE_1 14
1617+#define WTBL_GROUP_TX_CNT_LINE_2 15
1618+#define WTBL_GROUP_TX_CNT_LINE_3 16
1619+#define WTBL_GROUP_TX_CNT_LINE_4 17
1620+#define WTBL_GROUP_TX_CNT_LINE_5 18
1621+#define WTBL_GROUP_TX_CNT_LINE_6 19
1622+
1623+/* WTBL Group - Admission Control Counter */
1624+#define WTBL_GROUP_ADM_CNT_LINE_1 20
1625+#define WTBL_GROUP_ADM_CNT_LINE_2 21
1626+#define WTBL_GROUP_ADM_CNT_LINE_3 22
1627+#define WTBL_GROUP_ADM_CNT_LINE_4 23
1628+#define WTBL_GROUP_ADM_CNT_LINE_5 24
1629+#define WTBL_GROUP_ADM_CNT_LINE_6 25
1630+#define WTBL_GROUP_ADM_CNT_LINE_7 26
1631+#define WTBL_GROUP_ADM_CNT_LINE_8 27
1632+
1633+/* WTBL Group -MLO Info */
1634+#define WTBL_GROUP_MLO_INFO_LINE_1 28
1635+#define WTBL_GROUP_MLO_INFO_LINE_2 29
1636+#define WTBL_GROUP_MLO_INFO_LINE_3 30
1637+
1638+/* WTBL Group -RESP Info */
1639+#define WTBL_GROUP_RESP_INFO_DW_31 31
1640+
1641+/* WTBL Group -RX DUP Info */
1642+#define WTBL_GROUP_RX_DUP_INFO_DW_32 32
1643+
1644+/* WTBL Group - Rx Statistics Counter */
1645+#define WTBL_GROUP_RX_STAT_CNT_LINE_1 33
1646+#define WTBL_GROUP_RX_STAT_CNT_LINE_2 34
1647+#define WTBL_GROUP_RX_STAT_CNT_LINE_3 35
1648+
1649+/* UWTBL Group - HW AMSDU */
1650+#define UWTBL_HW_AMSDU_DW WF_UWTBL_AMSDU_CFG_DW
1651+
1652+/* LWTBL DW 4 */
1653+#define WTBL_DIS_RHTR WF_LWTBL_DIS_RHTR_MASK
1654+
1655+/* UWTBL DW 5 */
1656+#define WTBL_KEY_LINK_DW_KEY_LOC0_MASK BITS(0, 10)
1657+#define WTBL_PSM WF_LWTBL_PSM_MASK
1658+
1659+/* Need to sync with FW define */
1660+#define INVALID_KEY_ENTRY WTBL_KEY_LINK_DW_KEY_LOC0_MASK
1661+
1662+// RATE
1663+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
1664+#define WTBL_RATE_TX_RATE_OFFSET 0
1665+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
1666+#define WTBL_RATE_TX_MODE_OFFSET 6
1667+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
1668+#define WTBL_RATE_NSTS_OFFSET 10
1669+#define WTBL_RATE_STBC_MASK BIT(14)
1670+#define WTBL_RATE_STBC_OFFSET 14
1671+
1672+/* DMA */
1673+// HOST DMA
1674+//#define CONN_INFRA_REMAPPING_OFFSET 0x64000000
1675+//#define WF_WFDMA_HOST_DMA0_BASE (0x18024000 + CONN_INFRA_REMAPPING_OFFSET)
1676+#define WF_WFDMA_HOST_DMA0_BASE 0xd4000
1677+
1678+#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR \
1679+ (WF_WFDMA_HOST_DMA0_BASE + 0x200) /* 4200 */
1680+#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR \
1681+ (WF_WFDMA_HOST_DMA0_BASE + 0X204) /* 4204 */
1682+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR \
1683+ (WF_WFDMA_HOST_DMA0_BASE + 0x208) /* 4208 */
1684+
1685+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR \
1686+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
1687+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK \
1688+ 0x00000008 /* RX_DMA_BUSY[3] */
1689+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1690+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR \
1691+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
1692+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK \
1693+ 0x00000004 /* RX_DMA_EN[2] */
1694+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1695+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR \
1696+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
1697+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK \
1698+ 0x00000002 /* TX_DMA_BUSY[1] */
1699+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1700+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR \
1701+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
1702+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK \
1703+ 0x00000001 /* TX_DMA_EN[0] */
1704+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1705+
1706+
1707+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR \
1708+ (WF_WFDMA_HOST_DMA0_BASE + 0x300) /* 4300 */
1709+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL1_ADDR \
1710+ (WF_WFDMA_HOST_DMA0_BASE + 0x304) /* 4304 */
1711+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL2_ADDR \
1712+ (WF_WFDMA_HOST_DMA0_BASE + 0x308) /* 4308 */
1713+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL3_ADDR \
1714+ (WF_WFDMA_HOST_DMA0_BASE + 0x30c) /* 430C */
1715+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR \
1716+ (WF_WFDMA_HOST_DMA0_BASE + 0x310) /* 4310 */
1717+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL1_ADDR \
1718+ (WF_WFDMA_HOST_DMA0_BASE + 0x314) /* 4314 */
1719+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL2_ADDR \
1720+ (WF_WFDMA_HOST_DMA0_BASE + 0x318) /* 4318 */
1721+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL3_ADDR \
1722+ (WF_WFDMA_HOST_DMA0_BASE + 0x31c) /* 431C */
1723+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR \
1724+ (WF_WFDMA_HOST_DMA0_BASE + 0x320) /* 4320 */
1725+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL1_ADDR \
1726+ (WF_WFDMA_HOST_DMA0_BASE + 0x324) /* 4324 */
1727+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL2_ADDR \
1728+ (WF_WFDMA_HOST_DMA0_BASE + 0x328) /* 4328 */
1729+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL3_ADDR \
1730+ (WF_WFDMA_HOST_DMA0_BASE + 0x32c) /* 432C */
1731+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR \
1732+ (WF_WFDMA_HOST_DMA0_BASE + 0x330) /* 4330 */
1733+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL1_ADDR \
1734+ (WF_WFDMA_HOST_DMA0_BASE + 0x334) /* 4334 */
1735+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL2_ADDR \
1736+ (WF_WFDMA_HOST_DMA0_BASE + 0x338) /* 4338 */
1737+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL3_ADDR \
1738+ (WF_WFDMA_HOST_DMA0_BASE + 0x33c) /* 433C */
1739+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR \
1740+ (WF_WFDMA_HOST_DMA0_BASE + 0x340) /* 4340 */
1741+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL1_ADDR \
1742+ (WF_WFDMA_HOST_DMA0_BASE + 0x344) /* 4344 */
1743+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL2_ADDR \
1744+ (WF_WFDMA_HOST_DMA0_BASE + 0x348) /* 4348 */
1745+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL3_ADDR \
1746+ (WF_WFDMA_HOST_DMA0_BASE + 0x34c) /* 434C */
1747+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR \
1748+ (WF_WFDMA_HOST_DMA0_BASE + 0x350) /* 4350 */
1749+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL1_ADDR \
1750+ (WF_WFDMA_HOST_DMA0_BASE + 0x354) /* 4354 */
1751+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL2_ADDR \
1752+ (WF_WFDMA_HOST_DMA0_BASE + 0x358) /* 4358 */
1753+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL3_ADDR \
1754+ (WF_WFDMA_HOST_DMA0_BASE + 0x35c) /* 435C */
1755+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR \
1756+ (WF_WFDMA_HOST_DMA0_BASE + 0x360) /* 4360 */
1757+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL1_ADDR \
1758+ (WF_WFDMA_HOST_DMA0_BASE + 0x364) /* 4364 */
1759+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL2_ADDR \
1760+ (WF_WFDMA_HOST_DMA0_BASE + 0x368) /* 4368 */
1761+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL3_ADDR \
1762+ (WF_WFDMA_HOST_DMA0_BASE + 0x36c) /* 436C */
1763+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR \
1764+ (WF_WFDMA_HOST_DMA0_BASE + 0x400) /* 4400 */
1765+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL1_ADDR \
1766+ (WF_WFDMA_HOST_DMA0_BASE + 0x404) /* 4404 */
1767+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL2_ADDR \
1768+ (WF_WFDMA_HOST_DMA0_BASE + 0x408) /* 4408 */
1769+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL3_ADDR \
1770+ (WF_WFDMA_HOST_DMA0_BASE + 0x40c) /* 440C */
1771+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR \
1772+ (WF_WFDMA_HOST_DMA0_BASE + 0x410) /* 4410 */
1773+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL1_ADDR \
1774+ (WF_WFDMA_HOST_DMA0_BASE + 0x414) /* 4414 */
1775+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL2_ADDR \
1776+ (WF_WFDMA_HOST_DMA0_BASE + 0x418) /* 4418 */
1777+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL3_ADDR \
1778+ (WF_WFDMA_HOST_DMA0_BASE + 0x41c) /* 441C */
1779+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR \
1780+ (WF_WFDMA_HOST_DMA0_BASE + 0x420) /* 4420 */
1781+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL1_ADDR \
1782+ (WF_WFDMA_HOST_DMA0_BASE + 0x424) /* 4424 */
1783+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL2_ADDR \
1784+ (WF_WFDMA_HOST_DMA0_BASE + 0x428) /* 4428 */
1785+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL3_ADDR \
1786+ (WF_WFDMA_HOST_DMA0_BASE + 0x42c) /* 442C */
1787+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR \
1788+ (WF_WFDMA_HOST_DMA0_BASE + 0x430) /* 4430 */
1789+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL1_ADDR \
1790+ (WF_WFDMA_HOST_DMA0_BASE + 0x434) /* 4434 */
1791+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL2_ADDR \
1792+ (WF_WFDMA_HOST_DMA0_BASE + 0x438) /* 4438 */
1793+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL3_ADDR \
1794+ (WF_WFDMA_HOST_DMA0_BASE + 0x43c) /* 443C */
1795+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR \
1796+ (WF_WFDMA_HOST_DMA0_BASE + 0x440) /* 4440 */
1797+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL1_ADDR \
1798+ (WF_WFDMA_HOST_DMA0_BASE + 0x444) /* 4444 */
1799+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL2_ADDR \
1800+ (WF_WFDMA_HOST_DMA0_BASE + 0x448) /* 4448 */
1801+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL3_ADDR \
1802+ (WF_WFDMA_HOST_DMA0_BASE + 0x44c) /* 444C */
1803+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR \
1804+ (WF_WFDMA_HOST_DMA0_BASE + 0x450) /* 4450 */
1805+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL1_ADDR \
1806+ (WF_WFDMA_HOST_DMA0_BASE + 0x454) /* 4454 */
1807+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL2_ADDR \
1808+ (WF_WFDMA_HOST_DMA0_BASE + 0x458) /* 4458 */
1809+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL3_ADDR \
1810+
1811+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR \
1812+ (WF_WFDMA_HOST_DMA0_BASE + 0x500) /* 4500 */
1813+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL1_ADDR \
1814+ (WF_WFDMA_HOST_DMA0_BASE + 0x504) /* 4504 */
1815+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL2_ADDR \
1816+ (WF_WFDMA_HOST_DMA0_BASE + 0x508) /* 4508 */
1817+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL3_ADDR \
1818+ (WF_WFDMA_HOST_DMA0_BASE + 0x50c) /* 450C */
1819+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR \
1820+ (WF_WFDMA_HOST_DMA0_BASE + 0x510) /* 4510 */
1821+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL1_ADDR \
1822+ (WF_WFDMA_HOST_DMA0_BASE + 0x514) /* 4514 */
1823+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL2_ADDR \
1824+ (WF_WFDMA_HOST_DMA0_BASE + 0x518) /* 4518 */
1825+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL3_ADDR \
1826+ (WF_WFDMA_HOST_DMA0_BASE + 0x51c) /* 451C */
1827+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR \
1828+ (WF_WFDMA_HOST_DMA0_BASE + 0x520) /* 4520 */
1829+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL1_ADDR \
1830+ (WF_WFDMA_HOST_DMA0_BASE + 0x524) /* 4524 */
1831+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL2_ADDR \
1832+ (WF_WFDMA_HOST_DMA0_BASE + 0x528) /* 4528 */
1833+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL3_ADDR \
1834+ (WF_WFDMA_HOST_DMA0_BASE + 0x52C) /* 452C */
1835+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR \
1836+ (WF_WFDMA_HOST_DMA0_BASE + 0x530) /* 4530 */
1837+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL1_ADDR \
1838+ (WF_WFDMA_HOST_DMA0_BASE + 0x534) /* 4534 */
1839+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL2_ADDR \
1840+ (WF_WFDMA_HOST_DMA0_BASE + 0x538) /* 4538 */
1841+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL3_ADDR \
1842+ (WF_WFDMA_HOST_DMA0_BASE + 0x53C) /* 453C */
1843+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR \
1844+ (WF_WFDMA_HOST_DMA0_BASE + 0x540) /* 4540 */
1845+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL1_ADDR \
1846+ (WF_WFDMA_HOST_DMA0_BASE + 0x544) /* 4544 */
1847+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL2_ADDR \
1848+ (WF_WFDMA_HOST_DMA0_BASE + 0x548) /* 4548 */
1849+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL3_ADDR \
1850+ (WF_WFDMA_HOST_DMA0_BASE + 0x54c) /* 454C */
1851+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR \
1852+ (WF_WFDMA_HOST_DMA0_BASE + 0x550) /* 4550 */
1853+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL1_ADDR \
1854+ (WF_WFDMA_HOST_DMA0_BASE + 0x554) /* 4554 */
1855+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL2_ADDR \
1856+ (WF_WFDMA_HOST_DMA0_BASE + 0x558) /* 4558 */
1857+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL3_ADDR \
1858+ (WF_WFDMA_HOST_DMA0_BASE + 0x55c) /* 455C */
1859+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR \
1860+ (WF_WFDMA_HOST_DMA0_BASE + 0x560) /* 4560 */
1861+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL1_ADDR \
1862+ (WF_WFDMA_HOST_DMA0_BASE + 0x564) /* 4564 */
1863+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL2_ADDR \
1864+ (WF_WFDMA_HOST_DMA0_BASE + 0x568) /* 4568 */
1865+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL3_ADDR \
1866+ (WF_WFDMA_HOST_DMA0_BASE + 0x56c) /* 456C */
1867+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR \
1868+ (WF_WFDMA_HOST_DMA0_BASE + 0x570) /* 4570 */
1869+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL1_ADDR \
1870+ (WF_WFDMA_HOST_DMA0_BASE + 0x574) /* 4574 */
1871+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL2_ADDR \
1872+ (WF_WFDMA_HOST_DMA0_BASE + 0x578) /* 4578 */
1873+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL3_ADDR \
1874+ (WF_WFDMA_HOST_DMA0_BASE + 0x57c) /* 457C */
1875+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR \
1876+ (WF_WFDMA_HOST_DMA0_BASE + 0x580) /* 4580 */
1877+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL1_ADDR \
1878+ (WF_WFDMA_HOST_DMA0_BASE + 0x584) /* 4584 */
1879+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL2_ADDR \
1880+ (WF_WFDMA_HOST_DMA0_BASE + 0x588) /* 4588 */
1881+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL3_ADDR \
1882+ (WF_WFDMA_HOST_DMA0_BASE + 0x58c) /* 458C */
1883+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR \
1884+ (WF_WFDMA_HOST_DMA0_BASE + 0x590) /* 4590 */
1885+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL1_ADDR \
1886+ (WF_WFDMA_HOST_DMA0_BASE + 0x594) /* 4594 */
1887+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL2_ADDR \
1888+ (WF_WFDMA_HOST_DMA0_BASE + 0x598) /* 4598 */
1889+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL3_ADDR \
1890+ (WF_WFDMA_HOST_DMA0_BASE + 0x59c) /* 459C */
1891+
1892+//MCU DMA
1893+//#define WF_WFDMA_MCU_DMA0_BASE 0x02000
1894+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1895+
1896+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1897+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1898+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1899+
1900+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
1901+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1902+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1903+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
1904+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1905+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1906+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
1907+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1908+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1909+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
1910+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1911+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1912+
1913+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1914+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x304) // 0304
1915+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x308) // 0308
1916+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x30c) // 030C
1917+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1918+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x314) // 0314
1919+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x318) // 0318
1920+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x31c) // 031C
1921+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1922+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x324) // 0324
1923+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x328) // 0328
1924+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x32c) // 032C
1925+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1926+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x334) // 0334
1927+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x338) // 0338
1928+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x33c) // 033C
1929+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1930+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x344) // 0344
1931+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x348) // 0348
1932+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x34c) // 034C
1933+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1934+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x354) // 0354
1935+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x358) // 0358
1936+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x35c) // 035C
1937+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1938+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x364) // 0364
1939+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x368) // 0368
1940+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x36c) // 036C
1941+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x370) // 0370
1942+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x374) // 0374
1943+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x378) // 0378
1944+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x37c) // 037C
1945+
1946+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1947+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x504) // 0504
1948+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x508) // 0508
1949+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x50c) // 050C
1950+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1951+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x514) // 0514
1952+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x518) // 0518
1953+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x51c) // 051C
1954+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1955+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x524) // 0524
1956+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x528) // 0528
1957+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x52C) // 052C
1958+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1959+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x534) // 0534
1960+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x538) // 0538
1961+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x53C) // 053C
1962+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1963+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x544) // 0544
1964+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x548) // 0548
1965+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x54C) // 054C
1966+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1967+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x554) // 0554
1968+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x558) // 0558
1969+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x55C) // 055C
1970+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1971+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x564) // 0564
1972+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x568) // 0568
1973+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x56c) // 056C
1974+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1975+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x574) // 0574
1976+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x578) // 0578
1977+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x57c) // 057C
1978+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1979+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x584) // 0584
1980+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x588) // 0588
1981+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x58c) // 058C
1982+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1983+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x594) // 0594
1984+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x598) // 0598
1985+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x59c) // 059C
1986+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A0) // 05A0
1987+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A4) // 05A4
1988+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A8) // 05A8
1989+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5Ac) // 05AC
1990+
1991+// MEM DMA
1992+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1993+
1994+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1995+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1996+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1997+
1998+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
1999+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
2000+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
2001+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
2002+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
2003+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
2004+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
2005+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
2006+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
2007+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
2008+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
2009+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
2010+
2011+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
2012+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x304) // 0304
2013+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x308) // 0308
2014+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x30c) // 030C
2015+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
2016+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x314) // 0314
2017+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x318) // 0318
2018+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x31c) // 031C
2019+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x320) // 0320
2020+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x324) // 0324
2021+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x328) // 0328
2022+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x32c) // 032C
2023+
2024+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
2025+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x504) // 0504
2026+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x508) // 0508
2027+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x50c) // 050C
2028+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
2029+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x514) // 0514
2030+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x518) // 0518
2031+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x51c) // 051C
2032+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x520) // 0520
2033+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x524) // 0524
2034+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x528) // 0528
2035+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x52C) // 052C
2036+
2037+/* MIB INFO */
2038+#define WF_UMIB_TOP_BASE 0x820cd000
2039+#define BN0_WF_MIB_TOP_BASE 0x820ed000
2040+#define BN1_WF_MIB_TOP_BASE 0x820fd000
2041+#define IP1_BN0_WF_MIB_TOP_BASE 0x830ed000
2042+
2043+#define WF_UMIB_TOP_B0BROCR_ADDR (WF_UMIB_TOP_BASE + 0x480) // D480
2044+#define WF_UMIB_TOP_B0BRBCR_ADDR (WF_UMIB_TOP_BASE + 0x4D0) // D4D0
2045+#define WF_UMIB_TOP_B0BRDCR_ADDR (WF_UMIB_TOP_BASE + 0x520) // D520
2046+#define WF_UMIB_TOP_B1BROCR_ADDR (WF_UMIB_TOP_BASE + 0x5B4) // D5B4
2047+#define WF_UMIB_TOP_B2BROCR_ADDR (WF_UMIB_TOP_BASE + 0x6E8) // D6E8
2048+
2049+#define BN0_WF_MIB_TOP_M0SCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x000) // D000
2050+#define BN0_WF_MIB_TOP_M0SDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x020) // D020
2051+#define BN0_WF_MIB_TOP_M0SDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x024) // D024
2052+#define BN0_WF_MIB_TOP_M0SDR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x030) // D030
2053+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
2054+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
2055+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
2056+#define BN0_WF_MIB_TOP_BTCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F8) // D4F8
2057+#define BN0_WF_MIB_TOP_RVSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6D4) // D6D4
2058+
2059+#define BN0_WF_MIB_TOP_TSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x670) // D670
2060+#define BN0_WF_MIB_TOP_TSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x67C) // D67C
2061+#define BN0_WF_MIB_TOP_TSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x680) // D680
2062+#define BN0_WF_MIB_TOP_TSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x684) // D684
2063+#define BN0_WF_MIB_TOP_TSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
2064+#define BN0_WF_MIB_TOP_TSCR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x68C) // D68C
2065+#define BN0_WF_MIB_TOP_TSCR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
2066+
2067+#define BN0_WF_MIB_TOP_TBCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6AC) // D6AC
2068+#define BN0_WF_MIB_TOP_TBCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B0) // D6B0
2069+#define BN0_WF_MIB_TOP_TBCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B4) // D6B4
2070+#define BN0_WF_MIB_TOP_TBCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B8) // D6B8
2071+#define BN0_WF_MIB_TOP_TBCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6BC) // D6BC
2072+
2073+#define BN0_WF_MIB_TOP_TDRCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6DC) // D6DC
2074+#define BN0_WF_MIB_TOP_TDRCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6E0) // D6E0
2075+#define BN0_WF_MIB_TOP_TDRCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6E4) // D6E4
2076+#define BN0_WF_MIB_TOP_TDRCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6E8) // D6E8
2077+#define BN0_WF_MIB_TOP_TDRCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6EC) // D6EC
2078+
2079+#define BN0_WF_MIB_TOP_BTSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
2080+#define BN0_WF_MIB_TOP_BTSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x5F0) // D5F0
2081+#define BN0_WF_MIB_TOP_BTSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x600) // D600
2082+#define BN0_WF_MIB_TOP_BTSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x610) // D610
2083+#define BN0_WF_MIB_TOP_BTSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x620) // D620
2084+#define BN0_WF_MIB_TOP_BTSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x73C) // D73C
2085+#define BN0_WF_MIB_TOP_BTSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x74C) // D74C
2086+
2087+#define BN0_WF_MIB_TOP_RSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x760) // D760
2088+#define BN0_WF_MIB_TOP_BSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x964) // D964
2089+#define BN0_WF_MIB_TOP_TSCR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x9AC) // D9AC
2090+
2091+#define BN0_WF_MIB_TOP_MSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F4) // D9F4
2092+#define BN0_WF_MIB_TOP_MSR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F8) // D9F8
2093+#define BN0_WF_MIB_TOP_MSR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9FC) // D9FC
2094+#define BN0_WF_MIB_TOP_MCTR5_ADDR (BN0_WF_MIB_TOP_BASE + 0xA00) // DA00
2095+#define BN0_WF_MIB_TOP_MCTR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xA04) // DA04
2096+
2097+#define BN0_WF_MIB_TOP_RSCR26_ADDR (BN0_WF_MIB_TOP_BASE + 0x904) // D904
2098+#define BN0_WF_MIB_TOP_RSCR27_ADDR (BN0_WF_MIB_TOP_BASE + 0x908) // D908
2099+#define BN0_WF_MIB_TOP_RSCR28_ADDR (BN0_WF_MIB_TOP_BASE + 0x90C) // D90C
2100+#define BN0_WF_MIB_TOP_RSCR31_ADDR (BN0_WF_MIB_TOP_BASE + 0x918) // D918
2101+#define BN0_WF_MIB_TOP_RSCR33_ADDR (BN0_WF_MIB_TOP_BASE + 0x920) // D920
2102+#define BN0_WF_MIB_TOP_RSCR35_ADDR (BN0_WF_MIB_TOP_BASE + 0x928) // D928
2103+#define BN0_WF_MIB_TOP_RSCR36_ADDR (BN0_WF_MIB_TOP_BASE + 0x92C) // D92C
2104+
2105+#define BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK 0xFFFFFFFF // AMPDU_MPDU_COUNT[31..0]
2106+#define BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK 0xFFFFFFFF // AMPDU_ACKED_COUNT[31..0]
2107+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
2108+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
2109+#define BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK 0xFFFFFFFF // RX_MDRDY_COUNT[31..0]
2110+#define BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK 0xFFFFFFFF // CCK_MDRDY_TIME[31..0]
2111+#define BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[31..0]
2112+#define BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_GREEN_MDRDY_TIME[31..0]
2113+#define BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK 0xFFFFFFFF // P_CCA_TIME[31..0]
2114+#define BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK 0xFFFFFFFF // S_CCA_TIME[31..0]
2115+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
2116+#define BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK 0xFFFFFFFF // BEACONTXCOUNT[31..0]
2117+#define BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK 0xFFFFFFFF // TX_20MHZ_CNT[31..0]
2118+#define BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK 0xFFFFFFFF // TX_40MHZ_CNT[31..0]
2119+#define BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK 0xFFFFFFFF // TX_80MHZ_CNT[31..0]
2120+#define BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK 0xFFFFFFFF // TX_160MHZ_CNT[31..0]
2121+#define BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK 0xFFFFFFFF // TX_320MHZ_CNT[31..0]
2122+#define BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK 0xFFFFFFFF // MUBF_TX_COUNT[31..0]
2123+#define BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK 0xFFFFFFFF // VEC_MISS_COUNT[31..0]
2124+#define BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK 0xFFFFFFFF // DELIMITER_FAIL_COUNT[31..0]
2125+#define BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK 0xFFFFFFFF // RX_FCS_ERROR_COUNT[31..0]
2126+#define BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK 0xFFFFFFFF // RX_FIFO_FULL_COUNT[31..0]
2127+#define BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK 0xFFFFFFFF // RX_LEN_MISMATCH[31..0]
2128+#define BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
2129+#define BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK 0xFFFFFFFF // RTSTXCOUNTn[31..0]
2130+#define BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK 0xFFFFFFFF // RTSRETRYCOUNTn[31..0]
2131+#define BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK 0xFFFFFFFF // BAMISSCOUNTn[31..0]
2132+#define BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK 0xFFFFFFFF // ACKFAILCOUNTn[31..0]
2133+#define BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK 0xFFFFFFFF // FRAMERETRYCOUNTn[31..0]
2134+#define BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK 0xFFFFFFFF // FRAMERETRY2COUNTn[31..0]
2135+#define BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK 0xFFFFFFFF // FRAMERETRY3COUNTn[31..0]
2136+
2137+/* PLE AMSDU */
2138+#define WF_PLE_TOP_BASE 0x820c0000
2139+
2140+#define WF_PLE_TOP_AMSDU_PACK_1_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e0) // 10E0
2141+#define WF_PLE_TOP_AMSDU_PACK_2_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e4) // 10E4
2142+#define WF_PLE_TOP_AMSDU_PACK_3_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e8) // 10E8
2143+#define WF_PLE_TOP_AMSDU_PACK_4_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10ec) // 10EC
2144+#define WF_PLE_TOP_AMSDU_PACK_5_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f0) // 10F0
2145+#define WF_PLE_TOP_AMSDU_PACK_6_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f4) // 10F4
2146+#define WF_PLE_TOP_AMSDU_PACK_7_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f8) // 10F8
2147+#define WF_PLE_TOP_AMSDU_PACK_8_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10fc) // 10FC
2148+
2149+/* PLE */
2150+#define WF_PLE_TOP_PBUF_CTRL_ADDR (WF_PLE_TOP_BASE + 0x04) // 0004
2151+
2152+#define WF_PLE_TOP_PG_HIF_GROUP_ADDR (WF_PLE_TOP_BASE + 0x0c) // 000C
2153+#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR (WF_PLE_TOP_BASE + 0x10) // 0010
2154+#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR (WF_PLE_TOP_BASE + 0x14) // 0014
2155+#define WF_PLE_TOP_PG_CPU_GROUP_ADDR (WF_PLE_TOP_BASE + 0x18) // 0018
2156+#define WF_PLE_TOP_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x360) // 0360
2157+
2158+#define WF_PLE_TOP_DIS_STA_MAP0_ADDR (WF_PLE_TOP_BASE + 0x100) // 0100
2159+#define WF_PLE_TOP_DIS_STA_MAP1_ADDR (WF_PLE_TOP_BASE + 0x104) // 0104
2160+#define WF_PLE_TOP_DIS_STA_MAP2_ADDR (WF_PLE_TOP_BASE + 0x108) // 0108
2161+#define WF_PLE_TOP_DIS_STA_MAP3_ADDR (WF_PLE_TOP_BASE + 0x10c) // 010C
2162+#define WF_PLE_TOP_DIS_STA_MAP4_ADDR (WF_PLE_TOP_BASE + 0x110) // 0110
2163+#define WF_PLE_TOP_DIS_STA_MAP5_ADDR (WF_PLE_TOP_BASE + 0x114) // 0114
2164+#define WF_PLE_TOP_DIS_STA_MAP6_ADDR (WF_PLE_TOP_BASE + 0x118) // 0118
2165+#define WF_PLE_TOP_DIS_STA_MAP7_ADDR (WF_PLE_TOP_BASE + 0x11c) // 011C
2166+#define WF_PLE_TOP_DIS_STA_MAP8_ADDR (WF_PLE_TOP_BASE + 0x120) // 0120
2167+
2168+#define WF_PLE_TOP_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x378) // 0378
2169+#define WF_PLE_TOP_NATIVE_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x37c) // 037C
2170+
2171+#define WF_PLE_TOP_FREEPG_CNT_ADDR (WF_PLE_TOP_BASE + 0x3a0) // 03A0
2172+#define WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PLE_TOP_BASE + 0x3a4) // 03A4
2173+#define WF_PLE_TOP_HIF_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3a8) // 03A8
2174+#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3ac) // 03AC
2175+#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3b0) // 03B0
2176+#define WF_PLE_TOP_CPU_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3b4) // 03B4
2177+
2178+#define WF_PLE_TOP_FL_QUE_CTRL_0_ADDR (WF_PLE_TOP_BASE + 0x3e0) // 03E0
2179+#define WF_PLE_TOP_FL_QUE_CTRL_1_ADDR (WF_PLE_TOP_BASE + 0x3e4) // 03E4
2180+#define WF_PLE_TOP_FL_QUE_CTRL_2_ADDR (WF_PLE_TOP_BASE + 0x3e8) // 03E8
2181+#define WF_PLE_TOP_FL_QUE_CTRL_3_ADDR (WF_PLE_TOP_BASE + 0x3ec) // 03EC
2182+
2183+#define WF_PLE_TOP_AC0_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x600) // 0600
2184+#define WF_PLE_TOP_AC0_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x604) // 0604
2185+#define WF_PLE_TOP_AC0_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x608) // 0608
2186+#define WF_PLE_TOP_AC0_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x60c) // 060C
2187+#define WF_PLE_TOP_AC0_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x610) // 0610
2188+#define WF_PLE_TOP_AC0_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x614) // 0614
2189+#define WF_PLE_TOP_AC0_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x618) // 0618
2190+#define WF_PLE_TOP_AC0_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x61c) // 061C
2191+#define WF_PLE_TOP_AC0_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x620) // 0620
2192+
2193+#define WF_PLE_TOP_AC1_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x700) // 0700
2194+#define WF_PLE_TOP_AC1_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x704) // 0704
2195+#define WF_PLE_TOP_AC1_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x708) // 0708
2196+#define WF_PLE_TOP_AC1_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x70c) // 070C
2197+#define WF_PLE_TOP_AC1_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x710) // 0710
2198+#define WF_PLE_TOP_AC1_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x714) // 0714
2199+#define WF_PLE_TOP_AC1_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x718) // 0718
2200+#define WF_PLE_TOP_AC1_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x71c) // 071C
2201+#define WF_PLE_TOP_AC1_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x720) // 0720
2202+
2203+#define WF_PLE_TOP_AC2_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x800) // 0800
2204+#define WF_PLE_TOP_AC2_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x804) // 0804
2205+#define WF_PLE_TOP_AC2_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x808) // 0808
2206+#define WF_PLE_TOP_AC2_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x80c) // 080C
2207+#define WF_PLE_TOP_AC2_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x810) // 0810
2208+#define WF_PLE_TOP_AC2_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x814) // 0814
2209+#define WF_PLE_TOP_AC2_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x818) // 0818
2210+#define WF_PLE_TOP_AC2_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x81c) // 081C
2211+#define WF_PLE_TOP_AC2_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x820) // 0820
2212+
2213+#define WF_PLE_TOP_AC3_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x900) // 0900
2214+#define WF_PLE_TOP_AC3_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x904) // 0904
2215+#define WF_PLE_TOP_AC3_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x908) // 0908
2216+#define WF_PLE_TOP_AC3_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x90c) // 090C
2217+#define WF_PLE_TOP_AC3_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x910) // 0910
2218+#define WF_PLE_TOP_AC3_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x914) // 0914
2219+#define WF_PLE_TOP_AC3_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x918) // 0918
2220+#define WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x91c) // 091C
2221+#define WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x920) // 0920
2222+
2223+#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_ADDR WF_PLE_TOP_QUEUE_EMPTY_ADDR
2224+#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_MASK 0x01000000 // ALL_AC_EMPTY[24]
2225+#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_SHFT 24
2226+
2227+#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR
2228+#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31]
2229+#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31
2230+#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR
2231+#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 // PBUF_OFFSET[25..17]
2232+#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17
2233+#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR
2234+#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF // TOTAL_PAGE_NUM[11..0]
2235+#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0
2236+
2237+#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_ADDR WF_PLE_TOP_FREEPG_CNT_ADDR
2238+#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 // FFA_CNT[27..16]
2239+#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16
2240+#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_ADDR WF_PLE_TOP_FREEPG_CNT_ADDR
2241+#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF // FREEPG_CNT[11..0]
2242+#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0
2243+
2244+#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_ADDR WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR
2245+#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 // FREEPG_TAIL[27..16]
2246+#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16
2247+#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_ADDR WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR
2248+#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF // FREEPG_HEAD[11..0]
2249+#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0
2250+
2251+#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_GROUP_ADDR
2252+#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK 0x0FFF0000 // HIF_MAX_QUOTA[27..16]
2253+#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_SHFT 16
2254+#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_GROUP_ADDR
2255+#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK 0x00000FFF // HIF_MIN_QUOTA[11..0]
2256+#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_SHFT 0
2257+
2258+#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_ADDR WF_PLE_TOP_HIF_PG_INFO_ADDR
2259+#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_MASK 0x0FFF0000 // HIF_SRC_CNT[27..16]
2260+#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_SHFT 16
2261+#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_ADDR WF_PLE_TOP_HIF_PG_INFO_ADDR
2262+#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_MASK 0x00000FFF // HIF_RSV_CNT[11..0]
2263+#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_SHFT 0
2264+
2265+#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR
2266+#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_MASK 0x0FFF0000 // HIF_WMTXD_MAX_QUOTA[27..16]
2267+#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_SHFT 16
2268+#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR
2269+#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_MASK 0x00000FFF // HIF_WMTXD_MIN_QUOTA[11..0]
2270+#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_SHFT 0
2271+
2272+#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_ADDR WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR
2273+#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_MASK 0x0FFF0000 // HIF_WMTXD_SRC_CNT[27..16]
2274+#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_SHFT 16
2275+#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_ADDR WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR
2276+#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_MASK 0x00000FFF // HIF_WMTXD_RSV_CNT[11..0]
2277+#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_SHFT 0
2278+
2279+#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR
2280+#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK 0x0FFF0000 // HIF_TXCMD_MAX_QUOTA[27..16]
2281+#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_SHFT 16
2282+#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR
2283+#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK 0x00000FFF // HIF_TXCMD_MIN_QUOTA[11..0]
2284+#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_SHFT 0
2285+
2286+#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_ADDR WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR
2287+#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK 0x0FFF0000 // HIF_TXCMD_SRC_CNT[27..16]
2288+#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_SHFT 16
2289+#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_ADDR WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR
2290+#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK 0x00000FFF // HIF_TXCMD_RSV_CNT[11..0]
2291+#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_SHFT 0
2292+
2293+#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PLE_TOP_PG_CPU_GROUP_ADDR
2294+#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 // CPU_MAX_QUOTA[27..16]
2295+#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16
2296+#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PLE_TOP_PG_CPU_GROUP_ADDR
2297+#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF // CPU_MIN_QUOTA[11..0]
2298+#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0
2299+
2300+#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_ADDR WF_PLE_TOP_CPU_PG_INFO_ADDR
2301+#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 // CPU_SRC_CNT[27..16]
2302+#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16
2303+#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_ADDR WF_PLE_TOP_CPU_PG_INFO_ADDR
2304+#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF // CPU_RSV_CNT[11..0]
2305+#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0
2306+
2307+#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR
2308+#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 // EXECUTE[31]
2309+#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31
2310+#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR
2311+#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 // Q_BUF_QID[30..24]
2312+#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
2313+#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR
2314+#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_MASK 0x00FFF000 // FL_BUFFER_ADDR[23..12]
2315+#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_SHFT 12
2316+#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR
2317+#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK 0x00000FFF // Q_BUF_WLANID[11..0]
2318+#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT 0
2319+
2320+#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_ADDR WF_PLE_TOP_FL_QUE_CTRL_1_ADDR
2321+#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_MASK 0xC0000000 // Q_BUF_TGID[31..30]
2322+#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_SHFT 30
2323+#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_ADDR WF_PLE_TOP_FL_QUE_CTRL_1_ADDR
2324+#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_MASK 0x30000000 // Q_BUF_PID[29..28]
2325+#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT 28
2326+
2327+#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PLE_TOP_FL_QUE_CTRL_2_ADDR
2328+#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 // QUEUE_TAIL_FID[27..16]
2329+#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16
2330+#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PLE_TOP_FL_QUE_CTRL_2_ADDR
2331+#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF // QUEUE_HEAD_FID[11..0]
2332+#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0
2333+
2334+#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PLE_TOP_FL_QUE_CTRL_3_ADDR
2335+#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF // QUEUE_PKT_NUM[11..0]
2336+#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0
2337+
2338+/* PSE */
2339+#define WF_PSE_TOP_BASE 0x820c8000
2340+
2341+#define WF_PSE_TOP_PBUF_CTRL_ADDR (WF_PSE_TOP_BASE + 0x04) // 8004
2342+#define WF_PSE_TOP_QUEUE_EMPTY_ADDR (WF_PSE_TOP_BASE + 0xB0) // 80B0
2343+#define WF_PSE_TOP_QUEUE_EMPTY_1_ADDR (WF_PSE_TOP_BASE + 0xBC) // 80BC
2344+#define WF_PSE_TOP_PG_HIF0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x110) // 8110
2345+#define WF_PSE_TOP_PG_HIF1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x114) // 8114
2346+#define WF_PSE_TOP_PG_CPU_GROUP_ADDR (WF_PSE_TOP_BASE + 0x118) // 8118
2347+#define WF_PSE_TOP_PG_PLE_GROUP_ADDR (WF_PSE_TOP_BASE + 0x11C) // 811C
2348+#define WF_PSE_TOP_PG_PLE1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x120) // 8120
2349+#define WF_PSE_TOP_PG_LMAC0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x124) // 8124
2350+#define WF_PSE_TOP_PG_LMAC1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x128) // 8128
2351+#define WF_PSE_TOP_PG_LMAC2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x12C) // 812C
2352+#define WF_PSE_TOP_PG_LMAC3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x130) // 8130
2353+#define WF_PSE_TOP_PG_MDP_GROUP_ADDR (WF_PSE_TOP_BASE + 0x134) // 8134
2354+#define WF_PSE_TOP_PG_MDP2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x13C) // 813C
2355+#define WF_PSE_TOP_PG_HIF2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x140) // 8140
2356+#define WF_PSE_TOP_PG_MDP3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x144) // 8144
2357+#define WF_PSE_TOP_HIF0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x150) // 8150
2358+#define WF_PSE_TOP_HIF1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x154) // 8154
2359+#define WF_PSE_TOP_CPU_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x158) // 8158
2360+#define WF_PSE_TOP_PLE_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x15C) // 815C
2361+#define WF_PSE_TOP_PLE1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x160) // 8160
2362+#define WF_PSE_TOP_LMAC0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x164) // 8164
2363+#define WF_PSE_TOP_LMAC1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x168) // 8168
2364+#define WF_PSE_TOP_LMAC2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x16C) // 816C
2365+#define WF_PSE_TOP_LMAC3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x170) // 8170
2366+#define WF_PSE_TOP_MDP_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x174) // 8174
2367+#define WF_PSE_TOP_MDP2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x17C) // 817C
2368+#define WF_PSE_TOP_HIF2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x180) // 8180
2369+#define WF_PSE_TOP_MDP3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x184) // 8184
2370+#define WF_PSE_TOP_FL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1B0) // 81B0
2371+#define WF_PSE_TOP_FL_QUE_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1B4) // 81B4
2372+#define WF_PSE_TOP_FL_QUE_CTRL_2_ADDR (WF_PSE_TOP_BASE + 0x1B8) // 81B8
2373+#define WF_PSE_TOP_FL_QUE_CTRL_3_ADDR (WF_PSE_TOP_BASE + 0x1BC) // 81BC
2374+#define WF_PSE_TOP_FREEPG_CNT_ADDR (WF_PSE_TOP_BASE + 0x380) // 8380
2375+#define WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PSE_TOP_BASE + 0x384) // 8384
2376+
2377+#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR
2378+#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31]
2379+#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31
2380+#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR
2381+#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 // PBUF_OFFSET[25..17]
2382+#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17
2383+#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR
2384+#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF // TOTAL_PAGE_NUM[11..0]
2385+#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0
2386+
2387+#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2388+#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK 0x80000000 // RLS_Q_EMTPY[31]
2389+#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT 31
2390+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2391+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_MASK 0x10000000 // CPU_Q4_EMPTY[28]
2392+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_SHFT 28
2393+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2394+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_MASK 0x08000000 // MDP_RXIOC1_QUEUE_EMPTY[27]
2395+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_SHFT 27
2396+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2397+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_MASK 0x04000000 // MDP_TXIOC1_QUEUE_EMPTY[26]
2398+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_SHFT 26
2399+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2400+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_MASK 0x02000000 // SEC_TX1_QUEUE_EMPTY[25]
2401+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_SHFT 25
2402+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2403+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_MASK 0x01000000 // MDP_TX1_QUEUE_EMPTY[24]
2404+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_SHFT 24
2405+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2406+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK 0x00800000 // MDP_RXIOC_QUEUE_EMPTY[23]
2407+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT 23
2408+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2409+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK 0x00400000 // MDP_TXIOC_QUEUE_EMPTY[22]
2410+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT 22
2411+#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2412+#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK 0x00200000 // SFD_PARK_QUEUE_EMPTY[21]
2413+#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT 21
2414+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2415+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK 0x00100000 // SEC_RX_QUEUE_EMPTY[20]
2416+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT 20
2417+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2418+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK 0x00080000 // SEC_TX_QUEUE_EMPTY[19]
2419+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT 19
2420+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2421+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK 0x00040000 // MDP_RX_QUEUE_EMPTY[18]
2422+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT 18
2423+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2424+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK 0x00020000 // MDP_TX_QUEUE_EMPTY[17]
2425+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT 17
2426+#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2427+#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK 0x00010000 // LMAC_TX_QUEUE_EMPTY[16]
2428+#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT 16
2429+
2430+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2431+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK 0x00000008 // CPU_Q3_EMPTY[3]
2432+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT 3
2433+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2434+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK 0x00000004 // CPU_Q2_EMPTY[2]
2435+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT 2
2436+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2437+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK 0x00000002 // CPU_Q1_EMPTY[1]
2438+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT 1
2439+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
2440+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK 0x00000001 // CPU_Q0_EMPTY[0]
2441+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT 0
2442+
2443+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2444+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_MASK 0x20000000 // HIF_13_EMPTY[29]
2445+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_SHFT 29
2446+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2447+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_MASK 0x10000000 // HIF_12_EMPTY[28]
2448+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_SHFT 28
2449+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2450+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_MASK 0x08000000 // HIF_11_EMPTY[27]
2451+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_SHFT 27
2452+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2453+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_MASK 0x04000000 // HIF_10_EMPTY[26]
2454+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_SHFT 26
2455+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2456+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_MASK 0x02000000 // HIF_9_EMPTY[25]
2457+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_SHFT 25
2458+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2459+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_MASK 0x01000000 // HIF_8_EMPTY[24]
2460+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_SHFT 24
2461+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2462+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_MASK 0x00800000 // HIF_7_EMPTY[23]
2463+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_SHFT 23
2464+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2465+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_MASK 0x00400000 // HIF_6_EMPTY[22]
2466+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_SHFT 22
2467+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2468+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_MASK 0x00200000 // HIF_5_EMPTY[21]
2469+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_SHFT 21
2470+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2471+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_MASK 0x00100000 // HIF_4_EMPTY[20]
2472+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_SHFT 20
2473+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2474+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_MASK 0x00080000 // HIF_3_EMPTY[19]
2475+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_SHFT 19
2476+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2477+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_MASK 0x00040000 // HIF_2_EMPTY[18]
2478+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_SHFT 18
2479+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2480+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_MASK 0x00020000 // HIF_1_EMPTY[17]
2481+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_SHFT 17
2482+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2483+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_MASK 0x00010000 // HIF_0_EMPTY[16]
2484+#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_SHFT 16
2485+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2486+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_MASK 0x00008000 // MDP_RXIOC3_QUEUE_EMPTY[15]
2487+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_SHFT 15
2488+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2489+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_MASK 0x00000800 // MDP_RXIOC2_QUEUE_EMPTY[11]
2490+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_SHFT 11
2491+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2492+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_MASK 0x00000400 // MDP_TXIOC2_QUEUE_EMPTY[10]
2493+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_SHFT 10
2494+#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2495+#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_MASK 0x00000200 // SEC_TX2_QUEUE_EMPTY[9]
2496+#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_SHFT 9
2497+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR
2498+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_MASK 0x00000100 // MDP_TX2_QUEUE_EMPTY[8]
2499+#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_SHFT 8
2500+
2501+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR
2502+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK 0x0FFF0000 // HIF0_MAX_QUOTA[27..16]
2503+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT 16
2504+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR
2505+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK 0x00000FFF // HIF0_MIN_QUOTA[11..0]
2506+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT 0
2507+
2508+
2509+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR
2510+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK 0x0FFF0000 // HIF1_MAX_QUOTA[27..16]
2511+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT 16
2512+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR
2513+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK 0x00000FFF // HIF1_MIN_QUOTA[11..0]
2514+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT 0
2515+
2516+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR
2517+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 // CPU_MAX_QUOTA[27..16]
2518+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16
2519+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR
2520+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF // CPU_MIN_QUOTA[11..0]
2521+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0
2522+
2523+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR
2524+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK 0x0FFF0000 // PLE_MAX_QUOTA[27..16]
2525+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT 16
2526+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR