developer | a556978 | 2022-05-06 11:04:59 +0800 | [diff] [blame] | 1 | --- a/drivers/crypto/inside-secure/safexcel.c |
| 2 | +++ b/drivers/crypto/inside-secure/safexcel.c |
| 3 | @@ -304,6 +304,11 @@ |
| 4 | /* Enable access to all IFPP program memories */ |
| 5 | writel(EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN, |
| 6 | EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe)); |
| 7 | + |
| 8 | + /* bypass the OCE, if present */ |
| 9 | + if (priv->flags & EIP197_OCE) |
| 10 | + writel(EIP197_DEBUG_OCE_BYPASS, EIP197_PE(priv) + |
| 11 | + EIP197_PE_DEBUG(pe)); |
| 12 | } |
| 13 | |
| 14 | } |
| 15 | @@ -409,7 +414,7 @@ |
| 16 | dir = "eip197d"; |
| 17 | else if (priv->version == EIP197B_MRVL || |
| 18 | priv->version == EIP197_DEVBRD) |
| 19 | - dir = "eip197b"; |
| 20 | + dir = "eip197_minifw"; |
| 21 | else |
| 22 | return -ENODEV; |
| 23 | |
| 24 | @@ -792,6 +797,12 @@ |
| 25 | return ret; |
| 26 | } |
| 27 | |
| 28 | + /* Allow clocks to be forced on for EIP197 */ |
| 29 | + if (priv->flags & SAFEXCEL_HW_EIP197) { |
| 30 | + writel(0xffffffff, EIP197_HIA_GEN_CFG(priv) + EIP197_FORCE_CLOCK_ON); |
| 31 | + writel(0xffffffff, EIP197_HIA_GEN_CFG(priv) + EIP197_FORCE_CLOCK_ON2); |
| 32 | + } |
| 33 | + |
| 34 | return safexcel_hw_setup_cdesc_rings(priv) ?: |
| 35 | safexcel_hw_setup_rdesc_rings(priv) ?: |
| 36 | 0; |
| 37 | @@ -1498,6 +1509,9 @@ |
| 38 | hwopt = readl(EIP197_GLOBAL(priv) + EIP197_OPTIONS); |
| 39 | hiaopt = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_OPTIONS); |
| 40 | |
| 41 | + priv->hwconfig.icever = 0; |
| 42 | + priv->hwconfig.ocever = 0; |
| 43 | + priv->hwconfig.psever = 0; |
| 44 | if (priv->flags & SAFEXCEL_HW_EIP197) { |
| 45 | /* EIP197 */ |
| 46 | peopt = readl(EIP197_PE(priv) + EIP197_PE_OPTIONS(0)); |
| 47 | @@ -1516,8 +1530,37 @@ |
| 48 | EIP197_N_RINGS_MASK; |
| 49 | if (hiaopt & EIP197_HIA_OPT_HAS_PE_ARB) |
| 50 | priv->flags |= EIP197_PE_ARB; |
| 51 | - if (EIP206_OPT_ICE_TYPE(peopt) == 1) |
| 52 | + if (EIP206_OPT_ICE_TYPE(peopt) == 1) { |
| 53 | priv->flags |= EIP197_ICE; |
| 54 | + /* Detect ICE EIP207 class. engine and version */ |
| 55 | + version = readl(EIP197_PE(priv) + |
| 56 | + EIP197_PE_ICE_VERSION(0)); |
| 57 | + if (EIP197_REG_LO16(version) != EIP207_VERSION_LE) { |
| 58 | + dev_err(dev, "EIP%d: ICE EIP207 not detected.\n", |
| 59 | + peid); |
| 60 | + return -ENODEV; |
| 61 | + } |
| 62 | + priv->hwconfig.icever = EIP197_VERSION_MASK(version); |
| 63 | + } |
| 64 | + if (EIP206_OPT_OCE_TYPE(peopt) == 1) { |
| 65 | + priv->flags |= EIP197_OCE; |
| 66 | + /* Detect EIP96PP packet stream editor and version */ |
| 67 | + version = readl(EIP197_PE(priv) + EIP197_PE_PSE_VERSION(0)); |
| 68 | + if (EIP197_REG_LO16(version) != EIP96_VERSION_LE) { |
| 69 | + dev_err(dev, "EIP%d: EIP96PP not detected.\n", peid); |
| 70 | + return -ENODEV; |
| 71 | + } |
| 72 | + priv->hwconfig.psever = EIP197_VERSION_MASK(version); |
| 73 | + /* Detect OCE EIP207 class. engine and version */ |
| 74 | + version = readl(EIP197_PE(priv) + |
| 75 | + EIP197_PE_ICE_VERSION(0)); |
| 76 | + if (EIP197_REG_LO16(version) != EIP207_VERSION_LE) { |
| 77 | + dev_err(dev, "EIP%d: OCE EIP207 not detected.\n", |
| 78 | + peid); |
| 79 | + return -ENODEV; |
| 80 | + } |
| 81 | + priv->hwconfig.ocever = EIP197_VERSION_MASK(version); |
| 82 | + } |
| 83 | /* If not a full TRC, then assume simple TRC */ |
| 84 | if (!(hwopt & EIP197_OPT_HAS_TRC)) |
| 85 | priv->flags |= EIP197_SIMPLE_TRC; |
| 86 | @@ -1555,13 +1598,14 @@ |
| 87 | EIP197_PE_EIP96_OPTIONS(0)); |
| 88 | |
| 89 | /* Print single info line describing what we just detected */ |
| 90 | - dev_info(priv->dev, "EIP%d:%x(%d,%d,%d,%d)-HIA:%x(%d,%d,%d),PE:%x/%x,alg:%08x\n", |
| 91 | + dev_info(priv->dev, "EIP%d:%x(%d,%d,%d,%d)-HIA:%x(%d,%d,%d),PE:%x/%x(alg:%08x)/%x/%x/%x\n", |
| 92 | peid, priv->hwconfig.hwver, hwctg, priv->hwconfig.hwnumpes, |
| 93 | priv->hwconfig.hwnumrings, priv->hwconfig.hwnumraic, |
| 94 | priv->hwconfig.hiaver, priv->hwconfig.hwdataw, |
| 95 | priv->hwconfig.hwcfsize, priv->hwconfig.hwrfsize, |
| 96 | priv->hwconfig.ppver, priv->hwconfig.pever, |
| 97 | - priv->hwconfig.algo_flags); |
| 98 | + priv->hwconfig.algo_flags, priv->hwconfig.icever, |
| 99 | + priv->hwconfig.ocever, priv->hwconfig.psever); |
| 100 | |
| 101 | safexcel_configure(priv); |
| 102 | |
| 103 | @@ -1690,6 +1734,7 @@ |
| 104 | { |
| 105 | struct device *dev = &pdev->dev; |
| 106 | struct safexcel_crypto_priv *priv; |
| 107 | + struct resource *res; |
| 108 | int ret; |
| 109 | |
| 110 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
| 111 | @@ -1701,7 +1746,11 @@ |
| 112 | |
| 113 | platform_set_drvdata(pdev, priv); |
| 114 | |
| 115 | - priv->base = devm_platform_ioremap_resource(pdev, 0); |
| 116 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 117 | + if (!res) |
| 118 | + return -EINVAL; |
| 119 | + |
| 120 | + priv->base = devm_ioremap(dev, res->start, resource_size(res)); |
| 121 | if (IS_ERR(priv->base)) { |
| 122 | dev_err(dev, "failed to get resource\n"); |
| 123 | return PTR_ERR(priv->base); |
| 124 | --- a/drivers/crypto/inside-secure/safexcel.h |
| 125 | +++ b/drivers/crypto/inside-secure/safexcel.h |
| 126 | @@ -22,6 +22,7 @@ |
| 127 | #define EIP96_VERSION_LE 0x9f60 |
| 128 | #define EIP201_VERSION_LE 0x36c9 |
| 129 | #define EIP206_VERSION_LE 0x31ce |
| 130 | +#define EIP207_VERSION_LE 0x30cf |
| 131 | #define EIP197_REG_LO16(reg) (reg & 0xffff) |
| 132 | #define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff) |
| 133 | #define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff) |
| 134 | @@ -34,6 +35,7 @@ |
| 135 | |
| 136 | /* EIP206 OPTIONS ENCODING */ |
| 137 | #define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3) |
| 138 | +#define EIP206_OPT_OCE_TYPE(n) ((n>>10)&3) |
| 139 | |
| 140 | /* EIP197 OPTIONS ENCODING */ |
| 141 | #define EIP197_OPT_HAS_TRC BIT(31) |
| 142 | @@ -168,6 +170,7 @@ |
| 143 | #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n))) |
| 144 | #define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n))) |
| 145 | #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n))) |
| 146 | +#define EIP197_PE_ICE_VERSION(n) (0x0ffc + (0x2000 * (n))) |
| 147 | #define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n))) |
| 148 | #define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n))) |
| 149 | #define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n))) |
| 150 | @@ -176,10 +179,15 @@ |
| 151 | #define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n))) |
| 152 | #define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n))) |
| 153 | #define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n))) |
| 154 | +#define EIP197_PE_OCE_VERSION(n) (0x1bfc + (0x2000 * (n))) |
| 155 | #define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n))) |
| 156 | #define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n))) |
| 157 | +#define EIP197_PE_PSE_VERSION(n) (0x1efc + (0x2000 * (n))) |
| 158 | +#define EIP197_PE_DEBUG(n) (0x1ff4 + (0x2000 * (n))) |
| 159 | #define EIP197_PE_OPTIONS(n) (0x1ff8 + (0x2000 * (n))) |
| 160 | #define EIP197_PE_VERSION(n) (0x1ffc + (0x2000 * (n))) |
| 161 | +#define EIP197_FORCE_CLOCK_ON2 0xffd8 |
| 162 | +#define EIP197_FORCE_CLOCK_ON 0xffe8 |
| 163 | #define EIP197_MST_CTRL 0xfff4 |
| 164 | #define EIP197_OPTIONS 0xfff8 |
| 165 | #define EIP197_VERSION 0xfffc |
| 166 | @@ -353,6 +361,9 @@ |
| 167 | /* EIP197_PE_EIP96_TOKEN_CTRL2 */ |
| 168 | #define EIP197_PE_EIP96_TOKEN_CTRL2_CTX_DONE BIT(3) |
| 169 | |
| 170 | +/* EIP197_PE_DEBUG */ |
| 171 | +#define EIP197_DEBUG_OCE_BYPASS BIT(1) |
| 172 | + |
| 173 | /* EIP197_STRC_CONFIG */ |
| 174 | #define EIP197_STRC_CONFIG_INIT BIT(31) |
| 175 | #define EIP197_STRC_CONFIG_LARGE_REC(s) (s<<8) |
| 176 | @@ -777,6 +788,7 @@ |
| 177 | EIP197_PE_ARB = BIT(2), |
| 178 | EIP197_ICE = BIT(3), |
| 179 | EIP197_SIMPLE_TRC = BIT(4), |
| 180 | + EIP197_OCE = BIT(5), |
| 181 | }; |
| 182 | |
| 183 | struct safexcel_hwconfig { |
| 184 | @@ -784,7 +796,10 @@ |
| 185 | int hwver; |
| 186 | int hiaver; |
| 187 | int ppver; |
| 188 | + int icever; |
| 189 | int pever; |
| 190 | + int ocever; |
| 191 | + int psever; |
| 192 | int hwdataw; |
| 193 | int hwcfsize; |
| 194 | int hwrfsize; |