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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / d757709539f12c69b9a90f9c291e1987e1fa557a / . / package-21.02 / kernel / crypto-eip / src / ddk / kit / eip197 / eip202_global_init.c
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developer02e65912023-08-17 16:33:10 +0800[diff] [blame]1/* eip202_global_init.c
2 *
3 * EIP-202 Global Control Driver Library
4 * Initialization Module
5 */
6
7/* -------------------------------------------------------------------------- */
8/* */
9/* Module : ddk197 */
10/* Version : 5.6.1 */
11/* Configuration : DDK-197-GPL */
12/* */
13/* Date : 2022-Dec-16 */
14/* */
15/* Copyright (c) 2008-2022 by Rambus, Inc. and/or its subsidiaries. */
16/* */
17/* This program is free software: you can redistribute it and/or modify */
18/* it under the terms of the GNU General Public License as published by */
19/* the Free Software Foundation, either version 2 of the License, or */
20/* any later version. */
21/* */
22/* This program is distributed in the hope that it will be useful, */
23/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
24/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
25/* GNU General Public License for more details. */
26/* */
27/* You should have received a copy of the GNU General Public License */
28/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
29/* -------------------------------------------------------------------------- */
30
31/*----------------------------------------------------------------------------
32 * This module implements (provides) the following interface(s):
33 */
34
35#include "eip202_global_init.h"
36
37/*----------------------------------------------------------------------------
38 * This module uses (requires) the following interface(s):
39 */
40
41// Default configuration
42#include "c_eip97_global.h"
43
44// Driver Framework Basic Definitions API
45#include "basic_defs.h" // uint32_t
46
47// Driver Framework C Run-time Library API
48#include "clib.h" // ZEROINIT
49
50// Driver Framework Device API
51#include "device_types.h" // Device_Handle_t
52
53#include "eip202_global_level0.h" // EIP-202 Level 0 macros
54
55// EIP97_Interfaces_Get
56#include "eip97_global_internal.h"
57
58/*----------------------------------------------------------------------------
59 * Definitions and macros
60 */
61
62
63/*----------------------------------------------------------------------------
64 * Local variables
65 */
66
67
68/*----------------------------------------------------------------------------
69 * EIP202_Global_Detect
70 */
71bool
72EIP202_Global_Detect(
73 const Device_Handle_t Device)
74{
75 uint32_t Value;
76
77 Value = EIP202_Read32(Device, EIP202_G_REG_VERSION);
78 if (!EIP202_REV_SIGNATURE_MATCH( Value ))
79 return false;
80
81 return true;
82}
83
84
85
86
87/*----------------------------------------------------------------------------
88 * EIP202_Global_HWRevision_Get
89 */
90void
91EIP202_Global_HWRevision_Get(
92 const Device_Handle_t Device,
93 EIP202_Capabilities_t * const Capabilities_p)
94{
95 EIP202_EIP_REV_RD(Device,
96 &Capabilities_p->EipNumber,
97 &Capabilities_p->ComplmtEipNumber,
98 &Capabilities_p->HWPatchLevel,
99 &Capabilities_p->MinHWRevision,
100 &Capabilities_p->MajHWRevision);
101
102 EIP202_OPTIONS_RD(Device,
103 &Capabilities_p->NofRings,
104 &Capabilities_p->NofPes,
105 &Capabilities_p->fExpPlf,
106 &Capabilities_p->CF_Size,
107 &Capabilities_p->RF_Size,
108 &Capabilities_p->HostIfc,
109 &Capabilities_p->DMA_Len,
110 &Capabilities_p->HDW,
111 &Capabilities_p->TgtAlign,
112 &Capabilities_p->fAddr64);
113
114 EIP202_OPTIONS2_RD(Device,
115 &Capabilities_p->NofLA_Ifs,
116 &Capabilities_p->NofIN_Ifs,
117 &Capabilities_p->NofAXI_WrChs,
118 &Capabilities_p->NofAXI_RdClusters,
119 &Capabilities_p->NofAXI_RdCPC);
120}
121
122
123/*----------------------------------------------------------------------------
124 * EIP202_Global_Endianness_Slave_Configure
125 *
126 * Configure Endianness Conversion method
127 * for the EIP-202 slave (MMIO) interface
128 *
129 */
130bool
131EIP202_Global_Endianness_Slave_Configure(
132 const Device_Handle_t Device)
133{
134#ifdef EIP97_GLOBAL_ENABLE_SWAP_REG_DATA
135 uint32_t Value;
136
137 // Read and check the revision register
138 Value = EIP202_Read32(Device, EIP202_G_REG_VERSION);
139 if (!EIP202_REV_SIGNATURE_MATCH( Value ))
140 {
141 // No match, try to enable the Slave interface byte swap
142 // Must be done via EIP-202 HIA GLobal
143 EIP202_MST_CTRL_BYTE_SWAP_UPDATE(Device, true);
144
145 // Read and check the revision register again
146 Value = EIP202_Read32(Device, EIP202_G_REG_VERSION);
147 if (!EIP202_REV_SIGNATURE_MATCH( Value ))
148 // Bail out if still not OK
149 return false;
150 }
151
152 return true;
153#else
154 IDENTIFIER_NOT_USED(Device);
155 return true;
156#endif // EIP97_GLOBAL_ENABLE_SWAP_REG_DATA
157}
158
159
160/*----------------------------------------------------------------------------
161 * EIP202_Global_Init
162 */
163void
164EIP202_Global_Init(
165 const Device_Handle_t Device,
166 unsigned int NofPE,
167 unsigned int NofLA,
168 uint8_t ipbuf_min,
169 uint8_t ipbuf_max,
170 uint8_t itbuf_min,
171 uint8_t itbuf_max,
172 uint8_t opbuf_min,
173 uint8_t opbuf_max)
174{
175 unsigned int i;
176 uint8_t BufferCtrl;
177 unsigned int NofPEs,NofRings,NofLAs,NofIN,DFEDSEOffset;
178 EIP97_Interfaces_Get(&NofPEs,&NofRings,&NofLAs,&NofIN);
179 DFEDSEOffset = EIP97_DFEDSE_Offset_Get();
180
181 // Configure EIP-202 HIA Global
182 EIP202_MST_CTRL_BUS_BURST_SIZE_UPDATE(Device,
183 EIP97_GLOBAL_BUS_BURST_SIZE,
184 EIP97_GLOBAL_RX_BUS_BURST_SIZE);
185 EIP202_MST_CTRL_BUS_TIMEOUT_UPDATE(Device,
186 EIP97_GLOBAL_TIMEOUT_VALUE);
187 if (NofLA)
188 // User-configured value
189 BufferCtrl = EIP97_GLOBAL_DSE_BUFFER_CTRL;
190 else
191 // Default register reset value
192 BufferCtrl = (uint8_t)EIP202_DSE_BUFFER_CTRL;
193
194 for (i = 0; i < NofPE; i++)
195 {
196 // Configure EIP-202 HIA DFE Global
197 EIP202_DFE_CFG_WR(Device,
198 DFEDSEOffset,
199 i,
200 ipbuf_min,
201 EIP97_GLOBAL_DFE_DATA_CACHE_CTRL,
202 ipbuf_max,
203 itbuf_min,
204 EIP97_GLOBAL_DFE_CTRL_CACHE_CTRL,
205 itbuf_max,
206 (EIP97_GLOBAL_DFE_ADV_THRESH_MODE_FLAG == 1),
207 (EIP97_GLOBAL_DFE_AGGRESSIVE_DMA_FLAG == 1));
208
209 // Configure EIP-202 HIA DSE Global
210 EIP202_DSE_CFG_WR(Device,
211 DFEDSEOffset,
212 i,
213 opbuf_min,
214 EIP97_GLOBAL_DSE_DATA_CACHE_CTRL,
215 opbuf_max,
216 BufferCtrl,
217 (EIP97_GLOBAL_DSE_ENABLE_SINGLE_WR_FLAG == 1),
218 (EIP97_GLOBAL_DSE_AGGRESSIVE_DMA_FLAG == 1));
219
220 }
221
222 // Configure HIA Look-aside FIFO
223 EIP202_LASIDE_BASE_ADDR_LO_WR(Device,
224 EIP202_LASIDE_DSCR_BYTE_SWAP_METHOD);
225
226 for (i = EIP97_GLOBAL_LAFIFO_RING_ID;
227 i < NofLAs +
228 EIP97_GLOBAL_LAFIFO_RING_ID;
229 i++)
230 {
231 EIP202_LASIDE_SLAVE_CTRL_WR(Device,
232 i,
233 EIP202_LASIDE_IN_PKT_BYTE_SWAP_METHOD,
234 EIP202_LASIDE_IN_PKT_PROTO,
235 EIP202_LASIDE_TOKEN_BYTE_SWAP_METHOD,
236 EIP202_LASIDE_TOKEN_PROTO,
237 true); // Clear cmd descriptor error
238
239 EIP202_LASIDE_MASTER_CTRL_WR(Device,
240 i,
241 EIP202_LASIDE_OUT_PKT_BYTE_SWAP_METHOD,
242 EIP202_LASIDE_OUT_PKT_PROTO,
243 true); // Clear res descriptor error
244 }
245 // Configure HIA Inline FIFO
246 for (i = 0; i < NofIN; i++)
247 EIP202_INLINE_CTRL_WR(Device,
248 i,
249 EIP202_INLINE_IN_PKT_BYTE_SWAP_METHOD,
250 false, // Clear protocol error
251 EIP202_INLINE_OUT_PKT_BYTE_SWAP_METHOD,
252 opbuf_min,
253 opbuf_max,
254 EIP202_INLINE_BURST_SIZE,
255 EIP202_INLINE_FORCE_INORDER);
256
257}
258
259
260/*----------------------------------------------------------------------------
261 * EIP202_Global_Reset
262 */
263bool
264EIP202_Global_Reset(
265 const Device_Handle_t Device,
266 const unsigned int NofPE)
267{
268 unsigned int i;
269 unsigned int DFEDSEOffset;
270 DFEDSEOffset = EIP97_DFEDSE_Offset_Get();
271
272 // Restore the EIP-202 default configuration
273 // Resets DFE thread and clears ring assignment
274 for (i = 0; i < NofPE; i++)
275 EIP202_DFE_TRD_CTRL_WR(Device, DFEDSEOffset, i, 0, false, true);
276
277 // HIA DFE defaults
278 for (i = 0; i < NofPE; i++)
279 EIP202_DFE_CFG_DEFAULT_WR(Device, DFEDSEOffset, i);
280
281#ifndef EIP202_RA_DISABLE
282 EIP202_RA_PRIO_0_DEFAULT_WR(Device);
283 EIP202_RA_PRIO_1_DEFAULT_WR(Device);
284 EIP202_RA_PRIO_2_DEFAULT_WR(Device);
285 EIP202_RA_PRIO_3_DEFAULT_WR(Device);
286
287 // Resets ring assignment
288 for (i = 0; i < NofPE; i++)
289 EIP202_RA_PE_CTRL_WR(Device, i, 0, false, true);
290#endif // #ifndef EIP202_RA_DISABLE
291
292 // Resets DSE thread and clears ring assignment
293 for (i = 0; i < NofPE; i++)
294 EIP202_DSE_TRD_CTRL_WR(Device, DFEDSEOffset, i, 0, false, true);
295
296 // HIA DSE defaults
297 for (i = 0; i < NofPE; i++)
298 EIP202_DSE_CFG_DEFAULT_WR(Device, DFEDSEOffset, i);
299
300
301 // HIA LASIDE defaults
302 EIP202_LASIDE_BASE_ADDR_LO_DEFAULT_WR(Device);
303 EIP202_LASIDE_BASE_ADDR_HI_DEFAULT_WR(Device);
304 for (i = EIP97_GLOBAL_LAFIFO_RING_ID;
305 i < EIP97_GLOBAL_MAX_NOF_LAFIFO_TO_USE + EIP97_GLOBAL_LAFIFO_RING_ID;
306 i++)
307 {
308 EIP202_LASIDE_MASTER_CTRL_DEFAULT_WR(Device, i);
309 EIP202_LASIDE_SLAVE_CTRL_DEFAULT_WR(Device, i);
310 }
311
312 // HIA INLINE defaults
313 for (i = 0; i < NofPE; i++)
314 EIP202_INLINE_CTRL_DEFAULT_WR(Device, i);
315 return true;
316}
317
318
319/*----------------------------------------------------------------------------
320 * EIP202_Global_Reset_IsDone
321 */
322bool
323EIP202_Global_Reset_IsDone(
324 const Device_Handle_t Device,
325 const unsigned int PEnr)
326{
327 uint8_t RingId;
328 unsigned int DFEDSEOffset;
329 DFEDSEOffset = EIP97_DFEDSE_Offset_Get();
330
331 // Check for completion of all DMA transfers
332 EIP202_DFE_TRD_STAT_RINGID_RD(Device, DFEDSEOffset, PEnr, &RingId);
333 if(RingId == EIP202_DFE_TRD_REG_STAT_IDLE)
334 {
335 EIP202_DSE_TRD_STAT_RINGID_RD(Device, DFEDSEOffset, PEnr, &RingId);
336 if(RingId == EIP202_DFE_TRD_REG_STAT_IDLE)
337 {
338 // Take DFE thread out of reset
339 EIP202_DFE_TRD_CTRL_DEFAULT_WR(Device, DFEDSEOffset, PEnr);
340
341 // Take DSE thread out of reset
342 EIP202_DSE_TRD_CTRL_DEFAULT_WR(Device, DFEDSEOffset, PEnr);
343
344 // Do not restore the EIP-202 Master Control default configuration
345 // so this will not change the endianness conversion configuration
346 // for the Slave interface
347 }
348 return true;
349 }
350 else
351 {
352 return false;
353 }
354}
355
356
357/*----------------------------------------------------------------------------
358 * EIP202_Global_Configure
359 */
360void
361EIP202_Global_Configure(
362 const Device_Handle_t Device,
363 const unsigned int PE_Number,
364 const EIP202_Global_Ring_PE_Map_t * const RingPEMap_p)
365{
366 unsigned int DFEDSEOffset;
367 DFEDSEOffset = EIP97_DFEDSE_Offset_Get();
368 // Disable EIP-202 HIA DFE thread(s)
369 EIP202_DFE_TRD_CTRL_WR(Device,
370 DFEDSEOffset,
371 PE_Number, // Thread Nr
372 0,
373 false, // Disable thread
374 false); // Do not reset thread
375
376 // Disable EIP-202 HIA DSE thread(s)
377 EIP202_DSE_TRD_CTRL_WR(Device,
378 DFEDSEOffset,
379 PE_Number, // Thread Nr
380 0,
381 false, // Disable thread
382 false); // Do not reset thread
383
384#ifndef EIP202_RA_DISABLE
385 // Configure the HIA Ring Arbiter
386 EIP202_RA_PRIO_0_WR(
387 Device,
388 (RingPEMap_p->RingPrio_Mask & BIT_0) == 0 ? false : true,
389 (uint8_t)(RingPEMap_p->RingSlots0 & MASK_4_BITS),
390 (RingPEMap_p->RingPrio_Mask & BIT_1) == 0 ? false : true,
391 (uint8_t)((RingPEMap_p->RingSlots0 >> 4) & MASK_4_BITS),
392 (RingPEMap_p->RingPrio_Mask & BIT_2) == 0 ? false : true,
393 (uint8_t)((RingPEMap_p->RingSlots0 >> 8) & MASK_4_BITS),
394 (RingPEMap_p->RingPrio_Mask & BIT_3) == 0 ? false : true,
395 (uint8_t)((RingPEMap_p->RingSlots0 >> 12) & MASK_4_BITS));
396
397 EIP202_RA_PRIO_1_WR(
398 Device,
399 (RingPEMap_p->RingPrio_Mask & BIT_4) == 0 ? false : true,
400 (uint8_t)((RingPEMap_p->RingSlots0 >> 16) & MASK_4_BITS),
401 (RingPEMap_p->RingPrio_Mask & BIT_5) == 0 ? false : true,
402 (uint8_t)((RingPEMap_p->RingSlots0 >> 20) & MASK_4_BITS),
403 (RingPEMap_p->RingPrio_Mask & BIT_6) == 0 ? false : true,
404 (uint8_t)((RingPEMap_p->RingSlots0 >> 24) & MASK_4_BITS),
405 (RingPEMap_p->RingPrio_Mask & BIT_7) == 0 ? false : true,
406 (uint8_t)((RingPEMap_p->RingSlots0 >> 28) & MASK_4_BITS));
407
408 EIP202_RA_PRIO_2_WR(
409 Device,
410 (RingPEMap_p->RingPrio_Mask & BIT_8) == 0 ? false : true,
411 (uint8_t)(RingPEMap_p->RingSlots1 & MASK_4_BITS),
412 (RingPEMap_p->RingPrio_Mask & BIT_9) == 0 ? false : true,
413 (uint8_t)((RingPEMap_p->RingSlots1 >> 4) & MASK_4_BITS),
414 (RingPEMap_p->RingPrio_Mask & BIT_10) == 0 ? false : true,
415 (uint8_t)((RingPEMap_p->RingSlots1 >> 8) & MASK_4_BITS),
416 (RingPEMap_p->RingPrio_Mask & BIT_11) == 0 ? false : true,
417 (uint8_t)((RingPEMap_p->RingSlots1 >> 12) & MASK_4_BITS));
418
419 EIP202_RA_PRIO_3_WR(
420 Device,
421 (RingPEMap_p->RingPrio_Mask & BIT_12) == 0 ? false : true,
422 (uint8_t)((RingPEMap_p->RingSlots1 >> 16) & MASK_4_BITS),
423 (RingPEMap_p->RingPrio_Mask & BIT_13) == 0 ? false : true,
424 (uint8_t)((RingPEMap_p->RingSlots1 >> 20) & MASK_4_BITS),
425 (RingPEMap_p->RingPrio_Mask & BIT_14) == 0 ? false : true,
426 (uint8_t)((RingPEMap_p->RingSlots1 >> 24) & MASK_4_BITS));
427
428 // Ring assignment in the Ring Arbiter
429 EIP202_RA_PE_CTRL_WR(Device,
430 PE_Number,
431 RingPEMap_p->RingPE_Mask,
432 true,
433 false);
434#endif // #ifndef EIP202_RA_DISABLE
435
436 {
437 // Assign Rings to this DFE thread
438 // Enable EIP-202 HIA DFE thread(s)
439 EIP202_DFE_TRD_CTRL_WR(Device,
440 DFEDSEOffset,
441 PE_Number, // Thread Nr
442 RingPEMap_p->RingPE_Mask, // Rings to assign
443 true, // Enable thread
444 false); // Do not reset thread
445
446 // Assign Rings to this DSE thread
447 // Enable EIP-202 HIA DSE thread(s)
448 EIP202_DSE_TRD_CTRL_WR(Device,
449 DFEDSEOffset,
450 PE_Number, // Thread Nr
451 RingPEMap_p->RingPE_Mask, // Rings to assign
452 true, // Enable thread
453 false); // Do not reset thread
454 }
455}
456
457/* end of file eip202_global_init.c */